net: stmmac: dwmac-mediatek: modify csr_clk value to fix mdio read/write fail

Browse source

1. the frequency of csr clock is 66.5MHz, so the csr_clk value should
be 0 other than 5.
2. the csr_clk can be got from device tree, so remove initialization here.

Fixes: 9992f37e34 ("stmmac: dwmac-mediatek: add support for mt2712")
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

...

This commit is contained in:

Biao Huang 2019-05-24 14:26:09 +08:00 • committed by David S. Miller

parent 5e7f7fc538

commit f4ca7a9260

1 changed files with 0 additions and 2 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

2

drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c

View file