clk: renesas: rcar-gen4: Remove unused fixed PLL clock types

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All users of the fixed default PLL2/3/4/6 clock types have been
converted to fixed or variable fractional PLL clock types.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/c0229eb3518444f61173c6fb83bdcedb058dd079.1721648548.git.geert+renesas@glider.be

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Geert Uytterhoeven 2024-07-22 13:50:34 +02:00

parent ccdf745bd1

commit f7444f0fde

2 changed files with 0 additions and 24 deletions

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20

drivers/clk/renesas/rcar-gen4-cpg.c

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4

drivers/clk/renesas/rcar-gen4-cpg.h

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