drm/i915/cx0: Clear response ready & error bit

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Clear the response ready and error bit of PORT_P2M_MESSAGE_BUS_STATUS
before writing the transaction pending bit of
PORT_M2P_MSGBUS_CTL as that is a hard requirement. If not done
we find that the PHY hangs since it ends up in a weird state if left
idle for more than 1 hour.

Bspec: 65101
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
Link: https://patch.msgid.link/20260122044859.753682-1-suraj.kandpal@intel.com

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Suraj Kandpal 2026-01-22 10:18:58 +05:30

parent cca7eda1c7

commit f86bed1bc9

1 changed files with 4 additions and 0 deletions

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drivers/gpu/drm/i915/display/intel_cx0_phy.c

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