spi: cadence: Add Marvell xSPI interrupt changes

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It is possible that before enabling interrupt, interrupt bit will be
set. It might cause improper IRQ handler behaviour. To fix it, clear
interrupt bit before enabling interrupts. That behaviour is specific to
Marvell xSPI implementation.
In addition in Marvell xSPI interrupt must be cleared in two places -
xSPI itself, and Marvell overlay.

Signed-off-by: Witold Sadowski <wsadowski@marvell.com>
Link: https://patch.msgid.link/20240724154739.582367-6-wsadowski@marvell.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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Witold Sadowski 2024-07-24 08:47:35 -07:00 • committed by Mark Brown

parent 75128e2a14

commit fa7279acef

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drivers/spi/spi-cadence-xspi.c

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