drm/msm/dsi: Populate the 10nm PHY funcs

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Populate the PHY ops with the downstream driver as reference.

There are a couple of TODOs which need to be resolved:
- The PHY timings are all hardcoded for now. This needs to be replaced
  with automatic calculations once we get/understand them.
- There are some lane configuration registers which use a new
  representation between physical and logical lane mappings. For now,
  we've hardcoced them to follow the default mapping (i.e
  logical 0 -> phy 0, logical 1 -> phy 1 etc).

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

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Archit Taneja 2018-01-17 11:35:27 +05:30 • committed by Rob Clark

parent 28e4309ab9

commit ff73ff1940

1 changed files with 199 additions and 0 deletions

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drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c

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