Route GFX user queue resets through amdgpu_gfx_reset_mes_gfx() when
HQD detection and PER_PIPE are available, preserving collateral kernel
rings across a pipe reset.
If the HQD cannot be located, use MES packet reset and protect kernel
rings on all GFX pipes.
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The user queue UAPI permits the WPTR at any 8-byte aligned offset within a
BO. amdgpu_userq_fence_read_wptr() locates the mapping containing the WPTR
address, but amdgpu_bo_kmap() returns the start of the BO, so the code read
the first u64 regardless of the WPTR offset. USERQ_SIGNAL uses this value as
the exported fence seqno, so a wrong read makes the fence signal early (or
never), breaking dependency synchronization.
Translate the WPTR GPU address to a byte offset within the BO, accounting
for the VA mapping start and the mapping's BO offset, before reading it.
Fixes: a292fdecd7 ("drm/amdgpu: Implement userqueue signal/wait IOCTL")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
In gmc_v12_0_flush_gpu_tlb(), flush_type was not properly
passed to gmc_v12_0_flush_vm_hub(). This only affected
the MMIO path. In most cases the flush would go through
MES.
Reviewed-by: Mukul Joshi <mukul.joshi@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add the MES firmware debug-extension ("mes_dbgext") API definitions to
the shared MES v11 and v12 interface headers: the
MESAPI_MISC__SETUP_MES_DBGEXT misc opcode, the MES_DBGEXT_INIT_DATA
struct (log buffer MC address + option bits), and the corresponding
dbgext_init_data member of union MESAPI__MISC.
These describe the SETUP_MES_DBGEXT packet the firmware expects and are
consumed by the per-IP mes_dbgext wiring for gfx11 and gfx12.
Signed-off-by: Yongqiang Sun <Yongqiang.Sun@amd.com>
Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
amdgpu_ualink_export_handle() takes an explicit amdgpu_bo_ref() before
building the exporter node, and the out: label only drops the reference
from drm_gem_object_lookup(). The xarray insert failure path unrefs the
BO, but the drm_gem_prime_handle_to_dmabuf() failure path does not.
Userspace can hit that path at will, for example by exhausting its file
descriptor table so the dmabuf export returns -EMFILE, leaking a BO
reference and its pinned VRAM on every attempt.
Fixes: c67cb19811 ("drm/amdgpu: Implement UALink handle export")
Reported-by: Sashiko-bot <sashiko-bot@kernel.org>
Closes: https://sashiko.dev/#/patchset/20260914054604.12850-1-kmehltretter@gmail.com?part=1
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Route kernel GFX resets through amdgpu_gfx_reset_mes_gfx() when PER_PIPE
is supported, so collateral kernel rings are preserved across a pipe
reset. Keep the existing queue reset path otherwise.
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
The MPCCs different gamut remap matrices allow for S2D13 and S3D12 floating
point formats, but only S2D13 is used. There may be cases where
more integer bits are required.
[How]
Switch to S3D12 if any entries in the remap matrix cannot fit in S2D13.
Otherwise, prefer the extra precision of S2D13. Communicate the max value
that hw can support to dm via dc color caps.
Signed-off-by: Clay King <clayking@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
Rounding up cursor width was only used to calculate total size in
previous generations. Do not use the rounded up cursor width in
hardware programming.
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
These are important for getting correct DP and audio output.
The wrong pixel clock will be used otherwise.
[How]
Update the default clocks for the DCN60 lite3 variant.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Set a flag to enable pstate pmo, we want to always allow pstate
support on dcn42
Partial application: DCN42B resource constructor only.
Fixes: 6352e60273 ("drm/amd/display: Enable dcn42 pstate pmo")
Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
- BSOD was found on a DP config due to incomplete DSC padding
implementation for DP
- Block DSC padding on DP until fully implemented
Signed-off-by: Relja Vojvodic <Relja.Vojvodic@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: George Shen <george.shen@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
drm_mode_config_validate() warns when a plane exposes an alpha-capable
pixel format without a blend_mode_property. amdgpu DM only created that
property for overlay planes, so PRIMARY and CURSOR triggered the warning
on every probe and reload in kernel 7.2.
Create the blend mode property for every plane that advertises an alpha
format. Keep overlay-only alpha_property. Cursor advertises only
pre-multiplied blend mode because native cursor programming is
pre-multiplied.
Assisted-by: Cursor:Claude-Opus-4.8
Signed-off-by: Ray Wu <ray.wu@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Sun peng (Leo) Li <sunpeng.li@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why & how]
Out-of-urgent bandwidth delivery to DCN is very poor under workloads.
Even after asserting urgent, empirical data shows urgent return BW
delays of up to 100 μs. Override the value when programming
watermarks to avoid modifying mode support. Maintain the DML's calculated
value as a floor.
Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY&HOW]
VTG params should be corrected based on HW expectation:
- FP2 = v_bp - vstartup_start (if vstartup is after vsync), else 0
- vcount_init = OTG SOF position from vsync (0) or vtotal
depending on vstartup position
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why/How]
Current method of keeping track of the LT timeout can cause the actual
elapsed time to creep past the spec-defined limits.
Adjust the behavior to make timeouts more consistent.
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Chris Park <chris.park@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
some panel will generate HPD if receive invalid the action.
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
The DCN10 post-unlock BLS path still emitted self-refresh suppression steps
that are dead for this flow. Keeping them also left non-compliant BLS enums
and documentation behind after the architecture cleanup.
[HOW]
Removed the dead DCN10 BLS producer path, dropped the associated BLS enums,
params, helpers, dispatcher cases, unit-test dumper cases, and updated the
BLS documentation. Kept the shared dcn10_update_pending_status consumer
because later DCN generations still use it.
Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
hubbub_soft_reset_params carried the callee itself as a function pointer,
so the step was not fully described by its parameters. The core_gtest
dumper could only record hubbub and reset, which means two sequences
calling different functions compare equal. It also forced dcn401_hwseq to
name the dcn10 symbol hubbub1_soft_reset directly, because hubbub_funcs
had no slot for a soft reset.
[HOW]
Added soft_reset to hubbub_funcs and pointed hubbub4_01_funcs,
hubbub42_funcs and hubbub60_funcs at hubbub1_soft_reset, the same way
allow_self_refresh_control is already shared. Dropped the function pointer
from the params struct and the add helper, and had the executor call
hubbub->funcs->soft_reset. The dcn10_hubbub.h include in dcn401_hwseq.c is
no longer needed.
Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
Besides programming the hubbub, the HUBBUB_ALLOW_SELF_REFRESH_CONTROL
executor wrote through an output pointer into hwseq->wa_state to record
that the MPO stutter workaround had been applied. That bookkeeping has no
relationship to the register write and makes the operation mutate a logical
object while the sequence runs.
[HOW]
Removed the pointer from hubbub_allow_self_refresh_control_params and from
the add helper, leaving the executor a plain pass through to
hubbub->funcs->allow_self_refresh_control.
hwss_build_post_unlock_full_sequence now sets the workaround flag itself,
inside the same condition that decides to emit the step. TG_GET_FRAME_COUNT
is left as is: its out parameter is the read back register value, and
reading it after the write matches the legacy implementations.
Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
hubbub_force_pstate_change_control_params::wait was passed as the allow
argument of hubbub_funcs::force_pstate_change_control, which drives
DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE. Sitting three lines above a
udelay(500), the name read as a timing control and invited the wrong
conclusion about what the field does.
[HOW]
Renamed the field to allow and updated the add helper signature, the
executor, the core_gtest dumper and comparator, and the affected
core_golden entry. No functional change.
Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
The operation wrote no hardware register. Its executor only set
opp->mpcc_disconnect_pending, a driver side flag, which breaks the rule
that a block sequence step programs a hardware block rather than mutating
logical objects. It was also split across phases: written while the
pre-unlock sequence executed, then read and cleared while the post-unlock
sequence was still being built.
[HOW]
Deleted the enum value, the params struct, the add helper, the executor and
the dispatch case. dcn401_plane_atomic_disconnect_sequence now sets the
flag during the build phase, matching what dcn10, dcn20, dcn201, dcn35,
dcn3ag and dcn42b already do. Updated the operation specs and the
core_gtest dumper.
Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
opp2_set_disp_pattern_generator read
debug.disable_dynamic_expansion_for_test_pattern through opp->ctx->dc while
the sequence was executing. A block sequence operation must take its inputs
from a flat parameter list resolved during the build phase, so this hid an
input from the recorded sequence and left the FMT_DYNAMIC_EXP_CNTL branch
unreachable from the OPP unit tests.
[HOW]
Added disable_dyn_exp_for_test_pattern to
opp_funcs::opp_set_disp_pattern_generator and to
opp_set_disp_pattern_generator_params, and updated every caller to pass
dc->debug.disable_dynamic_expansion_for_test_pattern explicitly. Updated
the unit test mocks and the core_gtest dumper, and extended opp_gtest to
cover both values of the new flag.
Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why/How]
On the PWM path, convert the userspace brightness to an input signal and
derive the target luminance from the custom backlight curve, then pass
the resulting millipercent to the power module.
This keeps PWM programming and backlight curve mapping in the power
module, aligning the Linux path with the Windows behavior.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/5723
Fixes: 3c108046e1 ("drm/amd/display: Add power module on Linux")
Assisted-by: Cursor:Claude-Opus-4.8
Signed-off-by: Ray Wu <ray.wu@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: ChiaHsuan (Tom) Chung <chiahsuan.chung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
Add the POR setting for SDP_PORT_CONTROL into dc init sequence.
This is temporary until the initialization moves into pre-OS DMCUB.
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why & how]
DCN60 supports cursor offload to DMU.
Request cursor offload in amdgpu_dm_init and initialize it after DMUB is up
(dc_dmub_srv_cursor_offload_init), which should be picked up by all the
ASICs that support cursor offload in the dcnX_resouce.c.
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
The copyright notice was carried over from code related to kernel
floating-point support. The associated DC_FP_START() and DC_FP_END() macros
are not present in SPL, so the notice is no longer applicable.
Remove the unused copyright notice from spl_os_types.h.
Signed-off-by: Jackson He <Jackson.He@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Samson Tam <samson.tam@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
why:
When a display is disabled the surviving DSC stream is committed with no
planes but the dynamic ODM policy still expands it to a four to one
combine. The added plane-less segments skip program_pipe so their OPP
formatter is never configured. The DPG blank then feeds an unprogrammed
formatter and the OPTC input underflows which flashes grey on screen.
how:
Program the OPP formatter for each plane-less OPP head in update_odm and
update_odm_sequence the same way program_pipe does for planed pipes. Both
function pointers are checked for null before calling. Every ODM segment
now feeds valid data to the OPTC so the four to one combine no longer
underflows.
Signed-off-by: Ashwin Santhosh <Ashwin.Santhosh@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
amdgpu_gem_ualink_handle_ioctl() dereferences adev->ualink.info before
validating it, but that structure is only allocated when the UALink IP
block is present, which is currently added only for GFX 12.1 only. The
ioctl is registered for every amdgpu device with DRM_RENDER_ALLOW, so
on any other ASIC a render node user can oops the kernel with a single
call.
Return -EOPNOTSUPP when the UALink software state is absent.
Fixes: 15d1c306d8 ("drm/amdgpu: Add ioctl infra for exporting/importing UALink handles")
Reported-by: Sashiko-bot <sashiko-bot@kernel.org>
Closes: https://sashiko.dev/#/patchset/20260914054604.12850-1-kmehltretter@gmail.com?part=1
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
Hotplugging an HDMI FRL sink can wedge DMCUB when a poll-driven retrain
lands on a link whose PHY has just been torn down. The status polling
path can program PHY EQ on the disabled PHY, after which the sink SCDC
reads back version 0 and the display fails to light up.
[HOW]
Skip FRL status polling unless the link is actively driving a stream.
The check runs under dc_lock, so it is serialized with link detection
and modesets while the PHY is being torn down.
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
- Gamcor light sleep must be disabled before gamcor programming
- Mirror the programming sequence for DSCL light sleep
- Create a dcn60 version for gamcor programming
- Make dcn30 helper functions public so they can be called from the
new dcn60 function
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
For unknown reasons, on gfx12 using multiple entities can causes
random corruption of BOs with DCC.
This workaround seems to prevent the issue until the root cause
is understood and fixed.
Link: https://gitlab.freedesktop.org/drm/amd/-/work_items/5663
Fixes: 3a6f6eeb3d ("drm/amdgpu: give ttm entities access to all the sdma scheds")
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The soft_reset() function for GMC (memory controller) block
of Vega has never been implemented, and there are no
plans to implement it.
Let's delete this function, it doesn't do anything and
also isn't called from anywhere.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Note that the soft reset code for GMC v6-v7 was never
called from anywhere, so there is no loss of functionality
from this commit. The implementation looks plausible but
it was never enabled or tested, and unlikely to be useful.
We should only reset the memory controller during ASIC reset
and otherwise leave it alone. Resetting the memory controller
can break everything and risks losing the contents of VRAM
(it's unclear if VRAM is lost or not, but it's likely).
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Use gfx_supported_reset's PER_PIPE bit to report GFX pipe reset support
through a shared helper.
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DMs still call dc_hardware_init and dc_hardware_release while Core 2
lands next to legacy. Those entry points live in dc/dc_api_dispatch:
LEGACY calls the old bodies directly, CORE2 uses core2_funcs. dc_create
allocates struct dc2 and returns the inner dc (TO_DC2). The shim only
records selection; dc_construct still constructs Core2. No dispatch
fields on public struct dc, and no architect spec edits.
TO_DC2 is a typed upcast (struct dc is the first member of struct dc2).
Shim headers are included for UNIT_TEST as well as production so TO_DC2
is defined when core_gtest compiles dc.c.
Assisted-by: Cursor:cursor
Signed-off-by: Cheng, Tony <Tony.Cheng@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Jun Lei <jun.lei@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY+HOW]
According to HW, change default z8 enter/exist for dcn314.
SR Z8 exit = 268, change to 390.
SR Z8 enter = 393, change to 601.
Signed-off-by: Fudongwang <Fudong.Wang@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY&HOW]
Not all revisions require the same clock overrides.
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
The HDMI FRL status polling work can run concurrently with link detect
after an unplug/replug. Both paths access the same link through DDC and may
perform FRL link training, while the polling path also reads link state
without holding dc_lock.
[HOW]
Use mutex_trylock() to serialize the complete link walk, FRL status
polling, and retraining sequence with dc_lock. If the lock is busy,
defer the background poll to the next 200ms cycle instead of blocking
an active detect, modeset, or flip.
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
The QoS model override for a display IP block was silently
skipped whenever the firmware-populated table was invalid.
[How]
Always re-point the bandwidth params at the driver's own
persistent QoS model storage before applying the override,
instead of returning early when the firmware-populated model
is NULL.
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Bandwidth overrides must be applied in a defined order so debug
settings are reflected in the final parameters.
[How]
Group clock adjustments with the clock table override and derive
the final mode limits after all clock table changes.
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Keep the display QoS model and firmware table consistent when test
overrides are enabled.
[How]
Serialize the overridden QoS values into a dedicated transfer buffer
and send the table after clock initialization.
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This can simplify includes
Assisted-by: Cursor:composer-2.5
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Jun Lei <jun.lei@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
to prevent misunderstanding in cwsr off case.
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
CWSR ranges use the always mapped flag and only need a mapping on the
GPU running the queue. However, svm_range_validate_and_map now updates
the mapping on every GPU with the ACCESS attribute, which is all
supported GPUs when XNACK is on. After the range is prefetched to VRAM,
those GPUs may span different XGMI hives, so the page owner mismatches
and is set to NULL. hmm_range_fault then tries to migrate the VRAM
pages back to system memory, but svm_migrate_to_ram skips it because
migrating pages back to system memory is not allowed while the GPU
mapping is being updated, so the CPU page fault is never resolved.
Only map to the ACCESS GPUs if the range is not mapped to any GPU and
is not in VRAM.
Fixes: b96f261049 ("drm/amdkfd: Unmap svm range from GPU set to no-access")
Signed-off-by: Andrew Martin <andrew.martin@amd.com>
Assisted-by: Claude:claude-opus-5
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Philip Yang <philip.yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add initial implemenation for the new generation of mmhub
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add header files for mmhub v5_0_1 register offsets
and shift masks
v2: Update mmhub ip headers to BTO version
v3: Update registers (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add a dedicated ras_psp_v15_0_3 ip_func using PCRU0 C2PMSG_67/127
for psp ring wptr and RAS capability query.
Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
