"make dtbs_check" fails with:
arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dt.yaml: eeprom@50: compatible: 'oneOf' conditional failed, one must be fixed:
'microchip,at24c64' does not match '^(atmel|catalyst|microchip|nxp|ramtron|renesas|rohm|st),(24(c|cs|lc|mac)[0-9]+|spd)$'
Fix this by dropping the bogus "at" prefix.
Fixes: a1d8a344f1 ("arm64: dts: renesas: Introduce r8a774a1-beacon-rzg2m-kit")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20210128110136.2293490-1-geert+renesas@glider.be
The MT8183 display PWM device will not work until the associated
power-domain is enabled. Add the power-domain reference to the node
allows the display PWM driver to operate and the backlight turn on.
Fixes: f15722c0fe ("arm64: dts: mt8183: Add pwm and backlight node")
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
Link: https://lore.kernel.org/r/20210113215723.71966-1-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add support for the variant of the Jetson Xavier NX Developer Kit that
has a system-on-module which includes an eMMC.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
There are two versions of the Jetson Xavier NX system-on-module; one
with a micro SD-card slot and one with an eMMC. Currently, only the
system-on-module with the micro SD-card slot is supported. Before adding
support for the eMMC variant, move the common device-tree parts of the
existing Jetson Xavier NX system-on-module board (p3668-0000) and
reference carrier board (p3509-0000) into include files that can be used
by both Jetson Xavier NX variants.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
property name must include only lowercase and '-'
Fixes: 91f9c963ce ("arm64: dts: mt8183: Add display nodes for MT8183")
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20210128112314.1304160-2-hsinyi@chromium.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
We can use CPU specific pmu configuration to expose the appropriate
CPU specific events rather than just the basic generic pmuv3 perf
events.
Reported-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Tero Kristo <kristo@kernel.org>
Link: https://lore.kernel.org/r/20210120195145.32259-1-nm@ti.com
The CEC and hotplug interrupts go through an interrupt controller shared
between the two HDMI controllers.
Let's add that interrupt controller and the interrupts for both HDMI
controllers
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Link: https://lore.kernel.org/r/20210111142309.193441-16-maxime@cerno.tech
Remove SATA from Stingray as it is unsupported.
Acked-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
BCM4908 has internal switch with 5 GPHYs. Ports 0 - 3 are always
connected to the internal PHYs. Remaining ports depend on device setup.
Asus GT-AC5300 has an extra switch with its PHYs accessible using the
internal MDIO.
CPU port and Ethernet interface remain to be documented.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Enable support for audio-graph based sound card on Jetson-Nano and
Jetson-TX1. Depending on the platform, required I/O interfaces are
enabled.
* Jetson-Nano: Enable I2S3, I2S4, DMIC1 and DMIC2.
* Jetson-TX1: Enable all I2S and DMIC interfaces.
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Expose a header which describes DT bindings required to use audio-graph
based sound card. All Tegra210 based platforms can include this header
and add platform specific information. Currently, from SoC point of view,
all links are exposed for ADMAIF, AHUB, I2S and DMIC components.
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Device tree nodes are ordered by unit-address and alphabetically by name
if a node doesn't have a unit-address. The thermal sensor and timer
nodes were not sorted in the correct order, so do that now.
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit enables USB host mode at J512 type-C port of Jetson-Xavier.
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
PMC driver provides USB sleepwalk registers access to XUSB PADCTL
driver. This commit adds a "nvidia,pmc" property which points to
PMC node to XUSB PADCTL device node.
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
HDA initialization is failing occasionally on Tegra210 and following
print is observed in the boot log. Because of this probe() fails and
no sound card is registered.
[16.800802] tegra-hda 70030000.hda: no codecs found!
Codecs request a state change and enumeration by the controller. In
failure cases this does not seem to happen as STATETS register reads 0.
The problem seems to be related to the HDA codec dependency on SOR
power domain. If it is gated during HDA probe then the failure is
observed. Building Tegra HDA driver into kernel image avoids this
failure but does not completely address the dependency part. Fix this
problem by adding 'power-domains' DT property for Tegra210 HDA. Note
that Tegra186 and Tegra194 HDA do this already.
Fixes: 742af7e7a0 ("arm64: tegra: Add Tegra210 support")
Depends-on: 96d1f078ff ("arm64: tegra: Add SOR power-domain for Tegra210")
Cc: <stable@vger.kernel.org>
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled
when using DDR interface mode.
This patch adds clock ID for this to dt-binding.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This patch adds basic support for MYIR Tech MYC-AM335X CPU Module:
- Up to 1GHz TI AM335X Series ARM Cortex-A8 Processors
- Up to 512MB DDR3 SDRAM
- Up to 512MB Nand Flash
and MYD-AM335X Development Board:
- MYC-AM335X CPU Module as Controller Board
- Serial ports, 4 x USB Host, OTG, 2 x Gigabit Ethernet, CAN, RS485,
TF, Audio
- Supports HDMI and LCD Display
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Tony Lindgren <tony@atomide.com>
I've switched employer a long time ago and the mentioned email address no
longer exists. Use my personal address to prevent the issue in the future.
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Previously, the 1GHz variants were marked as a turbo,
because that variant has reduced thermal operating range.
Now that the thermal throttling is in place, it should be
safe to remove the turbo-mode from the 1GHz variants, because
the CPU will automatically slow if the thermal limit is reached.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The Android vendor kernel uses 307.2MHz or a divider ratio of /5 while active
153600000 or /10 is only used when the sgx core is inactive.
Signed-off-by: Carl Philipp Klemm <philipp@uvos.xyz>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The omap4430 HS HIGH performance devces support 1.2GHz opp, lower speed
variants do not. However for mapphone devices Motorola seems to have
decided that this does not really matter for the SoC variants they have
tested to use, and decided to clock all devices, including the ones with
STANDARD performance chips at 1.2GHz upon release of the 3.0.8 vendor
kernel shiped with Android 4.0. Therefore it seems safe to do the same,
but let's only do it for Motorola devices as the others have not been
tested.
Note that we prevent overheating with the passive cooling device
cpu_alert0 configured in the dts file that starts lowering the speed as
needed.
This also removes the "failed to find current OPP for freq 1200000000"
warning.
Cc: Merlijn Wajer <merlijn@wizzup.org>
Cc: Pavel Machek <pavel@ucw.cz>
Cc: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Carl Philipp Klemm <philipp@uvos.xyz>
[tony@atomide.com: made motorola specific, updated comments]
Signed-off-by: Tony Lindgren <tony@atomide.com>
The current cooling device temperature is too high at 100C as we have a
battery on the device right next to the SoC as pointed out by Carl Philipp
Klemm <philipp@uvos.xyz>. Let's configure the max temperature to 80C.
As we only have a tshut interrupt and no talert interrupt on 4430, we have
a passive cooling device configured for 4430. However, we want the poll
interval to be 10 seconds instead of 1 second for power management. The
value of 10 seconds seems like plenty of time to notice the temperature
increase above the 75C temperatures. Having the bandgap temperature change
seems to take several tens of seconds because of heat dissipation above
75C range as monitored with a full CPU load.
Cc: Carl Philipp Klemm <philipp@uvos.xyz>
Cc: Merlijn Wajer <merlijn@wizzup.org>
Cc: Pavel Machek <pavel@ucw.cz>
Cc: Sebastian Reichel <sre@kernel.org>
Suggested-by: Carl Philipp Klemm <philipp@uvos.xyz>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We have gpio_86 wired internally to the bandgap thermal shutdown
interrupt on 4430 like we have it on 4460 according to the TRM.
This can be found easily by searching for TSHUT.
For some reason the thermal shutdown interrupt was never added
for 4430, let's add it. I believe this is needed for the thermal
shutdown interrupt handler ti_bandgap_tshut_irq_handler() to call
orderly_poweroff().
Fixes: aa9bb4bb88 ("arm: dts: add omap4430 thermal data")
Cc: Carl Philipp Klemm <philipp@uvos.xyz>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Eduardo Valentin <edubezval@gmail.com>
Cc: Merlijn Wajer <merlijn@wizzup.org>
Cc: Pavel Machek <pavel@ucw.cz>
Cc: Peter Ujfalusi <peter.ujfalusi@gmail.com>
Cc: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This adds audio playback to the first generation Amazon Echo
Signed-off-by: André Hentschel <nerv@dawncrow.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Fix checkpatch warning:
WARNING: please, no spaces at the start of a line
Signed-off-by: Stanislav Jakubek <stano.jakubek@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The BSC controllers used for the HDMI DDC have an interrupt controller
shared between both instances. Let's add it to avoid polling.
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Link: https://lore.kernel.org/r/20210111142309.193441-1-maxime@cerno.tech
RPi4's co-processor will copy the board's bootloader[1] configuration
into memory for the OS to consume. Specifically, for the bootloader
configuration and upgrade user-space routines to query it through
nvmem's sysfs interface.
Introduce a reserved-memory area template for the co-processor to edit
before booting the system so as for Linux not to overwrite that memory
and to expose it as an nvmem device.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Tested-by: Tim Gover <tim.gover@raspberrypi.com>
Link: https://lore.kernel.org/r/e8ca9365-a1f2-1f9d-377c-13bf97883cce@linaro.org
[1] https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711_bootloader_config.md
Updates the compatible string for DSI1 on BCM2711 to
differentiate it from BCM2835.
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Link: https://lore.kernel.org/r/20201203132543.861591-9-maxime@cerno.tech
The vendor kernel uses the following thermal-zone settings:
<= 70°C:
- CPU frequency limited to 1.488GHz
- GPU limited to 511MHz and 2 cores (pixel processors)
<= 80°C:
- CPU frequency limited to 1.2GHz
- GPU limited to 435MHz and 2 cores (pixel processors)
<= 90°C:
- CPU frequency limited to 0.804GHz
- GPU limited to 328MHz and 1 core (pixel processor)
Add simplified thermal configuration which is taken from the
GXBB/GXL/GXM SoC family (which uses the same manufacturing process and
has the same maximum junction temperature of 125°C). With this the
thermal framework will try to keep the SoC temperature at or below 80°C
which is identical to the vendor kernel (with the exception of one CPU
frequency step from 1.488GHz to 1.536GHz).
The number of GPU cores are not taken into account as this is not
supported.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20201221181306.904272-5-martin.blumenstingl@googlemail.com
The vendor kernel uses the following thermal-zone settings:
<= 70°C:
- CPU frequency limited to 1.608GHz
- GPU limited to 511MHz and 5 cores (pixel processors)
<= 80°C:
- CPU frequency limited to 1.2GHz
- GPU limited to 435MHz and 4 cores (pixel processors)
<= 90°C:
- CPU frequency limited to 0.804GHz
- GPU limited to 328MHz and 3 cores (pixel processors)
Add simplified thermal configuration which is taken from the
GXBB/GXL/GXM SoC family (which uses the same manufacturing process and
has the same maximum junction temperature of 125°C). With this the
thermal framework will try to keep the SoC temperature at or below 80°C
which is identical to the vendor kernel (with the exception of one GPU
pixel processor).
The number of GPU cores are not taken into account as this is not
supported.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20201221181306.904272-4-martin.blumenstingl@googlemail.com
The SoC temperature can be retrieved from ADC channel 8 on all 32-bit
SoCs (Meson6, Meson8, Meson8b and Meson8m2). Add a "generic-adc-thermal"
instance to meson.dtsi so the thermal sensor is available for all SoCs.
If the temperature sensor calibration data is missing for a board then
the "generic-adc-thermal" will not probe and not register a thermal
sensor.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20201221181306.904272-3-martin.blumenstingl@googlemail.com
The SoC temperature can be retrieved from ADC channel 8 on all 32-bit
SoCs (Meson6, Meson8, Meson8b and Meson8m2). Move the iio-hwmon instance
to meson.dtsi instead of duplicating it in all board.dts.
If the temperature sensor calibration data is missing for a board then
iio-hwmon will simply not probe.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20201221181306.904272-2-martin.blumenstingl@googlemail.com
The DHCOM SoM uSD slot has an optional voltage level translator, add
DT bindings which permit the MMCI driver to detect the translator
automatically.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Ludovic Barre <ludovic.barre@st.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: linux-stm32@st-md-mailman.stormreply.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add "init" mux option for SDMMC1, where the CMD, CK, CKIN lines are not
configured, so they can be claimed as GPIOs early on in driver probe().
This is used for probing optional voltage level translator.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Ludovic Barre <ludovic.barre@st.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: linux-stm32@st-md-mailman.stormreply.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
SCIF0 has been enabled by the firmware, so it worked already. Still, add
the proper nodes to make it work in any case.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210121110008.15894-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This is the result of multiple patches taken from the BSP, combined,
rebased, and properly sorted. SCIF0 gets DMA properties, other SCIFs are
entirely new.
Signed-off-by: Linh Phung <linh.phung.jy@renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210121110008.15894-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
