- Add support for the RZ/V2M and R-Car V4H SoCs,
- Miscellaneous fixes and improvements.
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Merge tag 'renesas-pinctrl-for-v5.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.20 (take two)
- Add support for the RZ/V2M and R-Car V4H SoCs,
- Miscellaneous fixes and improvements.
Saving/restoring interrupt and wake status bits across suspend can
cause the suspend to fail if an IRQ is serviced across the
suspend cycle.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
Fixes: 79d2c8bede ("pinctrl/amd: save pin registers over suspend/resume")
Link: https://lore.kernel.org/r/20220613064127.220416-3-Basavaraj.Natikar@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Update MAINTAINERS to set the Intel pin control status to Supported
* Switch Intel pin control drivers to use struct pingroup
The following is an automated git shortlog grouped by driver:
baytrail:
- Switch to to embedded struct pingroup
cherryview:
- Switch to to embedded struct pingroup
intel:
- Add Intel Meteor Lake pin controller support
- Drop no more used members of struct intel_pingroup
- Switch to to embedded struct pingroup
- Embed struct pingroup into struct intel_pingroup
lynxpoint:
- Switch to to embedded struct pingroup
MAINTAINERS:
- Update Intel pin control to Supported
Merge branch 'ib-v5.20-amd-pinctrl':
- Merge branch 'ib-v5.20-amd-pinctrl'
merrifield:
- Switch to to embedded struct pingroup
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Merge tag 'intel-pinctrl-v5.20-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v5.20-1
* Update MAINTAINERS to set the Intel pin control status to Supported
* Switch Intel pin control drivers to use struct pingroup
The following is an automated git shortlog grouped by driver:
baytrail:
- Switch to to embedded struct pingroup
cherryview:
- Switch to to embedded struct pingroup
intel:
- Add Intel Meteor Lake pin controller support
- Drop no more used members of struct intel_pingroup
- Switch to to embedded struct pingroup
- Embed struct pingroup into struct intel_pingroup
lynxpoint:
- Switch to to embedded struct pingroup
MAINTAINERS:
- Update Intel pin control to Supported
Merge branch 'ib-v5.20-amd-pinctrl':
- Merge branch 'ib-v5.20-amd-pinctrl'
merrifield:
- Switch to to embedded struct pingroup
Commit 6c846d026d ("gpio: Don't fiddle with irqchips marked as
immutable") added a warning to indicate if the gpiolib is altering the
internals of irqchips.
Following this change the following warning is now observed for the SPMI
PMIC pinctrl driver:
gpio gpiochip1: (200f000.spmi:pmic@0:gpio@c000): not an immutable chip, please consider fixing it!
Fix this by making the irqchip in the SPMI PMIC pinctrl driver immutable.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20220624195112.894916-1-robimarko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds missing ERROROUTC_A settings.
Current existing ERROROUTC should be _B, this patch tidies it up.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87mtdtsj8m.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
R-Car V4H has PWM/PWM_A/PWM_B, but current PFC setting is mixed.
This patch adds missing PWM settings, and tidies these up.
According to Document, GP3_14 Function4 is PWM2_A,
but we can't select it at P1SR3[27:24].
This patch just ignore it for now.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87o7y9sj90.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds missing FlexRay pins.
Because Document (Rev.0.51) has 2x FXR_TXENA/B pin with no suffix (_A, _B),
this patch names them as _X.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87pmipsj9a.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds missing SCIF1_X.
Because Document (Rev.0.51) has 2x SCIF1 with no suffix (_A, _B),
this patch names it as _X.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87tu81sja1.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
R-Car V4H has SCIF3 and SCIF3_A, but current PFC setting is mixed.
This patch cleans up SCIF3/SCIF3_A, based on Rev.0.51.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87v8shsja7.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds missing HSCIF1.
Because Document (Rev.0.51) has 2x HSCIF1 with no suffix (_A, _B),
this patch names it as _X.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87wncxsjah.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds missing TCLKx_A/TCLKx_B/TCLKx_X.
Because Document (Rev.0.51) has 2x TCLK3/TCLK4 with no suffix (_A, _B),
this patch names them as _X.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/871qv5txvt.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
According to Rev.0.51 datasheet 004_R-CarV4H_pin_function.xlsx,
GP1_23 - GP1_28 are 1.8/3.3V. But they are not on Table 7.28.
According to the HW team, there are no bits assigned.
This patch follows HW team's comment.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/8735fltxwg.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Current R-Car V4H PFC code has many MOD_SELx definitions with all 0.
But these have no meaning. This patch removes them.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/875ykhtxym.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Current R-Car V4H PFC code has many IPxSRx definitions with all 0.
But these have no meaning. This patch removes them.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/877d4xtxyv.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Current R-Car V4H PFC code has many NOGP definitions. But these are not
used, and they are different from original usage. This patch removes
them.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/878rpdtxz8.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
MODSEL8 controls I2C vs. GPIO modes, and the Datasheet (Rev.0.51) is
indicating that I2C needs 1. But we should use 0 for all cases in
reality. New Datasheet should be updated.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87a69ttxzg.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds initial pinctrl support for the R-Car V4H (R8A779G0)
SoC, including bias, drive strength and voltage control.
This patch was created based on the Rev.0.51 datasheet.
Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[Morimoto: merge Kihara-san's MODSEL8 fixup patch, cleanup white space, care about reserved bits on each configs, fixup comments, etc.]
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87czepty0j.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add PORT_GP_CFG_13() and PORT_GP_13() helper macros, to be used by the
r8a779g0 subdriver.
Based on a larger patch in the BSP by LUU HOAI.
Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87edz5ty0r.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add support for pin and gpio controller driver for RZ/V2M SoC.
Based on the RZ/G2L driver.
Note that the DETDO and DETMS dedicated pins are currently not
documented in the HW manual as to which pin group they are in.
HW team has since said that the output level of 1.8V I/O group 4
(for MD0-7, and debugger) is the same as the 1.8V I/O group 3.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220624084833.22605-3-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This driver adds pinctrl/GPIO support for Intel Meteor Lake. The
GPIO controller is based on the next generation GPIO hardware but still
compatible with the one supported by the Intel core pinctrl/GPIO driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
These PMICs each have 2 GPIOs with the same register layout as AXP813,
but without an ADC function. They all fall back to the AXP221 compatible
string, so only that one needs to be listed in the driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Link: https://lore.kernel.org/r/20220621034224.38995-4-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
These PMICs each have 2 GPIOs with the same register layout as AXP813,
but without an ADC function.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220621034224.38995-2-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix the compilation error, caused by updating constant variable.
Hence remove redundant constant variable, which is no more useful
as per new design.
The issue is due to some unstaged changes. Fix it up.
Fixes: 36fe26843d ("pinctrl: qcom: sc7280: Add clock optional check for ADSP bypass targets")
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1656489290-20881-1-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Commit fe44e49840 ("pinctrl: mediatek: add rsel setting on mt8192")
added RSEL bias type definition for some pins on mt8192. In order to be
able to configure the bias on those pins, add the RSEL values in the
bias-pull-up and bias-pull-down properties in the binding.
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220627173209.604400-1-nfraprado@collabora.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Samsung SoC pin controller driver uses only three defines from the
bindings header with pin configuration register values, which proves
the point that this header is not a proper bindings-type abstraction
layer with IDs.
Define the needed register values directly in the driver and stop using
the bindings header.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220605160508.134075-8-krzysztof.kozlowski@linaro.org
Link: https://lore.kernel.org/r/20220624081022.32384-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Update the driver to use an immutable IRQ chip to fix this warning:
"not an immutable chip, please consider fixing it!"
Preserve per-chip labels by adding an ->irq_print_chip() callback.
Acked-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Link: https://lore.kernel.org/r/20220622185010.2022515-3-aidanmacdonald.0x0@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix the below kernel-doc warning by adding the description for return
value.
"warning: No description found for return value of
'zynqmp_pmux_get_function_groups'".
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Link: https://lore.kernel.org/r/1655462819-28801-5-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support to handle 'output-enable' and 'bias-high-impedance'
configurations. As part of the output-enable configuration, ZynqMP pinctrl
driver takes care of removing the pins from tri-state.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Link: https://lore.kernel.org/r/1655462819-28801-4-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Set PINCTRL_OCELOT config option as a tristate and add
MODULE_DEVICE_TABLE()/MODULE_LICENSE() to export appropriate
information. Moreover, switch from builtin_platform_driver()
to module_platform_driver().
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Link: https://lore.kernel.org/r/20220617103548.490092-1-clement.leger@bootlin.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The idea was right but the code was breaking in next.
I assume some unstaged commit was involed. Fix it up.
Cc: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Cc: Stephen Boyd <swboyd@chromium.org>
Fixes: 36fe26843d ("pinctrl: qcom: sc7280: Add clock optional check for ADSP bypass targets")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Fix reporting of input disabled pins on RZ/G2L.
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Merge tag 'renesas-pinctrl-for-v5.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.20
- Fix reporting of input disabled pins on RZ/G2L.
