Commit e1b73b6427 ("amdkfd: remove DIQ support") removed the
KFD_QUEUE_TYPE_DIQ enumerator from enum kfd_queue_type but left its
description behind in the note block.
Fixes: e1b73b6427 ("amdkfd: remove DIQ support")
Signed-off-by: Lu Yao <yaolu@kylinos.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Unfortunately, some desktop boards eg. the FirePro D500
have the HARDWAREDC platform flag set and also have
a battery power state configured in their VBIOS.
This makes no sense for a desktop GPU and results in
incorrect behaviour: the clocks are stuck at lowest.
We observed that the kernel driver can work around
the issue in two possible ways:
1. Set PPSMC_SWSTATE_FLAG_DC on all power states
2. Clear PPSMC_SYSTEMFLAG_GPIO_DC
We think that the PPSMC_SYSTEMFLAG_GPIO_DC flag
makes the SMC assume it's running on battery even
though this is a desktop machine with no battery,
and that's why it doesn't do DPM on power states
without PPSMC_SYSTEMFLAG_GPIO_DC.
Issue was uncovered by "Fix updating clock limits from
power states" because previously the limits for the
battery state were not tracked separately. However,
battery power state has lower frequencies and voltages,
so the kernel doesn't set the DC flag on the current
power state anymore. That causes the SMC to be stuck
on the lowest clocks.
Let's clear PPSMC_SYSTEMFLAG_GPIO_DC on desktop GPUs.
We can use the AMD_IS_MOBILITY flag to determine that.
Fixes: e6c5d36756 ("drm/amd/pm/si: Fix updating clock limits from power states")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/16352
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://patch.msgid.link/20260923120354.1027996-1-timur.kristof@gmail.com
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anchor the object search to the DML wrapper top-level Makefile directory.
This allows source files in subdirectories to be properly discovered and
compiled with the required FPU CFLAGS, fixing SSE compilation errors.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
XNACK is not supported on A0. Updating RETRY_DISABLE only for the VMID
in use gives unreliable control, so all VMIDs must be programmed
identically.
Set SH_MEM_CONFIG.RETRY_DISABLE = 1 on rev_id 0 for every VMID in both
constants init and compute VMID init, so XNACK replay is off from device
boot up.
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Mukul Joshi <mukul.joshi@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The soft_reset() function for the DCE / DCN blocks
has never been implemented, and there are no
plans to implement it.
Let's delete this function, it doesn't do anything and
also isn't called from anywhere.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DCE 6.4 is found in Oland chips, which were advertised
as low-end gaming GPUs in 2013~2015 and then have been
sold as low-end workstation GPUs until 2017~2019.
These are not APUs.
Fixes: 7c15fd86aa ("drm/amd/display: dc/dce: add initial DCE6 support (v10)")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://patch.msgid.link/20260923122033.1046651-3-timur.kristof@gmail.com
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DCE8 should use legacy fast updates.
This was already set for DCE 8.0 and 8.3, but it seems
that DCE 8.1 (found in Kaveri chips) was forgotten.
This fix should be backported to all kernel versions that
have "Refactor fast update to use new HWSS build sequence",
but this patch won't apply cleanly to older kernels due to
another refactor in "Remove dc param from check_update".
Fixes: 0baae62463 ("drm/amd/display: Refactor fast update to use new HWSS build sequence")
Fixes: 9ec11bb842 ("drm/amd/display: Remove dc param from check_update")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://patch.msgid.link/20260923122033.1046651-2-timur.kristof@gmail.com
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DCE6 should use legacy fast updates, just like all DCE8 - DCN2.
Set that flag for DCE 6.0, 6.1 and 6.4 (all DCE6 versions).
Technically DCE6 should have been included when the fast update
code was refactored, but it just happened to work until now.
A recent commit "Attach only plane updates that actually changed"
has exposed this issue because with that commit, DC accidentally
took the new fast update code path for DCE6 as well, which caused
it to boot into a black screen with a flip done timeout.
This fix should be backported to all kernel versions that
have "Refactor fast update to use new HWSS build sequence",
but this patch won't apply cleanly to older kernels due to
another refactor in "Remove dc param from check_update".
Fixes: 0baae62463 ("drm/amd/display: Refactor fast update to use new HWSS build sequence")
Fixes: 9ec11bb842 ("drm/amd/display: Remove dc param from check_update")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://patch.msgid.link/20260923122033.1046651-1-timur.kristof@gmail.com
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Commit 56d8ce9d8c ("drm/amd/display: Apply correct panel mode when
reinitializing hardware") made ASSR failure fall back to the default panel
mode unless eDP mode had previously been applied.
However, dc_link is zero-initialized and DP_PANEL_MODE_DEFAULT is zero.
Before the first call to dp_set_panel_mode(), panel_mode therefore looks
like a previously applied default mode. If ASSR setup fails during the
first link training attempt, the driver incorrectly trains the eDP link
using the default scrambling mode.
On a Google Vilboz Chromebook running self-built coreboot firmware and
PSP verstage, this leaves the panel mostly black with corrupted output
along the top edge.
Track whether panel_mode has actually been initialized, and only consult
the saved mode after it has been applied. This retains the recovery
behavior while preserving eDP mode during initial link training.
Fixes: 56d8ce9d8c ("drm/amd/display: Apply correct panel mode when reinitializing hardware")
Assisted-by: Pi:gpt-5.6-sol
Reviewed-by: George Zhang <george.zhang@amd.com>
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
With the Broadcast RGB property at Automatic,
amdgpu_dm_get_output_color_space() selects COLOR_SPACE_SRGB for RGB
output, so DC neither compresses the pixels nor, without a QS-capable
sink, signals full range in the AVI InfoFrame. A sink that follows
CTA-861 treats the default quantization of a CTA video format as limited
and expands 16-235 to 0-255: everything below 16 is crushed to black,
everything above 235 clips.
Follow the CTA-861 default for Automatic instead, as the DRM HDMI state
helper (hdmi_is_limited_range()) and i915 do: limited range on an HDMI
sink for CTA modes other than 640x480, full range elsewhere. Full and
Limited keep their explicit meaning. The same rule applies to the
BT.2020 RGB branch. With commit 892659399f ("drm/amd/display:
Propagate HDMI RGB quantization selectability") the AVI InfoFrame then
carries the matching Q value on sinks that support selection.
Measured on a Radeon RX 7600 (DCN 3.2.1) driving a JVC DLA-RS4100 at
1920x1080p24 RGB 12 bpc: the sink reports the signal as limited range
while the picture shows crushed shadows; rendering limited range in the
client makes it match a reference source.
The KUnit fixtures that reach amdgpu_dm_get_output_color_space() now
carry a connector, since Automatic reads its display_info, and five
cases cover the new rule.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/5796
Reviewed-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Adrian Betschart <adrian.betschart@cinemaone.ch>
Assisted-by: Claude Code:claude-fable-5-1
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This helper was originally static inline. INLINE_IFN_KUNIT only added
inline for KUnit builds, which dropped that hint from production.
There is no equivalent in kunit/visibility.h, and tests do not need
one: they call the exported symbol from another translation unit.
Use an unconditional inline with VISIBLE_IF_KUNIT instead so
production stays static inline.
kernel-doc already strips inline, so the dedicated xform can go too.
Reviewed-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Albert Esteve <aesteve@redhat.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Use the same helper for GMC v12.1 that is used by other
GMC IP block versions.
No functional changes intended. Just code cleanup.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Switch exports of KUnit-only helpers to EXPORT_SYMBOL_IF_KUNIT.
Unlike EXPORT_IF_KUNIT, which used EXPORT_SYMBOL(), the standard
macro places symbols in the EXPORTED_FOR_KUNIT_TESTING namespace.
Add MODULE_IMPORT_NS() to the AMD DC test files so loadable tests
can still resolve those helpers.
Suggested-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Albert Esteve <aesteve@redhat.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Switch amdgpu_dm test helpers from the local STATIC_IFN_KUNIT
macro to VISIBLE_IF_KUNIT.
The two are not identical: STATIC_IFN_KUNIT was gated on
CONFIG_DRM_AMD_DC_KUNIT_TEST, while VISIBLE_IF_KUNIT is gated on
CONFIG_KUNIT. Helpers therefore become non-static whenever KUnit
is enabled, not only when the AMD DC tests are built.
However, given that DRM_AMD_DC_KUNIT_TEST depends on KUNIT,
tests remain behaviourally unchanged.
kernel-doc still needs to strip the qualifier. amdgpu_dm_color.c
is pulled into Documentation/gpu and several documented functions
use it.
Include <kunit/visibility.h> from dm_helpers.h, which is where the
local macros used to live.
Suggested-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Albert Esteve <aesteve@redhat.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Use plane_descriptors[k] for the loop bound, matching the loop body.
Fixes: 7f7d7ea1fa ("drm/amd/display: Add new sources for DCN6")
Reviewed-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Lu Yao <yaolu@kylinos.cn>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
dc_state_create_copy() can return NULL on allocation failure.
dm_suspend() only conditionally skips dm_gpureset_toggle_interrupts()
and continues execution, returning success. dm_resume() then
dereferences the NULL cached_dc_state in link_enc_cfg_copy() and the
following dc_state->stream_count loop, crashing during GPU reset
recovery.
Return -ENOMEM immediately if the copy fails, so the caller aborts
suspend instead of leaving a NULL cached state for resume.
Fixes: 8092aa3ab8 ("drm/amd/display: Add null checker before passing variables")
Reviewed-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Jiangshan Yi <yijiangshan@kylinos.cn>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why&How]
When building the DML files with clang without any sanitizer or LTO,
the following -Wframe-larger-than errors break the build under
CONFIG_WERROR:
display_mode_vba_30.c: error: stack frame size (2512) exceeds limit
(2048) in 'dml30_ModeSupportAndSystemConfigurationFull'
display_mode_vba_31.c: error: stack frame size (2416) exceeds limit
(2048) in 'dml31_ModeSupportAndSystemConfigurationFull'
display_mode_vba_314.c: error: stack frame size (2392) exceeds limit
(2048) in 'dml314_ModeSupportAndSystemConfigurationFull'
Clang consistently spills more than gcc, pushing the frame past the 2048
byte limit.
Apply an existing approach of increasing the warn stack size to the
non-sanitizer path so plain clang builds use a 3072 byte limit.
Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5642
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
UBSAN instrumentation adds checks and handler calls and increases
stack usage in the large DML calculation functions, similar to
KASAN and KCSAN. With UBSAN enabled these files exceed the default
-Wframe-larger-than limit and fail to build when -Werror is in effect.
Reproduced with LLVM (make LLVM=1, clang 19.1.1), CONFIG_UBSAN=y,
CONFIG_GCOV_PROFILE_ALL=y and CONFIG_DRM_AMDGPU_WERROR=y on x86_64.
[HOW]
Include CONFIG_UBSAN in the sanitizer check that selects the
higher per-file frame warning limit in the dml and dml2_0
Makefiles.
Suggested-by: Leo Li <sunpeng.li@amd.com>
Assisted-by: Copilot:Claude-Opus-5.5
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Use of compound literals to initialize heap objects may create stack
temporaries when compiling in debug mode. For large objects such
as dc_memory_pool which is 2 pages large to avoid cacheline sharing,
this causes function stackframe to exceed kernel limit.
[How]
Replace compound literal with field-by-field initialization.
Reported-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/all/aq0vYhZXtMqA41wZ@sirena.org.uk/
Signed-off-by: Dominik Kaszewski <dominik.kaszewski@amd.com>
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
If MODE.DST_VGPR_MSB != MODE.SRC0_VGPR_MSB upon trap entry then
v1 would be trashed.
Adjust workaround to prefetch random address 0xFFFFFFFFxxxxxxxx.
This address space is unavailable to userspace on gfx12.1, ensuring
no functional side-effects of prefetch.
Also remove unused WAVE_START exception handler.
Fixes: 0e1e0f87af ("drm/amdkfd: gfx12.1 add no-op prefetch on trap entry")
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Reviewed-by: Lancelot Six <lancelot.six@amd.com>
Cc: Joseph Greathouse <joseph.greathouse@amd.com>
Cc: Vladimir Indic <vladimir.indic@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Use scoped_guard/scoped_cond_guard instead.
Saving and restoring the GFP flags is not necessary in those use case.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Natalie Vock <nat@pixelcluster.dev>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The logic for checking whether NPM is enabled/disabled stays within the
particular IP version.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Advertise each NPM board attribute from a per-field R/W bitmap instead of
probing a single sensor. SMU 13.0.6/13.0.12 reports the cap only when NPM
metrics and MaxNodePowerLimit are present.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Assisted-by: Cursor Grok 4.6
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Smatch reports that link->link_enc is unconditionally dereferenced at
the top of dce110_enable_tmds_link_output() while the later
setup_ri_pj_check_in_sw_or_hw_mode calls guard against it being NULL,
making those checks contradictory.
Add an early return when link_enc is NULL and drop the redundant NULL
checks from the two call sites that follow, since link_enc is guaranteed
non-NULL past the guard
Fixes: 992694ad28 ("drm/amd/display: Enable DCN6 sources compilation")
Reported-by: Dan Carpenter <error27@gmail.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Roman Li <Roman.Li@amd.com>
Cc: Ivan Lipski <ivan.lipski@amd.com>
Cc: Dan Wheeler <daniel.wheeler@amd.com>
Cc: Alex Hung <alex.hung@amd.com>
Cc: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Alex Hung <alex.hung@amd.com>
Reviewed-by: Fangzhi Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This DC patchset brings improvements in multiple areas. In summary, we have:
- Increased KUnit coverage
- Reverts a patch causing regression on DCN42
- Fixes for cursor
- Imporvements for ABM
Reviewed-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
element_size_to_bytes_per_pixel() handled only element sizes 0 to 4 and
returned 0 for every other value, and an unexpected element size caused
a divide by zero.
[HOW]
Derive the size as 1 << element_size, which matches the existing
encoding, and fall back to 1 for values of 8 or more to keep the result
nonzero.
Reviewed-by: Austin Zheng <austin.zheng@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This reverts commit 555641725f ("drm/amd/display: Request DMUB HW cursor offload").
[WHY]
This commit causes the following failures on DCN42:
igt@kms_plane_cursor@viewport
igt@kms_plane_cursor@overlay
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Tony Qi <Haoming.Qi@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why&How]
The cursor programming path caches the last-written cursor state in SW
and, for the enable bit, skips the register write when the cache already
matches the request. Under cursor offload the SW cache is updated even
though the actual register write is deferred to firmware. When an
offloaded cursor update is aborted (e.g. an overlay geometry change
reprograms the cursor directly in the same frame), the queued firmware
write is dropped but the cache is left stale, so the following direct
programming pass skips the enable write and the cursor disappears over
the overlay plane.
Add a refresh_cursor_state() hubp/dpp hook that reads the cursor
position and attribute registers back from hardware into the SW cache,
and call it from dcn35_abort_cursor_offload_update() so the cache is
truthful after an abort. This keeps the enable-change optimization
intact for all ASICs and is race-robust regardless of whether firmware
applied the queued write before the abort. Only dcn60 (the sole offload
user) wires up the hook.
Assisted-by: Copilot:Claude-Opus-4.8
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why&How]
There can be more than 2 DCFCLK values for DCN6, so the assert is not
applicable.
Remove it.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit contains renames, adding const to pipe_ctx in
build_cursor_pos_update_params and also removing unnecessary checks
before dc_dmub_srv_is_cursor_offload_enabled().
[Why]
It improves code clarity.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
dcn401_build_cursor_position() clamped x_hotspot to 0xFF before
publishing *pos_out, but that field is also stored into hubp->curs_pos
and forwarded to dpp1_set_cursor_position(), which derives
src_x_offset from it. The ODM/MPC slice adjustments earlier in the same
function deliberately grow x_hotspot past 255 to keep the cursor
visible across a slice boundary, so the clamp corrupted DPP source
addressing in exactly the case it was meant to handle.
[How]
Clamp in hubp401_cursor_set_position() instead, where the 8-bit
CURSOR_HOT_SPOT_X field lives. A local is used for the register write
only; pos->x_hotspot passes through unmodified.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
UT mirror headers still declared the old prototypes and hwss_gtest still
called the callback directly. Separately, the divide by
param.pixel_clk_khz used to sit after hubp401_cursor_set_position()'s
"curs_attr.address == 0" early return; hoisting the math into the
builder moved it ahead of that guard, so it now traps on streams with
no timing programmed.
[How]
Guard the dst_x_offset block with "if (param.pixel_clk_khz)"
Route the test through hwss_program_cursor_position().
Update dc_hwss_ut.h / dc_hwseq_ut.h and the BLS docs to the new signatures.
Move the pos/param declarations to the top of the loop body.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Flatten the executor params for the initial set of HWSS block sequence ops
for SET_CURSOR_POSITION to separate SW and HW logic
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
pipe_ctx is not allowed to reach a block sequence step. Several operations
still carried it into the executor, which then walked the logical state at
execute time (pipe_ctx->stream->timing, pipe_ctx->plane_state and similar)
instead of acting on data resolved during build.
[How]
Give each operation a flat parameter list holding only the hardware objects
and values the final hwss call needs, and change the matching hooks to take
it. The function pointer, the params struct, the executor, the builder
helpers and all call sites are updated together.
Operations covered:
- OPTC_PROGRAM_MANUAL_TRIGGER - takes tg
- HUBP_PROGRAM_TRIPLEBUFFER - program_triplebuffer takes (hubp, bool)
- DPP_SETUP_DPP, DPP_PROGRAM_BIAS_AND_SCALE - take (dpp, plane_state)
- DSC_ENABLE_WITH_OPP - takes (dsc, opp_inst)
- OPP_PROGRAM_BIT_DEPTH_REDUCTION - opp
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
Clean up the AMDGPU DM KUnit tests after checkpatch reported an
invalid sizeof(void) allocation, typed kzalloc patterns, and a
repeated word in a kernel-doc summary. Clarify the test name that
covers an active CRTC state transition.
[HOW]
- Use sizeof(cpu_ptr) for the fake CPU pointer allocation.
- Replace typed kzalloc(sizeof(*object), ...) calls with
kzalloc_obj(*object, ...) in the connector, IRQ, plane, and
atomic-state tests.
- Rename the CRTC active-state test and update its kernel-doc and
suite registration.
Assisted-by: Copilot:GPT-5.6-Luna
Reviewed-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHAT]
Folding the MCCS FreeSync checks into the do_mccs block dropped the
other half of the original condition: the check that clears
freesync_capable for HDMI or PCON-in-whitelist sinks that expose no
EDID FreeSync VCP code. That check does not depend on the MCCS caps
and must run regardless of do_mccs.
As a result, when do_mccs is false such a sink without a FreeSync VCP
code is still reported as FreeSync-capable.
[HOW]
Restore the VCP code check outside the do_mccs block so it is
evaluated whether or not MCCS caps were read.
Fixes: 115bf5ca31 ("drm/amd/display: Consult MCCS FreeSync cap only if requested & supported")
Reviewed-by: Roman Li <roman.li@amd.com>
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
Writeback mode tests call drm_mode_probed_add without holding
mode_config.mutex, producing a warning for every generated mode.
[HOW]
Hold the mutex around writeback mode enumeration and release it before
checking the returned count or inspecting the generated modes.
Assisted-by: Copilot:GPT-6-Astra
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
Vblank and interrupt-management tests need discoverable CRTCs with
complete vblank callbacks and balanced teardown.
[HOW]
Add the callbacks, link the fake CRTCs, and register cleanup actions
to disable vblank before unlinking. Pass the CRTC directly so cleanup
does not reinterpret two different fixture types through one layout.
Assisted-by: Copilot:GPT-6-Astra
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
The MST add-connector fixture registers an unmanaged master connector
but does not clean it up before its KUnit-owned storage is released.
[HOW]
Register a KUnit action after successful connector initialization to
run drm_connector_cleanup before freeing the master connector.
Assisted-by: Copilot:GPT-6-Astra
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
IRQ tests leave vblank active when removing their fake CRTCs, causing
warnings during DRM device teardown.
[HOW]
Turn off initialized vblank before unlinking each test CRTC in the
existing cleanup action.
Assisted-by: Copilot:GPT-6-Astra
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
The real connector fixture lacks atomic state callbacks required by
DRM connector initialization.
[HOW]
Install the DRM atomic connector duplicate and destroy state helpers
alongside the existing reset callback.
Assisted-by: Copilot:GPT-6-Astra
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
The VRR transition test needs a discoverable CRTC and balanced vblank
teardown. Assertion failures must not leave freed CRTCs linked.
[HOW]
Supply a vblank counter callback and link the test CRTC. Register a
KUnit cleanup action to disable vblank and unlink it on every exit.
Assisted-by: Copilot:GPT-6-Astra
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
The cursor offset test binds a CRTC without a framebuffer, triggering
a plane-state consistency warning before the intended offset check.
[HOW]
Provide a test framebuffer in the new plane state while retaining the
invalid offset and its expected rejection.
Assisted-by: Copilot:GPT-6-Astra
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
Incomplete CRTC callbacks and vblank teardown cause DRM warnings in
CRTC tests.
[HOW]
Provide the required CRTC callbacks, link fake CRTCs for vblank lookup,
and register cleanup actions to disable vblank before unlinking them.
Assisted-by: Copilot:GPT-6-Astra
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
Connector mode population without mode_config.mutex produces warning
stack traces. Legacy property reads also warn on atomic DRM devices.
[HOW]
Lock mode-population calls and release the mutex before assertions.
Read stored property values with the atomic-compatible default getter.
Assisted-by: Copilot:GPT-6-Astra
Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
