When retry faults are disabled (amdgpu.noretry=1),
we should program the RETRY_PERMISSION_OR_INVALID_PAGE_FAULT
bit to zero.
Note that retry faults are enabled by default on GFX12.1
so this just fixes the case when they are explicitly disabled.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Remove the old direct submit path. This simplifies
the code.
v2: remove more local variables
Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
amdgpu_debugfs_vm_bo_status_info() prints the "Idle BOs" section by
iterating lists->needs_update, the same list already printed just
above under "Moved BOs". struct amdgpu_vm_bo_status has a dedicated
idle list, populated whenever a BO's state machine settles, but it
was never read here, so genuinely idle BOs never show up in the
debugfs output and the "Idle BOs" section duplicates "Moved BOs"
instead.
Iterate lists->idle for the "Idle BOs" section.
Fixes: 4cdbba5a16 ("drm/amdgpu: restructure VM state machine v4")
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
For different address types the variable PAGE_SHIFT might
not work well and it's better to use the GPU specific one
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
update the kernel docs for amdgpu_userq_fence_read_wptr.
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
amdgpu_vm_bo_lookup_mapping() expected callers to pre-shift the
address to a page frame number before calling in, unlike its sibling
functions amdgpu_vm_bo_map() and amdgpu_vm_bo_replace_map(), which
accept a raw address and shift internally. This inconsistency meant
every caller had to duplicate the same shift to make it pfn and many
place the shift is not AMDGPU_GPU_PAGE_SHIFT but normal PAGE_SHIFT too.
Move the shift inside amdgpu_vm_bo_lookup_mapping() and update all
callers to stop pre-shifting, so the function's calling convention
matches its siblings.
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The KFD/userq software oversubscription-notify timers added to
replace GFX11 MES firmware's oversubscription_timer call
amdgpu_mes_notify_unmap_queue(), which takes mes->mutex_hidden,
the same lock add/remove_hw_queue() use. Under SR-IOV this call
can block up to 9s (vs 2.1s bare metal), so MES round-trip latency
goes up (world-switch contention) it stalls re-mapping queues
and times out KFDQMTest.AllCpQueues.
Keep the firmware timer enabled for SR-IOV VFs and skip the
software timers there; the issue this works around is bare-metal
only.
Fixes: 590e266261 ("drm/amdkfd: workaround 100% gpu usage issue for gfx11")
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
FRL (Fixed Rate Link) is required to drive HDMI 2.1 high-bandwidth
modes and is broadly supported on capable sinks, but it was left
disabled unless a user explicitly opted in via the
amdgpu.dcfeaturemask module parameter.
Enable it by default by adding DC_FRL_MASK to the default
amdgpu_dc_feature_mask value, keeping the mask semantics unchanged.
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Switch remaining direct submissions to using a job structure for IBs.
This converts GFX, compute, SDMA, and VPE to using jobs. VCE, UVD, JPEG,
and VCN already did.
v2: fix missing ib pointer setup spotted by the kernel test robot
v3: rebase
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Update queue reset required MES version for MES 12.1 to 0x7b since we
change the implementation from detect-and-reset method to
per-queue-reset method.
Signed-off-by: Amber Lin <amber.lin@amd.com>
Reviewed-by: Michael Chen <michael.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Don't apply to KIQ. Seems to cause problems on KIQ
on some ARM platforms.
Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5658
Fixes: 91cf34bc5a ("drm/amdgpu/gfx8: align mqd settings with KFD")
Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Reviewed-by: Kent Russell <kent.russell@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
oversubscription_timer in MES is in micro second, so change the
timer's interval in KFD/useq to micro second.
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Suggested-by: Leo Lin <Leo.Lin@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
why:
HDMI 2.1 Auto Low-Latency Mode (ALLM) lets a Source request the Sink's
low-latency mode through the HF-VSIF. HDMI 2.1 Section 7.6.6 requires
that when Gaming-VRR is enabled (VRR_EN=1) and the Sink advertises ALLM
in the SCDS, the Source shall transmit the HF-VSIF and set ALLM_Mode=1.
amdgpu never set ALLM_Mode, so this requirement was not met.
how:
- In update_freesync_state_on_stream(), set ALLM_Mode=1 in the HF-VSIF
when Gaming-VRR is active (vrr state ACTIVE_VARIABLE/ACTIVE_FIXED,
i.e. VRR_EN=1) and the sink advertises ALLM, per HDMI 2.1 Section
7.6.6, and push the updated HF-VSIF (vsp_infopacket) as a stream
update.
- ALLM is driven by the mandatory Gaming-VRR case.
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Signed-off-by: Tomasz Pakuła <tomasz.pakula.oficjalny@gmail.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
why:
HDMI 2.1 sinks advertise their VRR range in the HDMI Forum VSDB
(HF-VSDB), but amdgpu derived FreeSync capability only from the AMD
VSDB. Sinks that expose just the HDMI Forum VRR capability (e.g. HDMI
compliance EDIDs) were therefore reported as not VRR capable.
how:
- In amdgpu_dm_update_freesync_caps(), when the AMD VSDB does not
provide a valid FreeSync range, fall back to the HDMI 2.1 VRR range
parsed by DRM core from the HF-VSDB
(connector->display_info.hdmi.vrr_cap). VRRMAX = 0 means "up to the
Base Refresh Rate"; when the EDID provides no monitor range maximum
either, fall back to the Base Refresh Rate (the highest refresh-rate
mode of the preferred timing) so a valid VRR range is still reported
to userspace.
- Add VRR debug logging along the FreeSync capability and config paths.
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Signed-off-by: Tomasz Pakuła <tomasz.pakula.oficjalny@gmail.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Parse the HDMI 2.1 gaming-related capabilities advertised in the HDMI
Forum VSDB (HF-VSDB) and expose them through struct drm_hdmi_info so
drivers can consume them.
Add struct drm_hdmi_vrr_cap describing the sink's VRR capabilities: Fast
VActive (Quick Frame Transport), Negative M VRR, Cinema VRR, MDelta, and
the VRRmin/VRRmax range, together with a "supported" flag derived from
that range. Add the fapa_start_location and allm (Auto Low Latency Mode)
flags to struct drm_hdmi_info.
drm_parse_hdmi_gaming_info() reads byte 8 of the HF-VSDB for the
FAPA/ALLM/FVA/CNMVRR/CinemaVRR/MDelta flags and bytes 9-10 for
VRRmin/VRRmax. Per HDMI 2.1, VRR is considered supported when VRRmin is
within 1-48 and VRRmax is either 0 (maximum based on the video mode) or
>= 100. It is invoked from drm_parse_hdmi_forum_scds(), and the parsed
values are logged for debugging.
Signed-off-by: Tomasz Pakuła <tomasz.pakula.oficjalny@gmail.com>
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Tested-by: Bernhard Berger <bernhard.berger@gmail.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The BAR0 fallback read path was introduced as a workaround for SR-IOV VFs
where the VRAM aperture is not available during early init. Restrict this
workaround to only SR-IOV VFs where it's needed.
Reported-by: gloveless@jqluv.com
Fixes: cba4928cdf ("drm/amdgpu: reduce early full GPU access during SR-IOV init")
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Link: https://patch.msgid.link/20260826185102.2269511-1-mario.limonciello@amd.com
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Explicitely set use_mmio_for_reset = false in gfx_v12_1_sw_init for
using MES to perform queue/pipe reset
Signed-off-by: Amber Lin <amber.lin@amd.com>
Reviewed-by: Jesse Zhang <Jesse.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
why:
HDMI FRL sinks were not parsed for the AMD VSDB and no VTEM info packet
was emitted for them, so 2.1 FreeSync over HDMI FRL did not work. It is
backward-compatible with 2.0 FreeSync.
how:
- Accept SIGNAL_TYPE_HDMI_FRL alongside SIGNAL_TYPE_HDMI_TYPE_A when
parsing the AMD VSDB in amdgpu_dm_update_freesync_caps().
- Build and send the VTEM info packet via mod_build_infopacket_vtem()
when the stream signal is HDMI FRL during the freesync state update.
- Set the VTEM Data_Set_Length to 0 when no VTEM feature is enabled.
build_infopacket_header_vtem() hardcodes Data_Set_Length = 4, so a VTEM
with Data_Set_Length = 4 would be transmitted even when no VTEM feature
is enabled (VRR_EN = 0 and no FVA), e.g. when the sink advertises
VRRMIN = 0 and vrr_capable is false. This fails HDMI GCTS HF1-58 step
6.2.
The VTEM must keep being transmitted every MTW while VRR is enabled
(HF1-58 steps 8.1 and 8.3), so it cannot simply be suppressed per
frame. Instead, follow the MLDS option in HDMI 2.1 10.10.2.4: keep
transmitting the VTEM but set Data_Set_Length = 0 when no feature is
enabled. When VRR becomes active the full Data_Set_Length = 4 payload
with VRR_EN = 1 is sent as before.
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
MES (Micro Engine Scheduler) does not perform heavy-weight TLB
invalidation after unmapping queues, unlike HWS which does this
automatically. This causes a race condition where in-flight DMA
descriptors can access memory that has been unmapped, leading to page
faults and GPU queue hangs during SVM page migration.
The issue manifests as KFDSVMRangeTest.MultiThreadMigrationTest
failures on gfx1151 (Strix Point) with XNACK mode 1 enabled - the GPU
compute queue hangs with packets submitted but never consumed.
Add kfd_flush_tlb() calls after MES queue removal in two locations:
- evict_process_queues_cpsch(): after all queues removed during eviction
- suspend_queues(): after debug/criu queue suspension (with mem_fence barrier)
This ensures all in-flight memory accesses from unmapped queues are
flushed before memory is freed or migrated.
Signed-off-by: Priya Hosur <Priya.Hosur@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The id is claimed before the banks are read, so a poll that ends up
logging nothing still burns one and leaves a gap that every reader of
the log then has to walk over. Claim it when the first record of the
batch is about to go in.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The caller walks the log with cper_start_id and resumes at
cper_start_id + real_cper_num, but the reply only counts the ids that
held a record. A batch id that holds nothing therefore never moves the
caller forward, and every such id makes it read the next populated batch
one more time. Count the ids covered instead.
The rewind to the last populated batch when the query starts at the end
has the same effect once the caller has drained the log, and the latest
id is already reported by the snapshot query, so drop it.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
In function amdgpu_userq_fence_signaled rptr
is a confusing variabile name as it is a fence
value written by the cp in the fence address and no
where related to the rptr.
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
In function amdgpu_userq_fence_driver_process
rptr is a confusing variable name as it is a fence
value written by the cp in the fence address and no
where related to the rptr.
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
A bank carrying the scrub bit was found by the background scrubber
rather than by an access, which is worth telling apart from the rest
when reading a log.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The prefix marks the files that back a hardware IP block. ACA is a bank
format rather than an IP, and the rest of its files are named after it
alone, so the v5 pair is the odd one out.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Replace spaces with hyphens in amdgpu_tlb_fence_get_driver_name() and
amdgpu_tlb_fence_get_timeline_name(). Returning string literals with
spaces makes ftrace fence events and debugfs fence entries visually
ambiguous and harder to parse using standard log analysis tools.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Outside of UMC a bank with the poison bit set describes the consumption
of an error that was already reported, not a new uncorrectable one.
Injecting an uncorrectable error while a workload is running therefore
buries the real bank under a dump of GFX poison banks collected from
every other device of the hive.
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Correct GFX_IMU_MCM_ADDR_LUT_PF register value to suit
for xcc harvest situation.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jinzhou Su <jinzhou.su@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Support for partition mode to program MCM_ADDR_LUT.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Encode mcm address look up table in SPX mode
as a temp solution.
v2: fill in when interface is ready (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Support for partition mode to program MCM_ADDR_LUT.
v2: clean up (Alex)
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
VMEM instructions may hang after trap exit. Issue a no-op
prefetch to reset wave VMEM state.
v2: squash in preserve SCC on trap entry
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Cc: Joseph Greathouse <joseph.greathouse@amd.com>
Cc: Michael Chen <michael.chen@amd.com>
Cc: Lancelot Six <lancelot.six@amd.com>
Cc: Vladimir Indic <vladimir.indic@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
on gfx12.1 trap handler
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Jay Cornwall <jay.cornwall@amd.com>
Reviewed-by: Lancelot Six <lancelot.six@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
to support gfx12.1.0 PC Sampling.
Co-authored-by: Lancelot SIX <Lancelot.Six@amd.com>
Co-authored-by: Jay Cornwall <jay.cornwall@amd.com>
Co-authored-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Jay Cornwall <jay.cornwall@amd.com>
Reviewed-by: Vladimir Indic <Vladimir.Indic@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
to support multiple processes, and process correctly when s_trap
and context saving exception occur simultaneously.
-v2: update comments advised from Lancelot
-v3: update advised from Jay
-v4: remove state bit S_SAVE_PC_HI_NEED_2ND_LVL_TH_SHIFT
-v5: add STATUS.HALT handling
Co-authored-by: Lancelot SIX <Lancelot.Six@amd.com>
Co-authored-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Lancelot SIX <Lancelot.Six@amd.com>
Reviewed-by: Jay Cornwall <jay.cornwall@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DPX is unsupported on GC 9.4.3/9.4.4/9.5.0
skip these 6-XCC parts,so do not advertise it.
Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add DPX to the 6-XCC supported mode mask
This allows DPX to be advertised and selected
Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DPX currently advertises only NPS1 as a compatible memory partition
mode in soc_v1_0_get_xcp_res_info(). As a result, supported_nps_configs
and amd-smi partition --accelerator report NPS1 for the DPX profile even
when the device supports both NPS1 and NPS2.
Include NPS2 in the DPX compatible NPS mask so the reported profile
capabilities match the supported memory partition modes.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reset the partition count and free the buffer on gmc v12 sw_fini
during driver unload.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add the nps sysfs node for GC 12.1.0
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add nps supported modes init for gc 12.1.0
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Software components need to detect die revisions in order to apply the
correct software workarounds. During system boot, ASP firmware reads
the IDCODE values from the MID, AID and XCD fuses and encodes the die
revision into die_info[0].die_id in the IP discovery blob.
v2: Default die_rev_id to 0 and warn instead of failing probe when IP
discovery does not provide a die rev id.
v3: Update names for external_rev_id enumerators.
Signed-off-by: Horatio Zhang <hongkun.zhang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Track discovered LSDMA instances in inst_mask and clear harvested
instances when processing the harvest table. Report the harvest state
through IP discovery sysfs for LSDMA v7.1.0.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Clear harvested MMHUB instances from mmhub.inst_mask when processing
the harvest table. Report the harvest state through IP discovery
sysfs for MMHUB v4.2.0.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Expose the cached MEM_RESERVED_INFO discovery table via a per-device
sysfs file:
/sys/class/drm/cardX/device/mem_reserved_info
The file is read-only and dumps every region as:
list_num=<N>
[<i>] id=<id> (<name>) size=0x<size> start=0x<start>
Only created when the table was successfully resolved at discovery
init time.
Suggested-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Walk the cached MEM_RESERVED_INFO table once at discovery init time and
log every entry (region id, symbolic name, size, start). Add for
debugging purpose.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Extend amdgpu_ttm_init_fw_resv_region() to honour the
->get_fw_reserved_info().
Previously the FW carveout was hardcoded and placed at the top of VRAM
(real_vram_size - reserve_size):
- a hard-coded 144/256 MB for GC 12.1.0;
- or DISCOVERY_TMR_OFFSET fallback.
The hard-coded GC 12.1.0 path is replaced by ->get_fw_reserved_info(),
which returns a (size, offset_within_VRAM) pair derived from the
MASTER_DIE_UMF_REGION embedded in IP discovery, and falls back only
when the discovery region is missing or invalid.
v1->v2: Remove !adev->bios check, and call the get_fw_reserved_info
interface when it is available. (suggested by Hawking)
Suggested-by: Lijo Lazar <lijo.lazar@amd.com>
Suggested-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
If reading mmDRIVER_SCRATCH_2 returns non-zero, discovery.reserve_tmr
is set to true and driver need reserve tmr for firmware.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Suggested-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
