This series updates various DT bindings for Tegra architecture,
primarily focusing on schema validation fixes and new feature
documentation for Tegra234 and Tegra264 SoCs. Key changes include
converting Tegra20 NAND bindings to YAML, and updating memory, DMA, and
IOMMU definitions for Tegra264 (introducing CMDQV and DBB clock
support). Additionally, it resolves legacy warnings for Tegra30/132
display and VI interfaces.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAml4j/gACgkQ3SOs138+
s6FE+g/+KBy7GVuhVBQtGU5TWTV0NpDTonSHQBZXnslvFx91I0zDXqKOGEEKPFwH
RykvftVjbZ1LkwnP5Ow7BeQqF602CACPa9UJY3mavnvdDIWdTCwnUH2VbE+3JjO+
JS5pfR5WB01jAUCydKFYwCZ7+3eeArHO5DUO2h2f/SHqJCpUfggxmuBlGn2FfLwo
aAQwpjiLPWmlFz2Rg8sbl+ENqEA0yKZO9uSSO3N6gdNM7vggeFSizPKahc+jV6eE
+WL5Z6dZGB67288SUHHOEU60zzoDs1s50EjF2/kLmXWAowNO8HDmK191y1zHnmoJ
USzl8fdHmJ0bktUKDJE6Dlu+O0xaJmdz4s/bumgW3qi/e1aDtUrT9yOOgPvhAnjm
ZIppsjm/AUx/abECIVSxr3xlSkyyVjNX1Wswjjf4t62K/QxITjGhDsvNQrzwRrcY
LpJ/RL7n/07bM3RJ/iONkeBLyCjHjpWkIG5/vjbnGbTrqv8R8eXR4bKe0vqOry1P
/HxAE3sURx8wSFAdYFx8vtCOby904BeiWoMrORPnc3GXCAJlHRgoSTfUogE4soiR
l08hHyGoW1NDHsyXu2I+mHhoRKUhwYgIT0a+sBX++cbetTNhkkPKvN+QVIV317R5
XcYKqQcGgtwZDDQ+4L4cM2HG7CP6v5pRelp0lzX8AFuo/zvchB4=
=KbrZ
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-6.20-dt-bindings-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
dt-bindings: Changes for v6.20-rc1
This series updates various DT bindings for Tegra architecture,
primarily focusing on schema validation fixes and new feature
documentation for Tegra234 and Tegra264 SoCs. Key changes include
converting Tegra20 NAND bindings to YAML, and updating memory, DMA, and
IOMMU definitions for Tegra264 (introducing CMDQV and DBB clock
support). Additionally, it resolves legacy warnings for Tegra30/132
display and VI interfaces.
* tag 'tegra-for-6.20-dt-bindings-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: display: tegra: document Tegra30 VI and VIP
dt-bindings: display: tegra: document Tegra132 MIPI calibration device
dt-bindings: mtd: nvidia,tegra20-nand: convert to DT schema
dt-bindings: dma: Update ADMA bindings for tegra264
dt-bindings: iommu: Add NVIDIA Tegra CMDQV support
dt-bindings: memory: tegra: Document DBB clock for Tegra264
dt-bindings: tegra: pmc: Update aotag as an optional aperture
- A few changes from Andreas Kemnade to correct LCDIF compatible
for i.MX6SL/i.MX6SLL, add EPD regulator for imx6sll-kobo-clara2e,
support TPS65185 for tolino-shine2 and e60k02
- A series from Frank Li to clean up GPMI CHECK_DTB warnings
- A change from Alexander Stein to add default GIC address cells
for imx6qdl
- A change from Josua Mayer to add EPD PMIC for imx50-kobo-aura
-----BEGIN PGP SIGNATURE-----
iQEzBAABCgAdFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmluy0cACgkQUFdYWoew
fM68EQf+LlvId0IYp38a+tejJQUJ6MoQpy2hpX/0fFQ0OfUvZOkiR0nMTVkDyrC8
aaG3Ywig8nYLL3aoL6HkXZAFsb17yAX3xaWoqY2BFoWWZHilEKT8wT7tOwCLw/uO
u2Rvc32MkH3K+d3/I7SOaysGMQ0s+2xPS+lEeQ0SVZgz0n9MpCy+3FQTNyBFy0Bg
eFzJLGLNmy/hvJTaZPs7+pZ/4XIBVXuB6VSf7s5HuT7eQSqL9CXGtGVuXDIxK3Tw
APE4a19D6/toKa5SQGUeJ46XpPwBEosAIr/7v5Gex94g2WelGcClTJJB7DzFvJMc
cGEadGZ1tGGDfs9giZ/+a7km2KVTgw==
=qGS7
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml3j0QACgkQmmx57+YA
GNm34hAAwhKqqO5upJ3Gzl86BqzxLs8axHIhhd1Qh3zvizDyRvVIcoCR8Pd40aA9
zCeccYBa2xmyE4X4VPTYt8rWQSw60jbL5bQq65+6naOoJaH6v891ZgvQgBuXTUqe
/F0ze9EZ+DZbSnquEAQD7OStVb3lhuMkxKh6tELxO5oQdvoNysWe0IOhmEJ5hhdq
ELL0Pd3+SU0PNy2lxvpPwKX+EgVYYBS5jR9rnR80sbQHlxMfROuMrDkuFSUb7Wxe
0K7gwucj8dwt147I+/nmbvSompSa4hzplHQiEPTlrS3zC58DEGm6+O2GAiNdYEPQ
K4FCBSQd1CE0LlthoOAksYiht1Ekbhakwzj6VLLwt3RbqtURCRvR8aDl+kcDCZpP
I5EeNdACmoGMlouSH8hmxolyEDj6SD+be8yJoC4QSeYWtBj7m/+xk8jk0aMivVG2
bpyGdxPMMzGfSIycX4JsDZB/hDebAkLDVgCEm6+E/WwslS+/VBqbCJb9Func//ib
qwhtMoSCipF7Y7pqGQs4UjhmEnpFzbUmT39EXGSHoIRTJEg+Yoaz/zqTki4V8OsT
auNCeMwnADmi8+yquvpS9uvBiO2nNP4KlG1LdhBp5wTYjeDFU3ar3ZcEyikd2pD6
v10hMK+6Cqh1x7rn+uRtU1g+LC356hYHDqdaMxDpUOx6dizjj5M=
=F0gJ
-----END PGP SIGNATURE-----
Merge tag 'imx-dt-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
i.MX ARM device tree changes for 6.20:
- A few changes from Andreas Kemnade to correct LCDIF compatible
for i.MX6SL/i.MX6SLL, add EPD regulator for imx6sll-kobo-clara2e,
support TPS65185 for tolino-shine2 and e60k02
- A series from Frank Li to clean up GPMI CHECK_DTB warnings
- A change from Alexander Stein to add default GIC address cells
for imx6qdl
- A change from Josua Mayer to add EPD PMIC for imx50-kobo-aura
* tag 'imx-dt-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: imx: e60k02: add tps65185
ARM: dts: imx50-kobo-aura: add epd pmic description
ARM: dts: imx: tolino-shine2: add tps65185
ARM: dts: imx: move nand related property under nand@0
ARM: dts: imx6sx: update gpmi #size-cells to 0
ARM: dts: imx6qdl: add '#address-cells' and '#size-cells' for gpmi-nand
ARM: dts: imx: imx6sl: fix lcdif compatible
ARM: dts: imx: imx6sll-kobo-clara2e: add regulator for EPD
ARM: dts: imx: imx6sll: fix lcdif compatible
ARM: dts: imx6qdl: Add default GIC address cells
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Introduce the Kaanapali SoC, with the MTP and QRD devices. Introduce
support for the Milos SoC (SM7635) and initial support for the Fairphone
(Gen 6) device on this platform.
Add the QCS6490-based RubikPI3 board, the QRB2210-based Arduino UnoQ,
the X Elite-based Medion SPRCHRGD 14 S1 and Surface Pro 11 laptops, and
the SDM845-based Pixel 3 and Pixel 3 XL devices.
On the Kodiak-based (QCS6490) RB3Gen2 the TC9563 PCIe switch controller
is described.
On Lemans (SA8775P/QCS9075) the GPU and crypto blocks are added.
IO-regions and clocks are added to interconnect nodes to allow QoS
configuration. GPU, TPM and USB support are enabled on the evaluation
kit (EVK).
On Monaco (QCS8300) the two PCIe controllers, the camera subsystem,
tsens, display subsystem, crypto, CPUfreq, and coresight are added. On
the evaluation kit (EVK) the PCIe busses are enabled, together with an
AMC6821-based fan controller and the ST33 TPM chip.
On MSM8939 the camera subsystem is described. The Asus ZenFone 2
Laser/Selfie gains battery and hall sensor support.
On the Agatti-based RB1 board PM8008 is described and an overlay for the
Vision mezzanine is introduced.
On SDM630 the compute DSP remoteproc, FastRPC and related entites are
described. The LPASS LPI pinctrl node is described.
On SDM845-based OnePlus device the bootloader framebuffer and its
resources are described, to improve the transition. On the SDM845-based
devices from OnePlus, SHIFT, and Xiaomi ath10k calibration variants are
specified. The sensor remoteproc is enabled on Xiaomi Pocophone F1.
On SM7225-based Fairphone FP4 regulators for the cameras are described,
and the camera EEPROM is added.
On SM8650 the camera subsystem is described. On the QRD the Samsung
S5KJN1 camera sensor is added, and for the HDK an overlay for the "Rear
Camera Card" is added.
On SM8750 CPUfreq, SDCHCI and Iris (video encode/decode) support are
added, and missing - required - properties for the BAM DMA is added.
These are then enabled on the MTP.
On Talos (SM6150/QCS615) PMU, DisplayPort, and USB/DP combo PHY are added.
DisplayPort is enabled on the Talos Ride board.
On Hamoa (X Elite) add crypto engine, missing TCSR reference clocks, and
random number generator block. The soc bus address width is corrected to
match the hardware. On the Lenovo Thinkpad T14s HDMI and audio playback
over DisplayPort is introduced. HDMI, Iris (video encode/decode) and
PS8830 retimers are described for the ASUS Vivobook S 15. On the Hamoa
evaluation kit (EVK) PCIe busses, WiFi, backlight, TPM and RG
(red/green) LEDs are described.
Enable QSEECOM, and thereby UEFI variable access, on the Medion SPRCHRGD
14 S1 (commit should have been on drivers branch).
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmluY0UACgkQCx85Pw2Z
rcULshAA2wZmfS4CeeZjIGUMbZg+ntby1xUJ4cKTeUR9IDd86L57qAkhHCNaP/ST
8ta22+4W9uId2zDTyxxmXbf5rTLIkc+t0dLjkl48HHmu6Kmxc2qALwcW7m2Cw/AI
3MAXUxVMmTM8BKvxSqW4lzNtQehxMXuErxXzVyUdzHMyiard25HUmXuMTsbIcteK
yXr+SsAfisSjLTYAYhXkRihPK6OqYO9LkO1pah1Uf1pFY4FtJCbCEQR3a4uSTaQf
u/NMQAc83LcboM2al1eHVU9fCeoA/oH/i6VZfpEAQLFf7cvsDP6f8CZF8RDWs1NE
CdISQQdZxmgIfCawq5yt2765NR91Q8E64e49GSi56FWTEX+WBdohLR1qRLl7OrNM
/rlvB29GhFTpxCjV5JwoAGacS3dn2MScNSXQSQNMRZBpDgGMM2PtnyOc+IhjMb+2
vOZrU+RS7eph6d9++yrIAMZfnEo8NtwVo0Eu3n0LmPmn4PK/2Kc+OS0Vc8r7IwBI
qrAj4kkFGsMkfTEH2m4OO3lFH/Dw04E/YX1bSx3uFBkf8oQZrzmQJmn6kUT2MY0a
9rIJgnoo1R8d6MRAFkEKQqaRisWqEhnN3EZvn1bQj+0HlC5o3AHgjZQhwuZ/y/3B
DvD7sSV1qSkbF/Dxcy4VRXZI+T6PgybrbL/yF+CD6cZiR4Grw8w=
=qT6q
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml3gp8ACgkQmmx57+YA
GNmhbA//bKzmRMoV1kx7czXgCfAbSq0SAUNbHs294Zkog/8ILBWnSYiS1smMlKfe
W7c9x/7QT1myy2TiEZ2wDGzGWC/7benTu5HHGSL+UTSc3vVfKb3wpN021kuhxfhW
fNpATd6oiOtuGfURgaZlXHaJlDS8TDXr+jJ8lgDKUuMmyJPpBf265/eyS8pSCoVR
l6ImLT3Im2G4qXhYV7LzApTqe3wu6H6AW2EGPrAHWz4WrebTOzAr2yEY0CPOsPqA
EnF2slYnPsRYz7RwkBwXM8gSX7711iGwOp/xQWIqmZxHaQa915w816bnPLzWxJTg
j384ly4sJw/C047iLQdZBaqgGGU9Pu8/3iK1K0mlnfc3NmF1KeaSu3KKB4XxLkF/
+zw1gFjU6xCbfphHk44f8+hQdsIDa6wpL2jV4VdAE989wtOH2pIPS1WRboZCcvLz
LummFnQigACAfwKygnmHGIEtVA1rw0U5wfRdvVq2slv2Kfrye5x92QgY/euuR2wW
7XWIubZESPHqvBPSa2bG7XNcd5gG+EaSZg0apJ6s9JbMm1PHjtKbnEqmv2E5GYUE
bO3/XPrAalQ+bpN7TvCPkoFgD3Qr6SPK1Du/zQgIf0i5L/CGKKdaE/EVcmXSOOPR
4MH7kQQx7zcQ6i2OUOfDuGZemGGLOXXRZmGsJpY686gsLg6FYN8=
=3Isi
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-for-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm Arm64 DeviceTree for v6.20
Introduce the Kaanapali SoC, with the MTP and QRD devices. Introduce
support for the Milos SoC (SM7635) and initial support for the Fairphone
(Gen 6) device on this platform.
Add the QCS6490-based RubikPI3 board, the QRB2210-based Arduino UnoQ,
the X Elite-based Medion SPRCHRGD 14 S1 and Surface Pro 11 laptops, and
the SDM845-based Pixel 3 and Pixel 3 XL devices.
On the Kodiak-based (QCS6490) RB3Gen2 the TC9563 PCIe switch controller
is described.
On Lemans (SA8775P/QCS9075) the GPU and crypto blocks are added.
IO-regions and clocks are added to interconnect nodes to allow QoS
configuration. GPU, TPM and USB support are enabled on the evaluation
kit (EVK).
On Monaco (QCS8300) the two PCIe controllers, the camera subsystem,
tsens, display subsystem, crypto, CPUfreq, and coresight are added. On
the evaluation kit (EVK) the PCIe busses are enabled, together with an
AMC6821-based fan controller and the ST33 TPM chip.
On MSM8939 the camera subsystem is described. The Asus ZenFone 2
Laser/Selfie gains battery and hall sensor support.
On the Agatti-based RB1 board PM8008 is described and an overlay for the
Vision mezzanine is introduced.
On SDM630 the compute DSP remoteproc, FastRPC and related entites are
described. The LPASS LPI pinctrl node is described.
On SDM845-based OnePlus device the bootloader framebuffer and its
resources are described, to improve the transition. On the SDM845-based
devices from OnePlus, SHIFT, and Xiaomi ath10k calibration variants are
specified. The sensor remoteproc is enabled on Xiaomi Pocophone F1.
On SM7225-based Fairphone FP4 regulators for the cameras are described,
and the camera EEPROM is added.
On SM8650 the camera subsystem is described. On the QRD the Samsung
S5KJN1 camera sensor is added, and for the HDK an overlay for the "Rear
Camera Card" is added.
On SM8750 CPUfreq, SDCHCI and Iris (video encode/decode) support are
added, and missing - required - properties for the BAM DMA is added.
These are then enabled on the MTP.
On Talos (SM6150/QCS615) PMU, DisplayPort, and USB/DP combo PHY are added.
DisplayPort is enabled on the Talos Ride board.
On Hamoa (X Elite) add crypto engine, missing TCSR reference clocks, and
random number generator block. The soc bus address width is corrected to
match the hardware. On the Lenovo Thinkpad T14s HDMI and audio playback
over DisplayPort is introduced. HDMI, Iris (video encode/decode) and
PS8830 retimers are described for the ASUS Vivobook S 15. On the Hamoa
evaluation kit (EVK) PCIe busses, WiFi, backlight, TPM and RG
(red/green) LEDs are described.
Enable QSEECOM, and thereby UEFI variable access, on the Medion SPRCHRGD
14 S1 (commit should have been on drivers branch).
* tag 'qcom-arm64-for-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (155 commits)
dt-bindings: mailbox: qcom: Add IPCC support for Kaanapali and Glymur Platforms
dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings for Kaanapali
arm64: dts: qcom: lemans: enable static TPDM
arm64: dts: qcom: kodiak: Add memory region for audiopd
arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: add HDMI nodes
arm64: dts: qcom: x1e: bus is 40-bits (fix 64GB models)
arm64: dts: qcom: lemans; Add EL2 overlay
arm64: dts: qcom: sm8150: add uart13
arm64: dts: qcom: sdm845-db845c: specify power for WiFi CH1
arm64: dts: qcom: sdm845-db845c: drop CS from SPIO0
arm64: dts: qcom: qrb4210-rb2: Fix UART3 wakeup IRQ storm
arm64: dts: qcom: sm6125-ginkgo: Fix missing msm-id subtype
arm64: dts: qcom: qcs8300: Add GPU cooling
arm64: dts: qcom: sa8775p: Add reg and clocks for QoS configuration
arm64: dts: qcom: hamoa-iot-evk: Enable TPM (ST33) on SPI11
arm64: dts: qcom: talos: Add PMU support
arm64: dts: qcom: talos: switch to interrupt-cells 4 to add PPI partitions
arm64: dts: qcom: ipq9574: Complete USB DWC3 wrapper interrupts
arm64: dts: qcom: ipq5018: Correct USB DWC3 wrapper interrupts
arm64: dts: qcom: monaco: Add CTCU and ETR nodes
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Migrate the MSM8974 remoteproc power supplies to RPM provided
power-domains, to match what is done on most other platforms.
Give the LG Nexus 5 its more human friendly model name.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmluVn0ACgkQCx85Pw2Z
rcUaUQ/+Murq/FagYIODDX7uz1Expmnwo+WV7yRUbwNC27u79YYx+jEa2M7D7dU1
NzRWJVozK/o0jUBREjyO9zToDTL2pXBxx/E7ymlICVZA8TRH+M8gktxwbEJ3TnQc
7BJ44sZK7d3ZtAKocFCaMfq2WSjEgS8R8CnULZ1gIyy9Z8Be/L3mMjxZycrgVjqj
JGO1g5sKG3Nmi96sfYutCtEEj1D7ZpJTGye+5v3XEXjJ9qn5DeE+wYthb4GW1gL4
RYjUuwNIdzwm3+Rjy+ThQbPNIWU+bgxlQZFFJdHxTtDx9tl6ex1rrvqUKGwZJb/K
63z3Cj3Jk+oIgWTNhyCws037g5O+35+trjGJoYFl/T+cnXCijrAl5QnEs311HvBA
mf8QXcod7DUpvUiYtKn5qFzZfUf603/u3dP+vvzb9GD/IvZOwfjkzcHs8AWJF5yB
rSPaWY5bs/Cr5ryW6shO5UKp0Ad6YuDQ9gPweSFRc2CdmeYB3cA5uh0/D8D0Yj2W
7PmIk6VHRCi/Za89FB6/6lwGzsrPlBA7I51mLcdeN0W2FHRu8NuDnpp1BbAOrvya
SNZva+EN6W1nBIdfFnL28JoqVBN0rsIOmP+wihbDsjWMjwx5chTwo5buueV63QRg
teY57KpA8WXqzEWlkAGGVrGdjMUWcgIZQQqWcFINe+aOnLPgmCw=
=YBqC
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml3gnEACgkQmmx57+YA
GNkFqxAAujieZ00MAgjrJqMU1d8HfDIHLodWagTLuKL7168NOLS2++pl8a9vozMR
CsZpyVvTlChR2uk7cd2GaEVj+wqGCAfI2+BybxXFF1F4B1BDjOxNd29UlOZyF5qQ
qfj5+AFb16HrQv61He9rNUiesCPAn407ZZIzPk3QDBNnJUhYGjcONDnOjWy9/gp9
u/c1MaSVnxyk+LvyZqilkxe8lLv36SADPMdlSuLAZoEEEExVQRHAnt0mAIcuCBOZ
32JHYBWHpqMY/hyUfzXQ7gYNeLt0eJqe20VSyg6f6N/sTXHPgD1IaGdmlu8wx2e/
5rn5bo4SNjic8HuPtfzShWrK4X52BYsjHa7WfeNsWFT7EGOqJ7XtcFHFKFl/Em6X
8T5o8WricK7wPA/bSw6z8PZl0wd76iPp1XSw23x2VbrbDuU4F+4jeqOteZ7K+k4U
hJYLfbwMjojh59HQv+cOwdv3wWlbbLNU77PZX71jVUh716qH4abAuAWCLGlpj2Kv
6j5DWQfnzeUS9CFu7UJKHw83VBQ4col05OD6bxrh/1G8biH9bjEgQn1hgA/uKdF9
oxLl2ID+RX8vcGpMmjearkDe2SP0nxl4N1FkcFpnIj2+d6+QlFnrH1gsQjDbx6PB
Zy1ZwWiDzOQnIahZ59okoCSaMX0sn2nb6JefE70ka6cckSuewAo=
=p877
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm32-for-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm Arm32 DeviceTree updates for v6.20
Migrate the MSM8974 remoteproc power supplies to RPM provided
power-domains, to match what is done on most other platforms.
Give the LG Nexus 5 its more human friendly model name.
* tag 'qcom-arm32-for-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
ARM: dts: qcom: msm8974: Start using rpmpd for power domains
ARM: dts: qcom: msm8974: Sort header includes alphabetically
ARM: dts: qcom: msm8974-hammerhead: Update model property
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This update improves Device Tree support for 64-bit Tegra platforms,
specifically focusing on the Smaug board and the Tegra264 SoC. It
enables full USB-C functionality on Smaug by adding role-switching
support and enabling DisplayPort altmode. For Tegra264, it introduces
nodes for Command Queue Virtualization (CMDQV) in the SMMU, adds the
Data Backbone (DBB) clock for the memory controller, and corrects CPU
compatible strings to match the Neoverse V3AE core. Additionally, it
performs a cleanup by removing redundant status = "okay" properties
across Tegra186, Tegra194, Tegra234, and Tegra264 files.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmlskkoACgkQ3SOs138+
s6Hs7Q//fo3H7xm77b5gmYO2/+gMPF33J0D0xveF1X8S25+I5UgRYNqucHJatZ5Z
e1CzTWxmM53Y1On+k06B9JOy8dnrT5F75U8h7MvfSY9ZiInJjoKhvDAlc64T6Dag
U658zYGThWmQt3zmORFEANYb24YX+VnSuDQysrBqynTXPtBIr/jXnrQiPWBsMToe
m1Uo2/QISRegFujlMGaKn6mvPrajFJr9xa3s+83LZV72Lhl7e3ESbba7Kf0wN76M
vvtdt6vshc0IknH8SUWDmnyxg9B72TXrVvUkQ9GOdPN+FNdXvMWdMiR2iVWGAA9a
EjnOiHFND8qgRqa19j8x95oyRzEicARqSTGW2bC3gAji5+hhCOmz0u5QkxTFYKKd
HynJdOTt0p5QsZvyYACLsLVzY6Cx4w8Fc7+q7fq7IVxududHHAHQzLSXVhFT6xpt
5llD4HN10Gizc/xFdL6cGvGQ3nbmh0OMbSCnl4nQfhXHjMLaSuIvDnYImiU5+tY9
mkic1zSeoigF4FtIvnaQ4PjSsq/ypNQnE84I/aUMFBGzBdnyYnvsZHKZvfz7O/nB
JZYYzsjxK4MaldOAlyQVlHbIhedJYwv+Fgpq8YZBLwghZMcnsQ1I5uBacEQjUA/5
YN4BiDS12im3l3EmW4fqbo/aSS4PLa7Rkllr3966F4ObQmCtz6Q=
=AQ07
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml3ficACgkQmmx57+YA
GNkzZQ//R5Vf1w4e5iy66snGQ24R/d/zx0lS7+avsbZY1dIfqYdu5mbIXGixv/sC
WZ0g00vPF8QmIO+23DLPQIlfwI9Jzqu03KxlnoCxGjtfDz8k1ntJBTCT92+dgtrn
FtgPjQf5CFhj+QP4WA5YysQch7Jbxg+PBKtp2YeYJW8UuY2leJJlojgGxNWE8Izu
5z86Ceog8Uu9dKe7zVFoDJNyd8FDxg185OLVbHaOenhYTZKd4lsdpo6N4EDJu/j2
QVmIXdi+kBvzW/RXwJFcEBybP2kQghVISbH0R5Oc+oyUNT/Z52e9HuYHW5b1Hlre
NQT8ZJ5hHmM5i7izWSVIyC7cTPRh9VpABzfDQberx+ihWEeGdD6QaPd1UmHTs9Qq
1qdEqmQL5zRCjY/rqL2uUQPN2TfTZvznizCpzUD44CiDQu/zoRV/6CdlZWRBKnDa
Z+9iGtyNPzgNyVK96TJ7HZd1Gd8GxxfRJUCako5kHGOdHoft5UBngELvGSPKMwZN
RHYNyFphCNmpMvfyL8ZhywyVViTpPYY9LyzKJTZOya5wuQeXjwGuvoszLuaLyHCw
aexmDshstEUdf9j6VA/hQcD9lCi14dWQzMdjbNzZrqkVd5BoJDycdHwmqzZOTc/i
Xl8rtySU61G8ZHstfTPpSwGrBK2r1PXBBK9xo8t4dKqODxh4IFw=
=4UL9
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-6.20-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
arm64: tegra: Changes for v6.20-rc1
This update improves Device Tree support for 64-bit Tegra platforms,
specifically focusing on the Smaug board and the Tegra264 SoC. It
enables full USB-C functionality on Smaug by adding role-switching
support and enabling DisplayPort altmode. For Tegra264, it introduces
nodes for Command Queue Virtualization (CMDQV) in the SMMU, adds the
Data Backbone (DBB) clock for the memory controller, and corrects CPU
compatible strings to match the Neoverse V3AE core. Additionally, it
performs a cleanup by removing redundant status = "okay" properties
across Tegra186, Tegra194, Tegra234, and Tegra264 files.
* tag 'tegra-for-6.20-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: smaug: Add usb-role-switch support
arm64: tegra: smaug: Complete and enable tegra-udc node
arm64: tegra: smaug: Enable DisplayPort via USB-C port
arm64: tegra: Correct CPU compatibles on Tegra264
arm64: tegra: Drop unneeded status=okay on Tegra264
arm64: tegra: Drop unneeded status=okay on Tegra234
arm64: tegra: Drop unneeded status=okay on Tegra194
arm64: tegra: Drop unneeded status=okay on Tegra186
arm64: tegra: Add nodes for CMDQV
arm64: tegra: Add DBB clock to EMC on Tegra264
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
1. ExynosAutov920:
- Add MFD clock controller node.
2. Google GS101:
- Add True Random Number Generator (TRNG) and OTP nvmem nodes.
- Correct the PMU (Power Management Unit) compatibles by dropping
fallback to syscon. The PMU on Samsung devices serves the role of
syscon, however on GS101 it cannot be used via standard Linux syscon
interface, because register accesses require custom regmap. It was
simply never correctly working with "syscon" compatible fallback.
- Add phandles to System Registers SYSREG blocks in clock controllers,
necessary for enabling automatic clock control later.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmlrzm8QHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD13BJD/4s3Q75bedb7izJ3kvBYTE4Rj1WnfDokx0u
E8STJ5p6FrEB2AKxLSRJTW4/Ih0Bp52G+sBUMetKzUlEznXaJ9c8TdJ9hPRDUYh7
at9R2wpyyWWFOXLIAuNp0nohxUuCiNrJssZZZTsJzV1yFodCG3aPYn38/oNrKVTx
Uhl9zBxTtdGclpPi/npue34oEQRv824AXlu1DSjBbEJfuDYxX5uijcs8T97l2Dtj
rb6Mm2cjTvvU1pTR9sCzGrBxtHP92kl/72w8iSgfvi6OsXqvcHLDdNdhJYvAjdnl
eQNFe0XSFUZDT7pLv+gW/5PEGrO3J6sTKCk5xkic4yQczVr/pqdnxajSGvodOmQu
AQB5EcDwExFGhttiXUEAyG85MVOsLJv+i6sU+2VLQVDOc7+DCMidP0DMgfPh/B/S
dRb0dCTBKWGSnUL1iAnWLVUjxkmnbecA1EcE8/AxG++vn2bXo9t+w1J9LYcwkebU
lrZHj9DjJLvzg6ejBUbwMotzK+c1hYH9WqYGZOcdsw7jPd7ULEaJs1ycO0Oreny4
t8oae9wF85eD4aCZ9KLRnp3l9v2w/cIWzvOLwcqaIsANiVvTy2i3pxLyfkvwgQ2g
+gjms9FTH2IoJ36Y0+RmBklYABOodZiYF+e8eEoioo7xOS6FhMaYQRCcyfMgb9n2
gACUifUGAQ==
=xVlA
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml3fXEACgkQmmx57+YA
GNlNdRAAvxo6wZ1vv1UsVUbGhZ3TmSlYEkYYBo73GMVzkaXRm7HyPA5zo5I+yJRJ
QtH5SPYqgdzfeZGMjnMFGG/IIO4ZB4g7SEWHMFROdz1IIzjTzv5ZBt1rK2tvj7Ok
9gQKWwOnjDPxIcXRHDFcMwAF1WXPvOqTlGbTWBz5PoYcsU6II47ifbLqvautAn24
S74tBfjGukn5kodrtytJOyZt/Vc7NjR6oAXSQ+M7c+Yff4UbHWxRSSHwfGPVFBVB
vdkfg0rY3tzdLs1PUWWgC8T9O/xhILeCnxhnlbgo7u0a+3CnAdQcbfWhmSPPNYzT
+xX/bo6f+FzBPTVeK08QGAvVPH+dHWxk0aktABjS3Hpk6/fOwpCum1oJUECF2SiM
43huYrJZCGLHW12CmEEAKg52rghkqPJkevn+lBXnF5l862/VSeQ/LZUuHIXKK6a1
2xqJqnbzvlHqdjdTrCFC/v9xyQvwJXZt3BH6I8l1oN1ppunZb7jCAlESMGDYjhVZ
NBYsU21eeYCG07+QtvDZ4TSipmtq6RQsvW7fDuvQKSSiNMOOTs6iP5VH0RC48al1
rLUKwiPmYvFSlFBEwt2AIVECtHA73W4MQJgp4s6gwpS2XDYsHTi8NiUx9LbTha7s
kuqrCuwRcY0IQs7dwdDYAggkeQBsYsTWhZi+SGfeHyNlb2y3ur0=
=pNN2
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt64-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM64 changes for v6.20
1. ExynosAutov920:
- Add MFD clock controller node.
2. Google GS101:
- Add True Random Number Generator (TRNG) and OTP nvmem nodes.
- Correct the PMU (Power Management Unit) compatibles by dropping
fallback to syscon. The PMU on Samsung devices serves the role of
syscon, however on GS101 it cannot be used via standard Linux syscon
interface, because register accesses require custom regmap. It was
simply never correctly working with "syscon" compatible fallback.
- Add phandles to System Registers SYSREG blocks in clock controllers,
necessary for enabling automatic clock control later.
* tag 'samsung-dt64-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: gs101: add OTP node
arm64: dts: exynos: gs101: add samsung,sysreg property to CMU nodes
arm64: dts: exynosautov920: add CMU_MFD clock DT nodes
arm64: dts: exynos: gs101: remove syscon compatible from pmu node
dt-bindings: soc: samsung: exynos-pmu: remove syscon for google,gs101-pmu
arm64: dts: exynos: gs101: add TRNG node
dt-bindings: rng: add google,gs101-trng compatible
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Several minor cleanups for Nuvoton, LG, Spreadtrum, Toshiba, Cavium, ARM
and APM SoCs:
1. Switch to recommended node names by fixing style
(s/lowercase/hyphen/), using generic naming and adhering to DT
bindings.
2. Use consistent whitespaces around.
3. Add missing properties like UART clocks (Cavium Thunder 88xx) or
"reg" (APM).
4. Drop incorrect or long time deprecated propeties.
5. Correct clock cells to 0 for fixed-factor-clock clocks.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmlr0roQHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD1wd4D/0UV4Fo/gd/NGbC4iTgQeGKnYfFGsF3Vqsp
TQ92deruSVhN4C1Oudu80LW/Dvtdnemwj/XyLZJ6s2IzZOQ+D0eyJu8IEBHCYelc
+H3IUDq3MsuFaiP+0XXUrH233MOUYCpzxjPlD+JDw5rcp/u24R9Xxl79rWBmU2my
beWtllFRkBY5aaPfDZzApLpVHweXb0jp0/1Syhjw1QB/1fITKj5gwghMCxw9IfWG
N/1Z/C38xeYPZpGGb4f319a55P6mGeUgnt5sM6BFE/jyWBI6sl3wg+ZQG7hRZike
1kkww/c+dqLJV7nT41RKFlez+ET9to2Ll4Di98T4/Agt44Jp13AUWI0f2cnPUoVt
T1vEmLRuCLbUVqGPsVWEoqBw/QFuL/Cg0A33UKxF7Wo6iGKPKq8GhWcnPdUSy8PE
1P03S+UXsiwUpLOUeNfyOXi/Yg9DDFYwpClWruywsJtKk65gU6eJoDJulGDoF9w3
8lKA4lDWdCyuhhOaSkerYzDBQhsEUxhgxUDB+42ZAV+W71iL9ilTOLn3y/POS5a9
469Z1a4bztlAaL2OSzAt3vKT5cBvN+ImuqAa9By0S/l0otJT8lT5Mw2mQmlfCiDa
pjpXp0oWejpCloz8Zw2DGqeQoXKpNpZIiCtm546MzMFJxbqzZ4kW7csvoZHANCSV
LwCbdc3sdg==
=S1JL
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml3fOYACgkQmmx57+YA
GNnjgRAAmCk7jUttCUglZXWOKfXkunrfzkoSxCahG0E2TlENEu1sBJRCKNU0RCKe
y4sFSIDhGJDfZK7CHUDsiC403nCBAjGiKg+6FRnDKj60UgB3/cVmeoI/cR2l6pAU
goTJReQm8bg2FBeFFULQykVwPRtHRVlugmOIPBi0FX1VaOLzgmP8T1AWI3sFWu2g
qdhSByEHr7pzPtoB4C+4c7EsG5JEsVgOqGNOgpZ6wsmAwbqeoiNe2OOyYGP51Aaa
JaAK7C87D2s37I6eQhv2kmLEbij/8IpRiM5booU/l6JA3R7wJNbfWUs3cQ3eDbK9
TmcbtO2K+onPqd0xw1Ds2qByC1FVNv0nC27mmj8u4ldErJeylZrU2Vm1vtEgh9nC
1RGU5eSGwduWmz0dr+lr+wTHos3r8uKLrldZH6aOBNYY+HdhgnyL1r+dqEHx1o9P
Kwe9ADXWVy5UgWXuCCsY6dJ9/aEmBdrU8Wgn5dpwN620ypxgqlDsjCjQ3Yn39E+1
2Fb8/cCjD7BmIP7lgfIyNDOCjoVUBlYQocCVOC5yiDTgeedSFPLHRVtxTQtfCgeD
A18P0WJZy3C9GB6uQeA8cfY8Clh9tGjWs2XkToRw6vSCTEsRwoX40Sm5oL7eOgWw
LJ+ZMMjsyFOoZy77X4xsi7Js/0okDIZ5quVSoCyI7Jr1saoJ4lk=
=91V0
-----END PGP SIGNATURE-----
Merge tag 'dt64-cleanup-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
Minor improvements in ARM64 DTS for v6.20
Several minor cleanups for Nuvoton, LG, Spreadtrum, Toshiba, Cavium, ARM
and APM SoCs:
1. Switch to recommended node names by fixing style
(s/lowercase/hyphen/), using generic naming and adhering to DT
bindings.
2. Use consistent whitespaces around.
3. Add missing properties like UART clocks (Cavium Thunder 88xx) or
"reg" (APM).
4. Drop incorrect or long time deprecated propeties.
5. Correct clock cells to 0 for fixed-factor-clock clocks.
* tag 'dt64-cleanup-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt:
arm64: dts: apm: Drop "dma" device_type
arm64: dts: apm: Add "reg" to "syscon-reboot" and "syscon-poweroff"
arm64: dts: apm: Use recommended i2c node names
arm64: dts: apm/shadowcat: More clock clean-ups
ARM: dts: vexpress/v2m-rs1: Use documented arm,vexpress,config-bus child node names
arm64: dts: cavium: Drop thunder2
arm64: dts: cavium: thunder-88xx: Add missing PL011 "uartclk"
arm64: dts: toshiba: Use recommended node names
arm64: dts: sprd: Use recommended node names
arm64: dts: lg: Use recommended simple-bus node name
arm64: dts: nuvoton: npcm845: Minor whitespace cleanup
arm64: dts: toshiba: tmpv7708: Align node names with DT bindings
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add all required nodes and connections for USB3 support. This is
responsible for the majority of the diffstat. The dt-bindings for the
Type-C PHY are scheduled to be sent via the PHY tree and are already
in next.
- Add RTC subnodes to the System Management Controller
- Add chassis-type property for all M1 and M2 machines
- Fix some minor power management issues
- Add backlight nodes for the A9X-based iPad Pro
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQS3vz815OHsEaWy0u9EEX0kKnUe6QUCaW00EwAKCRBEEX0kKnUe
6TpmAQCCOAuFxlDbDqBsXjC5TcgkLsNc7m5IDrTjEJnS1HAQSQD/Y6S/KIoazQ8T
HM+Oo2E95xF+4Fv4JZOiQnaJ9u5l4wc=
=mYZM
-----END PGP SIGNATURE-----
Merge tag 'apple-soc-dt-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into soc/dt
Apple SoC DT update for 6.20
- Add all required nodes and connections for USB3 support. This is
responsible for the majority of the diffstat. The dt-bindings for the
Type-C PHY are scheduled to be sent via the PHY tree and are already
in next.
- Add RTC subnodes to the System Management Controller
- Add chassis-type property for all M1 and M2 machines
- Fix some minor power management issues
- Add backlight nodes for the A9X-based iPad Pro
* tag 'apple-soc-dt-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux:
arm64: dts: apple: t60xx: Add nodes for integrated USB Type-C ports
arm64: dts: apple: t8112: Add nodes for integrated USB Type-C ports
arm64: dts: apple: t8103: Add nodes for integrated USB Type-C ports
arm64: dts: apple: t8103: Add ps_pmp dependency to ps_gfx
arm64: dts: apple: t8103: Mark ATC USB AON domains as always-on
arm64: dts: apple: t8112-j473: Keep the HDMI port powered on
arm64: dts: apple: Add chassis-type property for Apple iMacs
arm64: dts: apple: Add chassis-type property for Mac Pro
arm64: dts: apple: Add chassis-type property for Apple desktop devices
arm64: dts: apple: Add chassis-type property for all Macbooks
arm64: dts: apple: s8001: Add DWI backlight for J98a, J99a
arm64: dts: apple: t8103,t60xx,t8112: Add SMC RTC node
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This pull request contains device tree changes for ARM NXP LPC32xx intended
for v6.20, please pull the following:
- Frank fixes device tree checker warnings reported for NXP LPC32xx boards,
- Piotr addes a DMA mux block under SCB, DMA properties to controllers and
I2S support for NXP LPC32xx,
- Kuldeep corrects values of PrimeCell PL022 'clocks' and 'clock-names'
properties, this is the change from a waiting queue, recently it was
repeatedly done by Frank, the hesitation was about a probable ABI break,
but here in particular the risk is practically negligible due to the kept
backwards compatibale 'clocks' property,
- Vladimir adds a few missing properties to a number of LPC32xx controllers.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEETKMJMWSwX7CFTVIOqj3i2jwlOWUFAmlqNe4ACgkQqj3i2jwl
OWXGGhAAwwSUolb765U8VYsV/N7piJtzFxgx+9tOOovQzHOck3BgrPNBw5KR4137
KTTCuwLyzrDxvb5xI7QJRXNhv069xktjOO1OLbEQ3Y8SSepJZPsbgdTY+MJSkrQ4
NJNZA1aqoNtO8urPH8GdgNh5lieTGAdU+fafFqc509WUnq0Tm/JvPnpvg/HRSs9q
Eya/Z+Ffjn74CSwB/Ulu9GLD80botZcy6hfrMscAocLtxbP91Hj15ig+0fpJpQwh
ercGvEXAhxEC0tyGmsoTPIHLWMtiJlbJ/KNPzdytbzlhYEIa6ShzpF76CvQhQXNV
sZmEub/bQIogQFbNpUhWBu7PgzwyYwz3j1pcNlMBP9WesuN3Jp15APDaknobsE+Z
lgO8SSi4lR8cMEw2aCMms44l6Xz7GX0DCDsn/aLxDqetQyBtyCJZ8caK2vw74QcP
wnkS57FXfr20fFeYmYp44vIzdVj41q11CRxf/7/THhhjjEMDFh29pO2CWP/XthBA
IQGKoSaTNvdz/lfOQIcK3VwBrktEIrq0REz5939t9Hu7jGVxPTvCwWnBdiqyYp0f
vWiZySfnMsw9oZg7tsu+OhM6UrDulyb4YiH2Cq6cXBAkhupJUuznQRSaI1c9eX34
VFGWFgPyR73eF48W/Rtc0d7mJT6wnA9VSUar6BBKBOfU1SDP4HQ=
=EP7J
-----END PGP SIGNATURE-----
Merge tag 'lpc32xx-dt-for-6.20' of https://github.com/vzapolskiy/linux-lpc32xx into soc/dt
ARM: nxp: lpc: device tree updates for v6.20
This pull request contains device tree changes for ARM NXP LPC32xx intended
for v6.20, please pull the following:
- Frank fixes device tree checker warnings reported for NXP LPC32xx boards,
- Piotr addes a DMA mux block under SCB, DMA properties to controllers and
I2S support for NXP LPC32xx,
- Kuldeep corrects values of PrimeCell PL022 'clocks' and 'clock-names'
properties, this is the change from a waiting queue, recently it was
repeatedly done by Frank, the hesitation was about a probable ABI break,
but here in particular the risk is practically negligible due to the kept
backwards compatibale 'clocks' property,
- Vladimir adds a few missing properties to a number of LPC32xx controllers.
* tag 'lpc32xx-dt-for-6.20' of https://github.com/vzapolskiy/linux-lpc32xx:
arm: dts: lpc32xx: add interrupts property to Motor Control PWM
arm: dts: lpc32xx: add clocks property to Motor Control PWM device tree node
ARM: dts: lpc32xx: Add missing properties to I2S device tree nodes
ARM: dts: lpc32xx: Declare the second AHB master support on PL080 DMA controller
ARM: dts: lpc32xx: Add missing DMA properties
ARM: dts: lpc32xx: Use syscon for system control block
ARM: dts: lpc32xx: describe FLASH_INT of SLC NAND controller
ARM: dts: lpc32xx: change NAND controllers node names
ARM: dts: lpc32xx: Update spi clock properties
ARM: dts: lpc3250-phy3250: replace deprecated at25 properties with new ones
ARM: dts: lpc3250-phy3250: rename nodename at@0 to eeprom@0
ARM: dts: lpc3250-ea3250: add key- prefix for gpio-keys
ARM: dts: lpc32xx: remove usb bus and elevate all children nodes
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
New platforms:
- Facebook Anacapa
The Meta Anacapa BMC is the DC-SCM (Data Center Secure Control
Module) controller for the Meta OCP Open Rack Wide (ORW) compute tray.
This platform is a key component of the AMD Helios AI rack reference
design system, designed for next-generation AI workloads.
The BMC utilizes the Aspeed AST2600 SoC to manage the compute tray, which
contains up to 4 AMD Instinct MI450 Series GPUs (connected via a Broadcom
OCP NIC) and host CPUs. Its primary role is to provide essential system
control, power sequencing, and telemetry reporting for the compute complex
via the OpenBMC software stack.
For more detail on the AMD Helios reference design:
https://www.amd.com/en/blogs/2025/amd-helios-ai-rack-built-on-metas-2025-ocp-design.html
- ASRock Rack ALTRAD8
The ALTRAD8 BMC is an Aspeed AST2500-based BMC for the ASRock Rack
ALTRAD8UD-1L2T and ALTRAD8UD2-1L2Q boards.
Significant changes:
- Switch IBM FSI CFAM nodes to use non-deprecated AT25 properties
Updated platforms:
- bletchley (Facebook): USB-C tweaks
-----BEGIN PGP SIGNATURE-----
iJIEABYKADoWIQSoUT1x3bOSX/nAa8ajM9GZTrjhpgUCaWmZIhwcYW5kcmV3QGNv
ZGVjb25zdHJ1Y3QuY29tLmF1AAoJEKMz0ZlOuOGmugABAN9BnP/6ziUbNz0ds1yx
ZAs79GBfdb5ayvAs5jMy9a0uAP0ZiQoCTIuzeIY6/9MNdf9WdPKAwe+vtiTYmLpR
HtZKDw==
=C694
-----END PGP SIGNATURE-----
Merge tag 'aspeed-6.20-devicetree-1' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
aspeed: second batch of arm devicetree changes for 6.20
New platforms:
- Facebook Anacapa
The Meta Anacapa BMC is the DC-SCM (Data Center Secure Control
Module) controller for the Meta OCP Open Rack Wide (ORW) compute tray.
This platform is a key component of the AMD Helios AI rack reference
design system, designed for next-generation AI workloads.
The BMC utilizes the Aspeed AST2600 SoC to manage the compute tray, which
contains up to 4 AMD Instinct MI450 Series GPUs (connected via a Broadcom
OCP NIC) and host CPUs. Its primary role is to provide essential system
control, power sequencing, and telemetry reporting for the compute complex
via the OpenBMC software stack.
For more detail on the AMD Helios reference design:
https://www.amd.com/en/blogs/2025/amd-helios-ai-rack-built-on-metas-2025-ocp-design.html
- ASRock Rack ALTRAD8
The ALTRAD8 BMC is an Aspeed AST2500-based BMC for the ASRock Rack
ALTRAD8UD-1L2T and ALTRAD8UD2-1L2Q boards.
Significant changes:
- Switch IBM FSI CFAM nodes to use non-deprecated AT25 properties
Updated platforms:
- bletchley (Facebook): USB-C tweaks
* tag 'aspeed-6.20-devicetree-1' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux:
ARM: dts: aspeed: ibm: Use non-deprecated AT25 properties
ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC
dt-bindings: arm: aspeed: add ASRock Rack ALTRAD8 board
ARM: dts: aspeed: bletchley: Remove try-power-role from connectors
ARM: dts: aspeed: Add Facebook Anacapa platform
dt-bindings: arm: aspeed: Add compatible for Facebook Anacapa BMC
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Just the one patch from Rob adding the device_type property to the memory node
of the NPCM845 EVB DTS.
-----BEGIN PGP SIGNATURE-----
iJIEABYKADoWIQSoUT1x3bOSX/nAa8ajM9GZTrjhpgUCaWmTaRwcYW5kcmV3QGNv
ZGVjb25zdHJ1Y3QuY29tLmF1AAoJEKMz0ZlOuOGmwhoBALNO5prUzEg8jIylyKug
5bD3y3ngdi/qK4dgHbhqIt21AQC0qfbyPn04OYp7w1cKaYW/sDnm30IVuEcPDh2F
ZCCPDA==
=OGn7
-----END PGP SIGNATURE-----
Merge tag 'nuvoton-arm64-6.20-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
Nuvoton arm64 devicetree changes for 6.20
Just the one patch from Rob adding the device_type property to the memory node
of the NPCM845 EVB DTS.
* tag 'nuvoton-arm64-6.20-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux:
arm64: dts: nuvoton: Add missing "device_type" property on memory node
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
PCIe-slot-overlay for rk3576-evb1
New peripherals: some of the video decoders on rk3576 and rk3588
Enabled peripherals: many RK3588-NPUs and a lot of other peripherals on
a plethora of boards.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmlmS34QHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgXr8B/4/WyFL/k6cg2ekp5kK1FRJwVNV6LlpfsyL
CM2nZxmt9Vg3VNlJK64aVJVA5724EBgHYk7ZYy+syPiisyPQAl9HX3J/oj6ijp3s
o4PxbqX12mtb+lMTHL9B3zRASsKkKKaQ5dJIXNjxmx0RxGWNsg1EnQmhoys7SLkf
+cKqbK6dbMvEc6d+NVUvhn4RWcENsRUxquMQKV3Ydk7CsI+PA2nHX4lZipowdUd5
UFXtFGISK+0mxUYtqbtO4r4ax01p1RRSCOZIB8xKm/kR5QQOHymKCYOHTZPyPIjL
Im+y+VnZy2b5OlVQNyjG7AFXZLPLThxxcIKIt/4zVuclKEpZlMl2
=bSiM
-----END PGP SIGNATURE-----
Merge tag 'v6.20-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
New boards: Orange Pi CM5 module + Baseboard, Radxa CM5 module + IO-board.
PCIe-slot-overlay for rk3576-evb1
New peripherals: some of the video decoders on rk3576 and rk3588
Enabled peripherals: many RK3588-NPUs and a lot of other peripherals on
a plethora of boards.
* tag 'v6.20-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (40 commits)
arm64: dts: rockchip: Add the vdpu383 Video Decoder on rk3576
arm64: dts: rockchip: Add the vdpu381 Video Decoders on RK3588
arm64: dts: rockchip: Add rk3588s-orangepi-cm5-base device tree
dt-bindings: arm: rockchip: Add Orange Pi CM5 Base
arm64: dts: rockchip: Enable second HDMI output on CM3588
arm64: dts: rockchip: Add HDMI to Gameforce Ace
arm64: dts: rockchip: Enable analog sound on RK3576 EVB1
arm64: dts: rockchip: Enable HDMI sound on RK3576 EVB1
arm64: dts: rockchip: Enable HDMI sound on Luckfox Core3576
arm64: dts: rockchip: Enable HDMI sound on FriendlyElec NanoPi M5
arm64: dts: rockchip: Use a readable audio card name on NanoPi M5
arm64: dts: rockchip: enable NPU on rk3588-jaguar
arm64: dts: rockchip: enable NPU on rk3588-tiger
dt-bindings: arm: rockchip: fix description for Radxa CM5
dt-bindings: arm: rockchip: fix description for Radxa CM3I
arm64: dts: rockchip: Add missing everest,es8388 supplies to rk3399-roc-pc-plus
arm64: dts: rockchip: Enable PCIe for ArmSoM Sige1
arm64: dts: rockchip: Enable the NPU on Turing RK1
arm64: dts: rockchip: Enable the NPU on FriendlyElec CM3588
arm64: dts: rockchip: Enable the NPU on NanoPC T6/T6-LTS
...
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This contains a small set of DT updates:
1. Align DTS node naming with established coding style by replacing underscores
with hyphens in node names. This is a safe change and does not affect ABI.
2. Add support for the CMN PMU on the Arm Morello platform, exposing the
CMN-Skeena (CMN-600 r3p1–compatible) PMU via the standard CMN-600 binding.
This enables PMU access on real Morello SDP hardware, where the registers
are functional.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAmlk2qwACgkQAEG6vDF+
4piEVA//Tli5yzCXuD+B1G63lZrPR0GuoCcpfXrsGM0yxtD3MEOddbzhO1xdkDKm
ZcEygj/xqW5iCCLM8gRMTjr1ZdyWOd6i8dIl+UPqKJ0UypA1b9zu0RC+LKdFLxLK
7SYiWA8he6zWJUKC1FgAmRPh9o+cFoWTnlyF/0wv4dLTtl2G+l6/Hc0r2vy4KBZj
YLDKorx4yc6T3/BYn6zDhy7CaCyJOIrp0tG6KRi6seCqZcwhfPgbiIWO7uZOUVZx
Qu68ohxW/+49OpPntmgCUMC0C2dFBPtJKsh911XJIseN7Z2MY0z7VOM4ruC+DS2t
1JAUHgHo0qFc/yS+y2ioEumShbjb2xMA9RFZ0/vdzEremC9sazQhS58Prb91nlKP
KtnPQcNEbzG/QgK7Vzyw1Kt2MCwLIsYlb/zaAN3YnnQ5a9p1CifVJXpDei4j0a7K
qPyDL2vPYheCio5BXWDt86yj0XXPArisdraCbwnjy5UifuHj5th1//UHjASGszxR
C0D6JGyQqkGBXNNh4b/fpxhcp68MZbDHAWJaGcGh75Arh0v1kE1+U19q7t2/3LRi
ZeRIT0lsgFYEccKifvJsYfLyfleKxq8O54P4ZgXe5ujq1GV+8YzP6wLDd9J8RRD+
yEx1nNEFpmEtHjTaM52e/SMxU8WTnrhZ9/Plj85c9JpXJXB7TvI=
=OCA/
-----END PGP SIGNATURE-----
Merge tag 'juno-updates-7.0' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt
Armv8 Juno/Vexpress updates for v7.0
This contains a small set of DT updates:
1. Align DTS node naming with established coding style by replacing underscores
with hyphens in node names. This is a safe change and does not affect ABI.
2. Add support for the CMN PMU on the Arm Morello platform, exposing the
CMN-Skeena (CMN-600 r3p1–compatible) PMU via the standard CMN-600 binding.
This enables PMU access on real Morello SDP hardware, where the registers
are functional.
* tag 'juno-updates-7.0' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: arm: Use hyphen in node names
arm64: dts: morello: Add CMN PMU
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Due to historical reasons all msm8974 boards have used the CX power rail
as regulator instead of going through the power domain framework.
Since rpmpd has gained msm8974 support quite a bit ago, let's start
using it and replace all usages of pm8841_s2 (CX), pm8841_s4 (GFX) and
for the boards using pma8084 pma8084_s2 (CX), pma8084_s7 (GFX).
For reference, downstream is using GFX power rail as parent-supply for
mmcc's OXILI_GDSC GDSC which then is used for GPU, but nothing there is
modelled upstream.
Signed-off-by: Luca Weiss <luca@lucaweiss.eu>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250621-msm8974-rpmpd-switch-v1-4-0a2cb303c446@lucaweiss.eu
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Before adding more headers in a random order, let's sort the includes
once so that's done.
Signed-off-by: Luca Weiss <luca@lucaweiss.eu>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250621-msm8974-rpmpd-switch-v1-3-0a2cb303c446@lucaweiss.eu
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Introduce a new DT compatible string for the NXP i.MX95 15x15 FRDM
development board, a compact and cost-effective platform based on
the i.MX95 applications processor.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Signed-off-by: Lei Xu <lei.xu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Wire up the TPS65185 regulator needed for the display.
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Kobo Aura (N514) includes a TPS65185 PMIC for the epaper display.
Add description for this pmic and its vin power-supply.
Signed-off-by: Josua Mayer <josua.mayer@jm0.eu>
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Wire up the TPS65185 regulator needed for the display.
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Document the Inter-Processor Communication Controller on the Qualcomm
Kaanapali and Glymur Platforms, which will be used to route interrupts
across various subsystems found on the SoC.
Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20251031-knp-ipcc-v3-1-62ffb4168dff@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Document ifm i.MX8MN VHIP4 EvalBoard v1 and v2 reference design binding.
This system exists in two generations, v1 and v2, which share a lot of
commonality. The boards come with either single gigabit ethernet or an
KSZ8794 fast-ethernet switch, boot from eMMC, and offer CAN interfaces
via Microchip MCP25xx SPI CAN controllers, UART, and USB host. The GPU
is not available in the SoC populated on these devices.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Marek Vasut <marex@nabladev.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
ifm is a manufacturer of industrial sensors, control technology and
automation solutions. Document their vendor prefix, which is already
used for ifm,ac14xx and other powerpc devices.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Marek Vasut <marex@nabladev.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add child node nand@0 and move NAND related property under it to align
modern nand-controller.yaml.
Fix below CHECK_DTBS warnings:
arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dtb: nand-controller@1806000 (fsl,imx6q-gpmi-nand): Unevaluated properties are not allowed ('nand-ecc-mode', 'nand-ecc-step-size', 'nand-ecc-strength', 'nand-on-flash-bbt' were unexpected)
from schema $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
Since 2019 year, commit
(212e496935 dt-bindings: mtd: Add YAML schemas for the generic NAND options)
NAND related property is preferred located under nand@<n> even though only
one NAND chip supported.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Update gpmi #size-cells to 0 to fix below CHECK_DTB warnings:
arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dtb: nand-controller@1806000 (fsl,imx6sx-gpmi-nand): #size-cells: 0 was expected
from schema $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add '#address-cells' and '#size-cells' for gpmi-nand to below CHECK_DTBS
warings:
arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dtb: nand-controller@112000 (fsl,imx6q-gpmi-nand): '#address-cells' is a required property
from schema $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Existing Parallel VI interface schema for Tegra20 is fully compatible with
Tegra30; hence, lets reuse it by setting fallback for Tegra30.
Adjust existing VI schema to reflect that Tegra20 VI is compatible with
Tegra30 by setting a fallback for Tegra30. Additionally, switch to using
an enum instead of list of const.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # tegra20, parallel camera
Signed-off-by: Thierry Reding <treding@nvidia.com>
Document MIPI calibration device found in Tegra132. This compatible
already exists in the Linux kernel, I have just documented it to satisfy
warnings.
Each Tegra SoC generation has unique set of registers which should be
configured. They all differ, hence fallback is not suitable here.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # tegra20, parallel camera
Signed-off-by: Thierry Reding <treding@nvidia.com>
The USB2 port on Smaug is configured for OTG operation but lacked the
required 'usb-role-switch' property, leading to a failed probe and a
non-functioning USB port. Add the property along with setting the default
role to host.
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Complete the missing properties in the tegra-udc node and enable it for
Smaug.
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enable both SOR and DPAUX modules allowing the USB-C port to transmit
video in DP altmode. Tested on several monitors with USB-C to HDMI
adapter.
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Signed-off-by: Thierry Reding <treding@nvidia.com>
"arm,armv8" CPU compatible is only for software models and must not be
used in DTS for actual hardware. Replace them with Neoverse V3AE
compatible, based what is written on Wikipedia [1].
Link: https://en.wikipedia.org/wiki/Tegra#Thor [1]
Reported-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Closes: https://lore.kernel.org/all/59ae6b16-7866-413a-a1d2-4a735024c108@oss.qualcomm.com/
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Device nodes are enabled by default and this DTSI file does not include
anything else, thus it is impossible that nodes were disabled before and
need to be re-enabled. Adding redundant status=okay is just confusing
and suggests some other code flow. Verified with dtx_diff.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Device nodes are enabled by default and this DTSI file does not include
anything else, thus it is impossible that nodes were disabled before and
need to be re-enabled. Adding redundant status=okay is just confusing
and suggests some other code flow. Verified with dtx_diff.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Device nodes are enabled by default and this DTSI file does not include
anything else, thus it is impossible that nodes were disabled before and
need to be re-enabled. Adding redundant status=okay is just confusing
and suggests some other code flow. Verified with dtx_diff.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Device nodes are enabled by default and this DTSI file does not include
anything else, thus it is impossible that nodes were disabled before and
need to be re-enabled. Adding redundant status=okay is just confusing
and suggests some other code flow. Verified with dtx_diff.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Command Queue Virtualization (CMDQV) hardware is part of the
SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in
virtualizing the command queue for the SMMU.
Update SMMU compatible strings to use nvidia,tegra264-smmu to enable
CMDQV support. Add device tree nodes for the CMDQV hardware and enable
them on the tegra264-p3834 platform where SMMUs are enabled. Each SMMU
instance is paired with its corresponding CMDQV instance via the
nvidia,cmdqv property.
Acked-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Document CPUSS Control Processor (CPUCP) mailbox controller for Qualcomm
Kaanapali, which is compatible with X1E80100, use fallback to indicate
this.
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20251021-knp-cpufreq-v2-1-95391d66c84e@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Convert NVIDIA Tegra NAND Flash Controller binding to YAML format.
Changes during Conversion:
- Define new properties `power-domains` and `operating-points-v2`
because the existing in tree DTS uses them.
- Modify MAINTAINERS references to point the created YAML file.
Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
- Update ADMA device tree bindings for tegra264 to support up to 64
interrupt channels by setting 'interrupts' property maxItems to 64.
- Also, update the 'allOf' conditional schema to ensure correct maxItems
for 'interrupts' based on compatible string, including tegra210 (22)
and tegra186 (32) ADMA controllers.
Signed-off-by: sheetal <sheetal@nvidia.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>