stmmac_bus_clks_config() is only used by stmmac_platform.c, so rather
than having it in stmmac_main.c and needing to export the symbol,
move it to where it's used.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Link: https://patch.msgid.link/E1v119j-0000000773s-1R2v@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Document the I2C controllers found in the MediaTek MT6878 SoC, by adding
a new compatible string for the controllers. Their design is compatible
with the design from the MediaTek MT8188 SoC.
Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250920-mt6878-i2c-bringup-v2-1-70a951f10be9@mentallysanemainliners.org
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Samsung S3C2410 SoC was removed from the Linux kernel in the
commit 61b7f8920b ("ARM: s3c: remove all s3c24xx support"), in January
2023. There are no in-kernel users of "samsung,s3c2410-i2c" compatible.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Andi Shyti <andi.shyti@kernel.org>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20250830103601.82046-4-krzysztof.kozlowski@linaro.org
Samsung S3C2410 SoC was removed from the Linux kernel in the
commit 61b7f8920b ("ARM: s3c: remove all s3c24xx support"), in January
2023. There are no in-kernel users of "samsung,s3c2410-i2c" compatible.
However, there is still a user of "s3c2410-i2c" platform device ID,
S3C64xx platform, so that part needs to stay.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Andi Shyti <andi.shyti@kernel.org>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20250830103601.82046-3-krzysztof.kozlowski@linaro.org
The LIBIE_AQ_STR macro() introduced by commit 5feaa7a07b ("libie: add
adminq helper for converting err to str") is used in order to generate
strings for printing human readable error codes. Its definition is missing
the separating underscore ('_') character which makes the resulting strings
difficult to read. Additionally, the string won't match the source code,
preventing search tools from working properly.
Add the missing underscore character, fixing the error string names.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Fixes: 5feaa7a07b ("libie: add adminq helper for converting err to str")
Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Link: https://patch.msgid.link/20250923205657.846759-1-anthony.l.nguyen@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
pbus_size_mem() logs the bridge window resource using pci_info() before the
start and end fields of the resource have been updated which then prints
stale information.
Set resource addresses earlier to make understanding logs easier.
Regrettably, this results in setting the addresses multiple times but that
seems unavoidable.
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20250924135641.3399-1-ilpo.jarvinen@linux.intel.com
Currently, HFS/HFS+ has very obsolete and inconvenient
debug output subsystem. Also, the code is duplicated
in HFS and HFS+ driver. This patch introduces
linux/hfs_common.h for gathering common declarations,
inline functions, and common short methods. Currently,
this file contains only hfs_dbg() function that
employs pr_debug() with the goal to print a debug-level
messages conditionally.
So, now, it is possible to enable the debug output
by means of:
echo 'file extent.c +p' > /proc/dynamic_debug/control
echo 'func hfsplus_evict_inode +p' > /proc/dynamic_debug/control
And debug output looks like this:
hfs: pid 5831:fs/hfs/catalog.c:228 hfs_cat_delete(): delete_cat: 00,48
hfs: pid 5831:fs/hfs/extent.c:484 hfs_file_truncate(): truncate: 48, 409600 -> 0
hfs: pid 5831:fs/hfs/extent.c:212 hfs_dump_extent():
hfs: pid 5831:fs/hfs/extent.c:214 hfs_dump_extent(): 78:4
hfs: pid 5831:fs/hfs/extent.c:214 hfs_dump_extent(): 0:0
hfs: pid 5831:fs/hfs/extent.c:214 hfs_dump_extent(): 0:0
v4
Debug messages have been reworked and information about
new HFS/HFS+ shared declarations file has been added
to MAINTAINERS file.
v5
Yangtao Li suggested to clean up debug output and
fix several typos.
Signed-off-by: Viacheslav Dubeyko <slava@dubeyko.com>
cc: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
cc: Yangtao Li <frank.li@vivo.com>
cc: linux-fsdevel@vger.kernel.org
cc: Johannes Thumshirn <Johannes.Thumshirn@wdc.com>
Signed-off-by: Viacheslav Dubeyko <slava@dubeyko.com>
"difference" is a noun, so "sufficient" is an adjective without "ly".
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250923-dt-net-typo-v1-1-08e1bdd14c74@posteo.net
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Remove unused flexible-array member in struct tls_rec and, with this,
fix the following warning:
net/tls/tls.h:131:29: warning: structure containing a flexible array member is not at the end of another structure [-Wflex-array-member-not-at-end]
Also, add a comment to prevent people from adding any members
after struct aead_request, which is a flexible structure --this is
a structure that ends in a flexible-array member.
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Reviewed-by: Sabrina Dubroca <sd@queasysnail.net>
Link: https://patch.msgid.link/aNMG1lyXw4XEAVaE@kspp
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Fix incorrect size parameter passed to cpuidle_state_write_file() in
cpuidle_state_disable().
The function was incorrectly using sizeof(disable) which returns the
size of the unsigned int variable (4 bytes) instead of the actual
length of the string stored in the 'value' buffer.
Since 'value' is populated with snprintf() to contain the string
representation of the disable value, we should use the length
returned by snprintf() to get the correct string length for
writing to the sysfs file.
This ensures the correct number of bytes is written to the cpuidle
state disable file in sysfs.
Link: https://lore.kernel.org/r/20250917050820.1785377-1-kaushlendra.kumar@intel.com
Signed-off-by: Kaushlendra Kumar <kaushlendra.kumar@intel.com>
Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
The RPMI based mailbox controller drivers and mailbox clients need to
share defines related to RPMI messages over mailbox interface so add
a common header for this purpose.
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Co-developed-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Link: https://lore.kernel.org/r/20250818040920.272664-5-apatel@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Add defines for the new SBI message proxy extension which is part
of the SBI v3.0 specification.
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Co-developed-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Link: https://lore.kernel.org/r/20250818040920.272664-4-apatel@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Commit 1b34cbbf4f ("crypto: af_alg - Disallow concurrent writes in
af_alg_sendmsg") changed some fields from bool to 1-bit bitfields of
type u32.
However, some assignments to these fields, specifically 'more' and
'merge', assign values greater than 1. These relied on C's implicit
conversion to bool, such that zero becomes false and nonzero becomes
true.
With a 1-bit bitfields of type u32 instead, mod 2 of the value is taken
instead, resulting in 0 being assigned in some cases when 1 was intended.
Fix this by restoring the bool type.
Fixes: 1b34cbbf4f ("crypto: af_alg - Disallow concurrent writes in af_alg_sendmsg")
Cc: stable@vger.kernel.org
Signed-off-by: Eric Biggers <ebiggers@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
There are a few minor code fixes for tegra firmware, i.MX firmware and the
eyeq reset controller, and a MAINTAINERS update as Alyssa Rosenzweig moves
on to non-kernel projects. The other changes are all for devicetree files:
- Multiple Marvell Armada SoCs need changes to fix PCIe, audio and SATA
- A socfpga board fails to probe the ethernet phy
- The two temperature sensors on i.MX8MP are swapped
- Allwinner devicetree files cause build-time warnings
- Two Rockchip based boards need corrections for headphone detection
and SPI flash
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjUXWcACgkQmmx57+YA
GNno4g//ZcWBmmkSEHlbbHzD9uMXdXGF/NyNWr/O+9f+uOEnmZ/RCxvNl7rGU8aq
5Mu6QlrgFiPRoDjqU1eHrd+Bya43M6TdOpYf3boM9tgd9wYuE7vLWUUF6BRV/x7D
SuNQfWMk0JwwDgYAltLs5mB+tKqxNnEDLdDQiV28UtES/aNsDAs5Z3pCeBAbbMC/
dkZzg/QvpKEIDBUEA9+24ShYelM5EerQsJJbCJbrM8j5/fJFGWmQ2Z2QPkvVVLIh
8UM6EL0xxa4emDHQJnmgkSbAi5UhPkttiDVl9aRmAfcvxUhGUzrBUu9Gj4ypEdiF
9haGz+qz5rpz0LS5eNzBGPaaiUTRlx6PvCcpuJhkJKHyFjQDj+eruX7LMjsFptlz
My1yS7J2LlDEpQOwIs8cQSnB6pV3eeol7DVM7PewbocbcSP1zgYcu+MYZc3QbJbH
KdG6glkzbBWl5Nhur4KBVpv8HmsV8521WJQiyuH4MmjOUlHVVljsx6JVjvythw78
n8nNHcwNIqpZRL2bYAaDT/uhtvPz3dgIU17Xl/s21Av3Wwru1GqNt/dMgMy6Ent5
+1lriby47DCP69g0joy82Eb3Jf8KkAYatDmUEr31kZA66cVPzmrEGX6QioqGcMs5
3XDF+JuAN3MzqGw4oZfPH5tLzYYUNr8g6F1A4CA5rlSDYiU81Rg=
=bxeQ
-----END PGP SIGNATURE-----
Merge tag 'soc-fixes-6.17-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC fixes from Arnd Bergmann:
"There are a few minor code fixes for tegra firmware, i.MX firmware
and the eyeq reset controller, and a MAINTAINERS update as Alyssa
Rosenzweig moves on to non-kernel projects.
The other changes are all for devicetree files:
- Multiple Marvell Armada SoCs need changes to fix PCIe, audio and
SATA
- A socfpga board fails to probe the ethernet phy
- The two temperature sensors on i.MX8MP are swapped
- Allwinner devicetree files cause build-time warnings
- Two Rockchip based boards need corrections for headphone detection
and SPI flash"
* tag 'soc-fixes-6.17-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
MAINTAINERS: remove Alyssa Rosenzweig
firmware: tegra: Do not warn on missing memory-region property
arm64: dts: marvell: cn9132-clearfog: fix multi-lane pci x2 and x4 ports
arm64: dts: marvell: cn9132-clearfog: disable eMMC high-speed modes
arm64: dts: marvell: cn913x-solidrun: fix sata ports status
ARM: dts: kirkwood: Fix sound DAI cells for OpenRD clients
arm64: dts: imx8mp: Correct thermal sensor index
ARM: imx: Kconfig: Adjust select after renamed config option
firmware: imx: Add stub functions for SCMI CPU API
firmware: imx: Add stub functions for SCMI LMM API
firmware: imx: Add stub functions for SCMI MISC API
riscv: dts: allwinner: rename devterm i2c-gpio node to comply with binding
arm64: dts: rockchip: Fix the headphone detection on the orangepi 5
arm64: dts: rockchip: Add vcc supply for SPI Flash on NanoPC-T6
ARM: dts: socfpga: sodia: Fix mdio bus probe and PHY address
reset: eyeq: fix OF node leak
ARM64: dts: mcbin: fix SATA ports on Macchiatobin
ARM: dts: armada-370-db: Fix stereo audio input routing on Armada 370
ARM: dts: allwinner: Minor whitespace cleanup
The kernel's CFI implementation uses the KCFI ABI specifically, and is
not strictly tied to a particular compiler. In preparation for GCC
supporting KCFI, rename CONFIG_CFI_CLANG to CONFIG_CFI (along with
associated options).
Use new "transitional" Kconfig option for old CONFIG_CFI_CLANG that will
enable CONFIG_CFI during olddefconfig.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Nathan Chancellor <nathan@kernel.org>
Link: https://lore.kernel.org/r/20250923213422.1105654-3-kees@kernel.org
Signed-off-by: Kees Cook <kees@kernel.org>
Enable the MMP_PDMA driver as a module in defconfig builds, where it is
needed by Spacemit K1 boards. This depends on a savedefconfig reorder
that it'd otherwise conflict with, so that's here too.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCaNQtyAAKCRB4tDGHoIJi
0nBWAQDnUUFKpinWzj/Z+I2EQddkEg+8rGLY2auIDicuCm7juAEAhZN63IND1U3S
R/+q/Dad4fe6bJh5AFjWq9bAQYNzAAk=
=ag/8
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjUYiEACgkQmmx57+YA
GNn3HA/+NBi9RoDDCpRvcjqLQRL/C7HfBdieuJHhqaxz/SWXgw3/3z031Zz1npTl
NRSFUSsTnjA8vvVS62xYwII4kVve+XpXbHkjqDPu0GlfCeKvkEMJNF9AL3GTFiZg
qzO7heRjMekv9jXZsbTWwVsTKWLgutU1ma2Xv5sG+Jj2Uy7NfoaXr4zKB+rT5oHi
rYiqPW6ByebyGI328Z0oA8Pc6w52AWSmoFvdpgbdlXeWLRuEHeD9oOtoqSB2HJku
1Ae0CAvx12/zkFC/vYZ8v/xuecxjq6s6SkKow80BAniDxSGmLCL6mfDwLlHHdmN0
1U1jVphiHchU0dELNo47KCYDONfMKCyQ4agQ0cuS5VQqwg6nfh/984MaS7+KENA2
B2Qq5Z4aUzUoUNMTVuyz2blcTLzNzSqZDoZFZO2hb2jnqXDVLEgWy130vTI3VAYH
Fe1e8EzFfz8oYWdVNJoQSwoJ7QK6JoiNbqKb9FMozB0pYZYIWCdOts1YxrvtDw1u
AszyTTrSoc76SodRXYX1PzqWdAXjm0inZrv69MNbphBCe7MavQJYh997Nni++w8u
T3sB6jLBFdVg30RTBblEaY/P3BcTwRCKmVMoS7eCyUoTkUgcizlJ18R27Z5ZMcnX
epWoFY+4R6o1bzcqeBpwNPzDSYt1fke3uWoHIlYW+RlawLh6hdk=
=Raip
-----END PGP SIGNATURE-----
Merge tag 'riscv-config-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/defconfig
RISC-V config for v6.18
Enable the MMP_PDMA driver as a module in defconfig builds, where it is
needed by Spacemit K1 boards. This depends on a savedefconfig reorder
that it'd otherwise conflict with, so that's here too.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-config-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: defconfig: Enable MMP_PDMA support for SpacemiT K1 SoC
riscv: defconfig: run savedefconfig to reorder it
Link: https://lore.kernel.org/r/20250924-unenvied-armful-5fcc80c23d19@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Starfive:
The main new addition is support for the JH7110 Milk-V Mars CM lite SoM.
Other than that, there's several cleanups done to the common JH7110 dtsi
file, some relating to properties used by U-Boot or encountered during
U-Boot development. Additionally, there's a binding and devicetree node
for the memory controller on the JH7110. The memory controller only sees
use in U-Boot, so the binding is here rather than in Krzysztof's
branch.
SiFive:
Support for SiFive vendor-specific extensions in the binding file for
extensions. These currently only see use in the SBI implementation.
Microchip:
Addition of support for the PolarFire SoC Discovery kit and
non-engineering sample Icicle kit. The latter differs very slightly from
the final ES devices due to bug fixes affecting functionality, and needs
its own dts. To reduce duplication, the common portion of the two Icicle
kits are moved into a dtsi. There's a few minor fixes here too, mostly
low-hanging fruit detected during the addition of the Discovery kit that
were then applied to the Icicle.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCaNQsNwAKCRB4tDGHoIJi
0tRJAQCOiusij3bReKGIWj0IwCJqPWzopPM7SksV68FXFaM/dAD+OJIKn/WmLHjN
luAnAUeUslgubmKuDNIQimrQm1OsSQ8=
=V7Gc
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjUYZ4ACgkQmmx57+YA
GNk2ABAAiA1kE871avv5q6kCo5ubiNl1yJFds/P++fu2pDDL+tEW5yUciYjTvWLi
N8GXov77FkxDtvcfp+8XRtzZpcfutaIIcaC24dNFoGxoUONuqR8ZDZ1BH3Nd7M8M
jro3iKWscj91hhtLWQK4HeW/7cDtVvW732Z+d+vfYsAecdIL7PPL/4aJ3LOm9+Lw
icQjfhCoH9qiyih6GO6/aMJW9aFi7gB46j7ggInUUlIo8CEM+3V3of5jS7/wRMPM
PZoES3N+w1tSqXYrVz+jr3ErEYmeYC0AvPgcV9/TcAgpgCjYbvTUlC+IL5EEupMW
kOTkEjG1UsgmUwBskI/zH9xxlv5vjk6mRIWlHkQ24T/LwdVz4YDYfmRWcS8sVokf
3ZeOoPjnGZ+ANGz1rgbitcffydnDX/xJSMkGkCZFP/BjEXQtCXhNnXm9ECZ0lFuU
NLn8leOnCB5VWrRm/ExSJIB6FTjm5OWwHIC2zs/9O+RvRVO54DTRwlaiqKybSE/E
dV0GGgbvqtS3cMEzpiFh3zDCEZ1ivpTsIyuGj4wBW41/GdeXLTjNNEqPBtmtr8VX
4kAuLEK/DKEe6/JL/E0TQai0SPky2TtXfCCX9eALShu0uDAx21WFyjacnbRuIhXY
V2UDs64/fkg3evp5rvSNDkFTsXj6NnvXFIrYLoAzOqzGVYHqf8g=
=mB9N
-----END PGP SIGNATURE-----
Merge tag 'riscv-dt-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
RISC-V Misc Devicetrees for v6.18
Starfive:
The main new addition is support for the JH7110 Milk-V Mars CM lite SoM.
Other than that, there's several cleanups done to the common JH7110 dtsi
file, some relating to properties used by U-Boot or encountered during
U-Boot development. Additionally, there's a binding and devicetree node
for the memory controller on the JH7110. The memory controller only sees
use in U-Boot, so the binding is here rather than in Krzysztof's
branch.
SiFive:
Support for SiFive vendor-specific extensions in the binding file for
extensions. These currently only see use in the SBI implementation.
Microchip:
Addition of support for the PolarFire SoC Discovery kit and
non-engineering sample Icicle kit. The latter differs very slightly from
the final ES devices due to bug fixes affecting functionality, and needs
its own dts. To reduce duplication, the common portion of the two Icicle
kits are moved into a dtsi. There's a few minor fixes here too, mostly
low-hanging fruit detected during the addition of the Discovery kit that
were then applied to the Icicle.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-dt-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: dts: starfive: add Milk-V Mars CM Lite system-on-module
dt-bindings: riscv: starfive: add milkv,marscm-lite
riscv: dts: starfive: add Milk-V Mars CM system-on-module
dt-bindings: riscv: starfive: add milkv,marscm-emmc
riscv: dts: starfive: add common board dtsi for Milk-V Mars CM variants
riscv: dts: microchip: add a device tree for Discovery Kit
dt-bindings: riscv: microchip: document Discovery Kit
riscv: dts: microchip: rename icicle kit ccc clock and other minor fixes
riscv: dts: microchip: add icicle kit with production device
dt-bindings: riscv: microchip: document icicle kit with production device
riscv: dts: microchip: add common board dtsi for icicle kit variants
riscv: dts: starfive: jh7110-common: drop mmc post-power-on-delay-ms
riscv: dts: starfive: jh7110-common: drop no-mmc property from mmc1
riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader
riscv: dts: starfive: jh7110: add DMC memory controller
dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC
riscv: dts: starfive: jh7110-common: drop no-sdio property from mmc1
riscv: dts: microchip: Minor whitespace cleanup
dt-bindings: riscv: Add SiFive vendor extensions description
Link: https://lore.kernel.org/r/20250924-frighten-magazine-ee2f16e64638@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
During kernel option migrations (e.g. CONFIG_CFI_CLANG to CONFIG_CFI),
existing .config files need to maintain backward compatibility while
preventing deprecated options from appearing in newly generated
configurations. This is challenging with existing Kconfig mechanisms
because:
1. Simply removing old options breaks existing .config files.
2. Manually listing an option as "deprecated" leaves it needlessly
visible and still writes them to new .config files.
3. Using any method to remove visibility (.e.g no 'prompt', 'if n',
etc) prevents the option from being processed at all.
Add a "transitional" attribute that creates symbols which are:
- Processed during configuration (can influence other symbols' defaults)
- Hidden from user menus (no prompts appear)
- Omitted from newly written .config files (gets migrated)
- Restricted to only having help sections (no defaults, selects, etc)
making it truly just a "prior value pass-through" option.
The transitional syntax requires a type argument and prevents type
redefinition:
config NEW_OPTION
bool "New option"
default OLD_OPTION
config OLD_OPTION
bool
transitional
help
Transitional config for OLD_OPTION migration.
This allows seamless migration: olddefconfig processes existing
CONFIG_OLD_OPTION=y settings to enable CONFIG_NEW_OPTION=y, while
CONFIG_OLD_OPTION is omitted from newly generated .config files.
Added positive and negative testing via "testconfig" make target.
Co-developed-by: Vegard Nossum <vegard.nossum@oracle.com>
Signed-off-by: Vegard Nossum <vegard.nossum@oracle.com>
Reviewed-by: Nathan Chancellor <nathan@kernel.org>
Tested-by: Nathan Chancellor <nathan@kernel.org>
Link: https://lore.kernel.org/r/20250923213422.1105654-2-kees@kernel.org
Signed-off-by: Kees Cook <kees@kernel.org>
The kconfig test harness ("make testconfig") was generating BrokenPipeError
warnings when running interactive tests like oldaskconfig and oldconfig:
/usr/lib/python3/dist-packages/_pytest/unraisableexception.py:85: PytestUnraisableExceptionWarning: Exception ignored in: <_io.BufferedWriter name=12>
Traceback (most recent call last):
File "/srv/code/scripts/kconfig/tests/conftest.py", line 127, in oldaskconfig
return self._run_conf('--oldaskconfig', dot_config=dot_config,
~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
interactive=True, in_keys=in_keys)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
BrokenPipeError: [Errno 32] Broken pipe
The issue occurred when the test framework attempted to write to stdin
after the conf subprocess had already exited.
Wrap stdin write operations in try/except to catch BrokenPipeError and
stop sending more input. Add explicit flush() after writes so we can see
delivery errors immediately. Ignore BrokenPipeError when closing stdin.
Explicitly call wait() to validate subprocess termination.
Reviewed-by: Nathan Chancellor <nathan@kernel.org>
Tested-by: Nathan Chancellor <nathan@kernel.org>
Link: https://lore.kernel.org/r/20250923213422.1105654-1-kees@kernel.org
Signed-off-by: Kees Cook <kees@kernel.org>
Set the glitch threshold by DTS property and keep the existing default
behavior if the 'debounce-delay-us' is not present.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20250923143746.2857292-7-dario.binacchi@amarulasolutions.com
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Support the debounce-delay-us property.
Drivers must convert this value to IPG clock cycles and map it to one of
the four discrete thresholds exposed by the TSC_DEBUG_MODE2 register:
0: 8191 IPG cycles
1: 4095 IPG cycles
2: 2047 IPG cycles
3: 1023 IPG cycles
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250923143746.2857292-5-dario.binacchi@amarulasolutions.com
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Add support for glitch delay configuration. A detected signal is valid
only if it remains stable longer than the configured delay; otherwise,
it is considered a glitch.
This property was introduced for the i.MX6UL touchscreen controller (TSC),
which provides a hardware deglitch filter with four thresholds depending
on the IPG clock frequency. In this use case, the IPG clock rate is 66 MHz,
resulting in thresholds of 124 µs, 62 µs, 31 µs, and 15 µs, which requires
a property with microsecond-level resolution.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250923143746.2857292-4-dario.binacchi@amarulasolutions.com
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
sifive:
Reduce the number of fences issued while flushing. Samuel reports that
this is approximately a 15% speed-up.
ax45mp:
Fix the binding so that it permits the cache-sets setting used by the
recently added QiLai SoC.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCaNQvGgAKCRB4tDGHoIJi
0mRQAQCCZsvM+vnC5OasyRbwNzt1WTXdRqXodP81pwvA4PeCswEAlIrvpTN85JX/
AG3mt64AzoVTakFvwjhcP3GHOHS8mw4=
=PX57
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjUX+MACgkQmmx57+YA
GNlrQBAAtbU+0VmnIxzC5jicNRmLVCisny7F11bRPPOdpgxEyq4eXD9ajCur58Om
c/CZyR3+cBRpLfcC+2fKZg9Sw3SzxRU8NRBu3h5ca2M0B94L/UxjzCc4H+2vQOPB
nxMduErLefJGVuHtTntYgjYLQi/GM0ggiUmeLjh1RMSS0+10JWLEXd5lzqOax90N
M+Y4ANXR22IQHmQFfXi+0o7L4VBQNUFslY4Z3owMI4KW/raSMNfVIfSbRds4WbWN
3z7xkg4jWSBWoLvCtDU0exUf4qpn+OmJ3OCDzq1gFSWfIi3iJD6j9AlTnWT7FtqR
o+vouJeMFaKJOOpZrk0/TToc7+O4qJUqUg/Nvi5k4BFEZrExAxu5yERngEsJIoe2
S9UCS0qVphaZLtN10dPfApER2w+u6knavZ6Sw5yoXplmpCHJW4NCzqoEaMHIJJFg
Gqep81ml01caqGtsK/PR/KcE+wBV92Wq1WwzjlBbvzIre/1jJv8orAj/qcEvGOHh
2WgqnAfOPxL993h+DyxTCsbPxRdKaSgOMviy7kE/l5lnaJK9dJMFsS/Ern7HrZHr
7AdUTGA8I61edjuRojn33MLb0cVg14ZHwrwyIK/IMX3MjwnTsyOa2qWNakF3ifI0
Od8coB9Sj1vccBvIQZTrJ23iyobFdsIVdJLfegJU2jnNCMVSPWA=
=It/E
-----END PGP SIGNATURE-----
Merge tag 'riscv-cache-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers
RISC-V cache drivers for v6.18
sifive:
Reduce the number of fences issued while flushing. Samuel reports that
this is approximately a 15% speed-up.
ax45mp:
Fix the binding so that it permits the cache-sets setting used by the
recently added QiLai SoC.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-cache-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
cache: sifive_ccache: Optimize cache flushes
dt-bindings: cache: ax45mp: add 2048 as a supported cache-sets value
Link: https://lore.kernel.org/r/20250924-relenting-aqua-a4a93b89809e@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Use for_each_online_cpu() instead of for_each_cpu() in qbman
- Update FSL QUICC ENGINE GPIO driver to a standard platform driver
and stop using legacy-of-mm-gpiochip.h header
- Misc fixes on bus/fsl-mc
-----BEGIN PGP SIGNATURE-----
iJIEABYKADoWIQQQ/+b4s5DeF6zCYyNoqS/rAbjdeAUCaNQTmBwcY2hyaXN0b3Bo
ZS5sZXJveUBjc2dyb3VwLmV1AAoJEGipL+sBuN14UZABAKSmuSrlq3ErA/76SfYU
vwqpn2OnQAWfb5ttS3teCnpqAQDwSOzhT2wO0EtK5HPnA9zC/iB8FeDLxtMIXFuW
vvcMCA==
=ECnN
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjUX5wACgkQmmx57+YA
GNlecg//TwLQSuZqwgk87L04xWSiWE/OhbMy7h9fuDrlbJNwl2xLyTXvSTq3E6RW
NyPTTz471Y2Z+Vpd2iw6m5DZjMyha7ZziUiNTeTKeXwzaiATuuz1154fmpYD3PH4
T16OL2/KsrkPVZfyM6Ww/si49XuSvbRvd+Oh2QlY2/chkyz+pSRDINcgPDqZTaED
bTRQhvZxx8ujBKJbFAVpO64qx4mpaaoIevX9qh5w5fBxoQywHxyGL25jsPlkzD1y
8akMNZ0H1hPE+vXMTdEIv14xiVavS4Exwv2HwDAruuJhsIC0f9C8rY4YYMXuM6yg
29LHmIGYHEjarS1ajFcEtAgAWtqx05GqbGlelxKfiLzaLSW8od7LE+5Gc0FwUW/4
BcmycStI4eh9piDyQIA2EyeA7OEIcrphJS/+CIQk+IJRBc79WMPaHpuaxCaMR1y6
FAOJCGpaqGja4+FRLClmGWGAlmyKROG0g+P9dUJu8DgIFO7f8rrJtzr1sv0+Oc37
zCBIHwiVlXeHcmWETjEGcOjQI8L9oQ3GBX7TrSGcM4+bXL9De4X8Es2wdPx48gkf
LlNOeW1TcXhHSWcOhhgHHiEFEOE5m5cYn9weDpnWSkX6eBK/jB1nvXNSSJkgOgi+
Vws1/Y4iD72nfTfxtr96sWZZsPQEfSh+WezRoy5WjpEPkvdQPYQ=
=Zmaw
-----END PGP SIGNATURE-----
Merge tag 'soc_fsl-6.18-1' of https://github.com/chleroy/linux into soc/drivers
FSL SOC Changes for 6.18:
- Use for_each_online_cpu() instead of for_each_cpu() in qbman
- Update FSL QUICC ENGINE GPIO driver to a standard platform driver
and stop using legacy-of-mm-gpiochip.h header
- Misc fixes on bus/fsl-mc
* tag 'soc_fsl-6.18-1' of https://github.com/chleroy/linux:
soc/fsl/qbman: Use for_each_online_cpu() instead of for_each_cpu()
soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver
soc: fsl: qe: Change GPIO driver to a proper platform driver
bus: fsl-mc: Replace snprintf and sprintf with sysfs_emit in sysfs show functions
bus: fsl-mc: Check return value of platform_get_resource()
Link: https://lore.kernel.org/r/26615a15-3494-435f-b0c1-861122b4b5e1@csgroup.eu
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
"The data line must be sampled" makes much more sense than what was
previously written, and given that "s" and "d" are neighbors on the
QWERTY keybord, it was probably a typo.
Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
Link: https://lore.kernel.org/r/20250923-ps2-typo-v1-1-03d2468acc32@posteo.net
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
When the module parameter slider_balance is set to the performance
slider value of 0, the SoC slider profile switches to the performance
mode.
This can cause the Linux power-profiles-daemon to change the system
power mode to performance from balanced mode. This happens when there
is only one platform profile registered as there will be no conflict
with other platform profiles.
Same issue occurs when the slider_balance is set to the power-saver
slider value.
Prevent module parameter slider_balance from overlapping with
performance and power-saver slider values by adding range validation.
Return an error when an invalid value is provided.
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Link: https://patch.msgid.link/20250923205631.3056590-1-srinivas.pandruvada@linux.intel.com
[ rjw: Changelog edits ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
The return value from tegra_bpmp_transfer() indicates the success or
failure of the IPC transaction with BPMP. If the transaction succeeded, we
also need to check the actual command's result code.
If we don't have error handling for tegra_bpmp_transfer(), we will set the
pcie->ep_state to EP_STATE_ENABLED even when the tegra_bpmp_transfer()
command fails. Thus, the pcie->ep_state will get out of sync with reality,
and any further PERST# assert + deassert will be a no-op and will not
trigger the hardware initialization sequence.
This is because pex_ep_event_pex_rst_deassert() checks the current
pcie->ep_state, and does nothing if the current state is already
EP_STATE_ENABLED.
Thus, it is important to have error handling for tegra_bpmp_transfer(),
such that the pcie->ep_state can not get out of sync with reality, so that
we will try to initialize the hardware not only during the first PERST#
assert + deassert, but also during any succeeding PERST# assert + deassert.
One example where this fix is needed is when using a rock5b as host.
During the initial PERST# assert + deassert (triggered by the bootloader on
the rock5b) pex_ep_event_pex_rst_deassert() will get called, but for some
unknown reason, the tegra_bpmp_transfer() call to initialize the PHY fails.
Once Linux has been loaded on the rock5b, the PCIe driver will once again
assert + deassert PERST#. However, without tegra_bpmp_transfer() error
handling, this second PERST# assert + deassert will not trigger the
hardware initialization sequence.
With tegra_bpmp_transfer() error handling, the second PERST# assert +
deassert will once again trigger the hardware to be initialized and this
time the tegra_bpmp_transfer() succeeds.
Fixes: c57247f940 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
[cassel: improve commit log]
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20250922140822.519796-8-cassel@kernel.org
Tegra already defines all BARs except BAR0 as BAR_RESERVED. This is
sufficient for pci-epf-test to not allocate backing memory and to not call
set_bar() for those BARs. However, marking a BAR as BAR_RESERVED does not
mean that the BAR gets disabled.
The host side driver, pci_endpoint_test, simply does an ioremap for all
enabled BARs and will run tests against all enabled BARs, so it will run
tests against the BARs marked as BAR_RESERVED.
After running the BAR tests (which will write to all enabled BARs), the
inbound address translation is broken. This is because the tegra controller
exposes the ATU Port Logic Structure in BAR4, so when BAR4 is written, the
inbound address translation settings get overwritten.
To avoid this, implement the dw_pcie_ep_ops .init() callback and start off
by disabling all BARs (pci-epf-test will later enable/configure BARs that
are not defined as BAR_RESERVED).
This matches the behavior of other PCIe endpoint drivers: dra7xx, imx6,
layerscape-ep, artpec6, dw-rockchip, qcom-ep, rcar-gen4, and uniphier-ep.
With this, the PCI endpoint kselftest test case CONSECUTIVE_BAR_TEST (which
was specifically made to detect address translation issues) passes.
Fixes: c57247f940 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20250922140822.519796-7-cassel@kernel.org
The "max_link_width", "current_link_speed", "current_link_width",
"secondary_bus_number", and "subordinate_bus_number" sysfs files all access
config registers, but they don't check the runtime PM state. If the device
is in D3cold or a parent bridge is suspended, we may see -EINVAL, bogus
values, or worse, depending on implementation details.
Wrap these access in pci_config_pm_runtime_{get,put}() like most of the
rest of the similar sysfs attributes.
Notably, "max_link_speed" does not access config registers; it returns a
cached value since d2bd39c045 ("PCI: Store all PCIe Supported Link
Speeds").
Fixes: 56c1af4606 ("PCI: Add sysfs max_link_speed/width, current_link_speed/width, etc")
Signed-off-by: Brian Norris <briannorris@google.com>
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20250924095711.v2.1.Ibb5b6ca1e2c059e04ec53140cd98a44f2684c668@changeid
* kvm-arm64/selftests-6.18:
: .
: KVM/arm64 selftest updates for 6.18:
:
: - Large update to run EL1 selftests at EL2 when possible
: (20250917212044.294760-1-oliver.upton@linux.dev)
:
: - Work around lack of ID_AA64MMFR4_EL1 trapping on CPUs
: without FEAT_FGT
: (20250923173006.467455-1-oliver.upton@linux.dev)
:
: - Additional fixes and cleanups
: (20250920-kvm-arm64-id-aa64isar3-el1-v1-0-1764c1c1c96d@kernel.org)
: .
KVM: arm64: selftests: Cover ID_AA64ISAR3_EL1 in set_id_regs
KVM: arm64: selftests: Remove a duplicate register listing in set_id_regs
KVM: arm64: selftests: Cope with arch silliness in EL2 selftest
KVM: arm64: selftests: Add basic test for running in VHE EL2
KVM: arm64: selftests: Enable EL2 by default
KVM: arm64: selftests: Initialize HCR_EL2
KVM: arm64: selftests: Use the vCPU attr for setting nr of PMU counters
KVM: arm64: selftests: Use hyp timer IRQs when test runs at EL2
KVM: arm64: selftests: Select SMCCC conduit based on current EL
KVM: arm64: selftests: Provide helper for getting default vCPU target
KVM: arm64: selftests: Alias EL1 registers to EL2 counterparts
KVM: arm64: selftests: Create a VGICv3 for 'default' VMs
KVM: arm64: selftests: Add unsanitised helpers for VGICv3 creation
KVM: arm64: selftests: Add helper to check for VGICv3 support
KVM: arm64: selftests: Initialize VGICv3 only once
KVM: arm64: selftests: Provide kvm_arch_vm_post_create() in library code
Signed-off-by: Marc Zyngier <maz@kernel.org>
We have a couple of writable bitfields in ID_AA64ISAR3_EL1 but the
set_id_regs selftest does not cover this register at all, add coverage.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Currently we list the main set of registers with bits we test three
times, once in the test_regs array which is used at runtime, once in the
guest code and once in a list of ARRAY_SIZE() operations we use to tell
kselftest how many tests we plan to execute. This is needlessly fiddly,
when adding new registers as the test_cnt calculation is formatted with
two registers per line. Instead count the number of bitfields in the
register arrays at runtime.
The existing code subtracts ARRAY_SIZE(test_regs) from the number of
tests to account for the terminating FTR_REG_END entries in the per
register arrays, the new code accounts for this when enumerating.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Implementations without FEAT_FGT aren't required to trap the entire ID
register space when HCR_EL2.TID3 is set. This is a terrible idea, as the
hypervisor may need to advertise the absence of a feature to the VM
using a negative value in a signed field, FEAT_E2H0 being a great
example of this.
Cope with uncooperative implementations in the EL2 selftest by accepting
a zero value when FEAT_FGT is absent and otherwise only tolerating the
expected nonzero value.
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Add an embarrassingly simple selftest for sanity checking KVM's VHE EL2
and test that the ID register bits are consistent with HCR_EL2.E2H being
RES1.
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Take advantage of VHE to implicitly promote KVM selftests to run at EL2
with only slight modification. Update the smccc_filter test to account
for this now that the EL2-ness of a VM is visible to tests.
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Initialize HCR_EL2 such that EL2&0 is considered 'InHost', allowing the
use of (mostly) unmodified EL1 selftests at EL2.
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Configuring the number of implemented counters via PMCR_EL0.N was a bad
idea in retrospect as it interacts poorly with nested. Migrate the
selftest to use the vCPU attribute instead of the KVM_SET_ONE_REG
mechanism.
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Arch timer registers are redirected to their hypervisor counterparts
when running in VHE EL2. This is great, except for the fact that the
hypervisor timers use different PPIs. Use the correct INTIDs when that
is the case.
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Marc Zyngier <maz@kernel.org>
HVCs are taken within the VM when EL2 is in use. Ensure tests use the
SMC instruction when running at EL2 to interact with the host.
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Marc Zyngier <maz@kernel.org>
The default vCPU target in KVM selftests is pretty boring in that it
doesn't enable any vCPU features. Expose a helper for getting the
default target to prepare for cramming in more features. Call
KVM_ARM_PREFERRED_TARGET directly from get-reg-list as it needs
fine-grained control over feature flags.
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Reviewed-by: Itaru Kitayama <itaru.kitayama@fujitsu.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
FEAT_VHE has the somewhat nice property of implicitly redirecting EL1
register aliases to their corresponding EL2 representations when E2H=1.
Unfortunately, there's no such abstraction for userspace and EL2
registers are always accessed by their canonical encoding.
Introduce a helper that applies EL2 redirections to sysregs and use
aggressive inlining to catch misuse at compile time. Go a little past
the architectural definition for ease of use for test authors (e.g. the
stack pointer).
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Start creating a VGICv3 by default unless explicitly opted-out by the
test. While having an interrupt controller is nice, the real benefit
here is clearing a hurdle for EL2 VMs which mandate the presence of a
VGIC.
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Marc Zyngier <maz@kernel.org>
vgic_v3_setup() has a good bit of sanity checking internally to ensure
that vCPUs have actually been created and match the dimensioning of the
vgic itself. Spin off an unsanitised setup and initialization helper so
vgic initialization can be wired in around a 'default' VM's vCPU
creation.
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Introduce a proper predicate for probing VGICv3 by performing a 'test'
creation of the device on a dummy VM.
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Marc Zyngier <maz@kernel.org>
vgic_v3_setup() unnecessarily initializes the vgic twice. Keep the
initialization after configuring MMIO frames and get rid of the other.
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
In order to compel the default usage of EL2 in selftests, move
kvm_arch_vm_post_create() to library code and expose an opt-in for using
MTE by default.
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Marc Zyngier <maz@kernel.org>
