Note that the soft reset code for GMC v6-v7 was never
called from anywhere, so there is no loss of functionality
from this commit. The implementation looks plausible but
it was never enabled or tested, and unlikely to be useful.
We should only reset the memory controller during ASIC reset
and otherwise leave it alone. Resetting the memory controller
can break everything and risks losing the contents of VRAM
(it's unclear if VRAM is lost or not, but it's likely).
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Use gfx_supported_reset's PER_PIPE bit to report GFX pipe reset support
through a shared helper.
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
DMs still call dc_hardware_init and dc_hardware_release while Core 2
lands next to legacy. Those entry points live in dc/dc_api_dispatch:
LEGACY calls the old bodies directly, CORE2 uses core2_funcs. dc_create
allocates struct dc2 and returns the inner dc (TO_DC2). The shim only
records selection; dc_construct still constructs Core2. No dispatch
fields on public struct dc, and no architect spec edits.
TO_DC2 is a typed upcast (struct dc is the first member of struct dc2).
Shim headers are included for UNIT_TEST as well as production so TO_DC2
is defined when core_gtest compiles dc.c.
Assisted-by: Cursor:cursor
Signed-off-by: Cheng, Tony <Tony.Cheng@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Jun Lei <jun.lei@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY+HOW]
According to HW, change default z8 enter/exist for dcn314.
SR Z8 exit = 268, change to 390.
SR Z8 enter = 393, change to 601.
Signed-off-by: Fudongwang <Fudong.Wang@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY&HOW]
Not all revisions require the same clock overrides.
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
The HDMI FRL status polling work can run concurrently with link detect
after an unplug/replug. Both paths access the same link through DDC and may
perform FRL link training, while the polling path also reads link state
without holding dc_lock.
[HOW]
Use mutex_trylock() to serialize the complete link walk, FRL status
polling, and retraining sequence with dc_lock. If the lock is busy,
defer the background poll to the next 200ms cycle instead of blocking
an active detect, modeset, or flip.
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
The QoS model override for a display IP block was silently
skipped whenever the firmware-populated table was invalid.
[How]
Always re-point the bandwidth params at the driver's own
persistent QoS model storage before applying the override,
instead of returning early when the firmware-populated model
is NULL.
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Bandwidth overrides must be applied in a defined order so debug
settings are reflected in the final parameters.
[How]
Group clock adjustments with the clock table override and derive
the final mode limits after all clock table changes.
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Keep the display QoS model and firmware table consistent when test
overrides are enabled.
[How]
Serialize the overridden QoS values into a dedicated transfer buffer
and send the table after clock initialization.
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This can simplify includes
Assisted-by: Cursor:composer-2.5
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Jun Lei <jun.lei@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
to prevent misunderstanding in cwsr off case.
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
CWSR ranges use the always mapped flag and only need a mapping on the
GPU running the queue. However, svm_range_validate_and_map now updates
the mapping on every GPU with the ACCESS attribute, which is all
supported GPUs when XNACK is on. After the range is prefetched to VRAM,
those GPUs may span different XGMI hives, so the page owner mismatches
and is set to NULL. hmm_range_fault then tries to migrate the VRAM
pages back to system memory, but svm_migrate_to_ram skips it because
migrating pages back to system memory is not allowed while the GPU
mapping is being updated, so the CPU page fault is never resolved.
Only map to the ACCESS GPUs if the range is not mapped to any GPU and
is not in VRAM.
Fixes: b96f261049 ("drm/amdkfd: Unmap svm range from GPU set to no-access")
Signed-off-by: Andrew Martin <andrew.martin@amd.com>
Assisted-by: Claude:claude-opus-5
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Philip Yang <philip.yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add initial implemenation for the new generation of mmhub
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add header files for mmhub v5_0_1 register offsets
and shift masks
v2: Update mmhub ip headers to BTO version
v3: Update registers (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add a dedicated ras_psp_v15_0_3 ip_func using PCRU0 C2PMSG_67/127
for psp ring wptr and RAS capability query.
Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
amdgpu_dpm_enable_vpe() should be skipped if dpm_enabled is false
Signed-off-by: Lin Cao <lincao12@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
PSP should not accept a GART VA directly from VF
Add logical to allocate VPE cmdbuf from VRAM
Signed-off-by: Lin Cao <lincao12@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This patch adds support for vpe v3.0.0 with new structs and ip functions
Signed-off-by: Caden Chien <chih-wei.chien@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add header files for vpe v3_0_0 register offsets
and shift masks
v2: Update vpe ip headers to LSC version
v3: Update vpe ip headers to BTO version
v4: Update registers (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
When aid_mask is set, poll MP0 C2PMSG_64 on each AID instance before
creating the PSP GFX command ring. Single-die paths are unchanged.
Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add VPE FW list including VPE_CTX and VPE_CTL
Signed-off-by: Lin Cao <lincao12@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Under SRIOV VF, GFX firmware are required to loaded.
[How]
Add GFX FW list.
FW contains:
PFP ucode, PFP data P0-P1
ME ucode, ME data P0-P1
MEC ucode, MEC data P0-P7
MES SCH ucode and data
MES KIQ ucode and data
Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
Signed-off-by: Lin Cao <lincao12@amd.com>
Reviewed-by: Frank Min<Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Handle AMDGPU_INFO_FW_MP5 in the firmware query path and report the MP5
firmware version in the debugfs firmware_info output.
Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-By: Frank Min<Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add an mp5_fw_version attribute to the fw_version sysfs group,
so userspace can read the MP5 firmware version.
Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-By: Frank Min<Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
ASP 15.0.3 stores the PSP runtime database at a fixed 64KB offset from the IP
discovery table, not at the legacy offset from the end of VRAM.
Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-By: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add firmware type retrieval in PSP v15.0.3 to adapt psp fw updates
Signed-off-by: Frank Min <Frank.Min@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add support for PSP version 15.0.3
v2: fix psp 15.0.3 C2P message reg access issue
Signed-off-by: Frank Min <Frank.Min@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add header files for mp v15_0_3 register offsets
and shift masks
v2: Update mp ip headers to LSC version
v3: Update mp ip headers to BTO version
v4: Update registers (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add support for LSDMA v8
v2: fix wait_pio_status() per Philip's comments.
Reviewed-by: Philip Yang <philip.yang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
add hdp v8 ip block
Signed-off-by: Frank Min <Frank.Min@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add header files for hdp v8_0_1 register offsets
and shift masks
v2: Update hdp ip headers to BTO version
v3: Update registers (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add initial implementation for the new generation of smuio
v2: squash in clock counter changes
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add header files for smuio v15_0_3 register offsets
and shift masks
v2: Update smuio ip headers to LSC version
v3: Update smuio ip headers to BTO version
v4: Update registers (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
On some SR-IOV VFs RCC_CONFIG_MEMSIZE reads back 0. Fall back to
RCC_HW_DEBUG for the frame buffer size in the nbif get_memsize()
callback and in the early-init paths that read the register directly.
Only VFs that read back 0 are affected.
Signed-off-by: ZhenGuo Yin <zhenguo.yin@amd.com>
Reviewed-by: Frank Min <frank.min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add initial implementation for the new generation of nbif
v2: squash in HDP, VPE, RLC/IH, SDMA fixes
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add header files for pcie v6_1_3 register offsets
and shift masks
v2: Update pcie ip headers to LSC version
v3: Update pcie ip headers to BTO version
v4: Update registers (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add header files for nbif v7_10_0 register headers
and shift masks
v2: Update nbif ip headers to LSC version
v3: Update nbif ip headers to BTO version
v4: Update registers (Alex)
v5: Squash in SR-IOV updates (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add ih v8_0 ip block
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add initial implementation for the new generation of ih
v2: squash in flood control fix
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
