This will bind to the PMGR pwrstate nodes that control power/clock
gating to SoC blocks. The mailbox driver doesn't do runtime-pm yet, so
initially this will just keep the domain on permanently.
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
We decided to keep SoC nodes sorted by address for sanity; fix a couple
that slipped into the wrong place.
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Hector Martin <marcan@marcan.st>
We now know that this frequency comes from the external reference
oscillator and is used for various SoC blocks, and isn't just a random
24MHz clock, so let's call it something more appropriate.
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Hector Martin <marcan@marcan.st>
- Add the LEDs to the Freecom FSG-3 that were missing.
- Add a devicetree for the Gorami MultiLink Router
- Add a devicetree for the Gateway GW7001 Router
This completes the migration of all IXP4xx devices to
device tree files.
Next merge window we will delete the remaining board files,
it cannot be done now because of cross-tree dependencies.
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Merge tag 'ixp4xx-dtx-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/dt
IXP4xx DTS changes for v5.17:
- Add the LEDs to the Freecom FSG-3 that were missing.
- Add a devicetree for the Gorami MultiLink Router
- Add a devicetree for the Gateway GW7001 Router
This completes the migration of all IXP4xx devices to
device tree files.
Next merge window we will delete the remaining board files,
it cannot be done now because of cross-tree dependencies.
* tag 'ixp4xx-dtx-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: dts: ixp4xx: Add devicetree for Gateway 7001
ARM: dts: Add Goramo MultiLink device tree
ARM: dts: Add FSG3 system controller and LEDs
Link: https://lore.kernel.org/r/CACRpkdYiWK7TEbZrh4_0WT5obMk=ZSc7AQVUSPXL+-uZ_hsUEA@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- 2 low priority fixes about pin function for sama7g5 and better
tailored mmc interface on sama5d2 xplained
- Addition of the Microchip EVB-KSZ9477: a Gigabit Ethernet
managed Switch Evaluation Board
- QSPI: addition of sama5d2 clock name and nodes for new sama7g7 and its
associated Evaluation Kit
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Merge tag 'at91-dt-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt
AT91 DT #1 for 5.17:
- 2 low priority fixes about pin function for sama7g5 and better
tailored mmc interface on sama5d2 xplained
- Addition of the Microchip EVB-KSZ9477: a Gigabit Ethernet
managed Switch Evaluation Board
- QSPI: addition of sama5d2 clock name and nodes for new sama7g7 and its
associated Evaluation Kit
* tag 'at91-dt-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: dts: at91: sama7g5ek: Add QSPI0 node
ARM: dts: at91: sama7g5: Add QSPI nodes
ARM: dts: at91: sama5d2: Name the qspi clock
ARM: dts: at91: add Microchip EVB-KSZ9477 board
ARM: dts: at91: sama5d2_xplained: remove PA11__SDMMC0_VDDSEL from pinctrl
ARM: dts: at91: update alternate function of signal PD20
Link: https://lore.kernel.org/r/20211213161451.90786-1-nicolas.ferre@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- helios64: hdd-power, pcie, 2.5GbE nic
- spi for rk356x and on the Quartz-A board
- headphone, bluetooth support on Rock Pi4
And some misc soc improvements:
- missing dsi compatible on px30
- pwm pinctrl name on rk356x
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Merge tag 'v5.17-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
Improvements on a number of boards:
- helios64: hdd-power, pcie, 2.5GbE nic
- spi for rk356x and on the Quartz-A board
- headphone, bluetooth support on Rock Pi4
And some misc soc improvements:
- missing dsi compatible on px30
- pwm pinctrl name on rk356x
* tag 'v5.17-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: Fix Bluetooth on ROCK Pi 4 boards
arm64: dts: rockchip: Add missing secondary compatible for PX30 DSI
arm64: dts: rockchip: Add spi1 pins on Quartz64 A
arm64: dts: rockchip: Add spi nodes on rk356x
arm64: dts: rockchip: Change pwm pinctrl-name to "default" on rk356x
arm64: dts: rockchip: Enable HDD power on helios64
arm64: dts: rockchip: add variables for pcie completion to helios64
arm64: dts: rockchip: define usb hub and 2.5GbE nic on helios64
arm64: dts: rockchip: add interrupt and headphone-detection for Rock Pi4's audio codec
Link: https://lore.kernel.org/r/3637342.7akbv5NDAT@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Separate DTs for all t8103 platforms
- Add i2c and cd321x nodes
- Bindings for apple,wdt
- PMGR bindings and DT updates to instantiate it
- WiFi MAC address DT handling
This also includes the MAINTAINERS change for the PMGR driver itself, to
avoid merge issues; the driver will be sent in a different pull.
Manual fixups: Added i2c power domain references to the PMGR DT commit,
since a prior commit added the i2c nodes.
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Merge tag 'asahi-soc-dt-5.17' of https://github.com/AsahiLinux/linux into arm/dt
Apple SoC DT updates for 5.17:
- Separate DTs for all t8103 platforms
- Add i2c and cd321x nodes
- Bindings for apple,wdt
- PMGR bindings and DT updates to instantiate it
- WiFi MAC address DT handling
This also includes the MAINTAINERS change for the PMGR driver itself, to
avoid merge issues; the driver will be sent in a different pull.
Manual fixups: Added i2c power domain references to the PMGR DT commit,
since a prior commit added the i2c nodes.
* tag 'asahi-soc-dt-5.17' of https://github.com/AsahiLinux/linux:
arm64: dts: apple: t8103: Expose PCI node for the WiFi MAC address
arm64: dts: apple: t8103: Add UART2
arm64: dts: apple: t8103: Add PMGR nodes
dt-bindings: arm: apple: Add apple,pmgr binding
dt-bindings: power: Add apple,pmgr-pwrstate binding
MAINTAINERS: Add PMGR power state files to ARM/APPLE MACHINE
dt-bindings: watchdog: Add Apple Watchdog
dt-bindings: interrupt-controller: apple,aic: Add power-domains property
dt-bindings: pinctrl: apple,pinctrl: Add power-domains property
dt-bindings: iommu: apple,dart: Add power-domains property
dt-bindings: i2c: apple,i2c: Add power-domains property
arm64: dts: apple: t8103: Add cd321x nodes
arm64: dts: apple: t8103: Add i2c nodes
arm64: dts: apple: Add missing M1 (t8103) devices
dt-bindings: arm: apple: Add iMac (24-inch 2021) to Apple bindings
arm64: dts: apple: add #interrupt-cells property to pinctrl nodes
dt-bindings: i2c: apple,i2c: allow multiple compatibles
arm64: dts: apple: change ethernet0 device type to ethernet
Link: https://lore.kernel.org/r/e18b476c-7b1f-de73-53a2-0e21fb5cd283@marcan.st
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Steven Maddox reported in the OpenWrt bugzilla, that his
RaidSonic IB-NAS4220-B was no longer booting with the new
OpenWrt 21.02 (uses linux 5.10's device-tree). However, it was
working with the previous OpenWrt 19.07 series (uses 4.14).
|[ 5.548038] No RedBoot partition table detected in 30000000.flash
|[ 5.618553] Searching for RedBoot partition table in 30000000.flash at offset 0x0
|[ 5.739093] No RedBoot partition table detected in 30000000.flash
|...
|[ 7.039504] Waiting for root device /dev/mtdblock3...
The provided bootlog shows that the RedBoot partition parser was
looking for the partition table "at offset 0x0". Which is strange
since the comment in the device-tree says it should be at 0xfe0000.
Further digging on the internet led to a review site that took
some useful PCB pictures of their review unit back in February 2009.
Their picture shows a Spansion S29GL128N11TFI01 flash chip.
>From Spansion's Datasheet:
"S29GL128N: One hundred twenty-eight 64 Kword (128 Kbyte) sectors"
Steven also provided a "cat /sys/class/mtd/mtd0/erasesize" from his
unit: "131072".
With the 128 KiB Sector/Erasesize in mind. This patch changes the
fis-index-block property to (0xfe0000 / 0x20000) = 0x7f.
Fixes: b5a923f8c7 ("ARM: dts: gemini: Switch to redboot partition parsing")
Reported-by: Steven Maddox <s.maddox@lantizia.me.uk>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Steven Maddox <s.maddox@lantizia.me.uk>
Link: https://lore.kernel.org/r/20211206004334.4169408-1-linus.walleij@linaro.org'
Bugzilla: https://bugs.openwrt.org/index.php?do=details&task_id=4137
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The SPEAr320s SOC is a SPEAr320 SOC variant.
Mostly identical to the SPEAr320 SOC variant, it has a
new interrupt routing for PL_PGIOs.
Add spear320s.dtsi to handle SPEAr320s SOC
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Link: https://lore.kernel.org/r/20211202095255.165797-7-herve.codina@bootlin.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Resources used by plgpio and pinmux are conflicting on SPEAr310
and SPEAr320.
Use the newly introduced regmap property in plgpio node to use
pinmux resources from plgpio and so avoid the conflict.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Link: https://lore.kernel.org/r/20211202095255.165797-5-herve.codina@bootlin.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Naming clocks is a good practice. The atmel-quadspi driver supports
an unnamed clock for the peripheral clock in order to be backward
compatible with old DTs, but it is recommended to name the clocks
on new DTs. The driver's bindings file requires the clock-names
property, so name the clock.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211209102542.254153-1-tudor.ambarus@microchip.com
This adds a device tree for the Gateway 7001 AP, based on
Intel IXP422.
Cc: Imre Kaloz <kaloz@openwrt.org>
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch fixes the Bluetooth on ROCK Pi 4 boards.
ROCK Pi 4 boards has BCM4345C5 and now it is supported
on Mainline Linux, brcm,bcm43438-bt still working but
observed the BT Audio issues with latest test.
So, use the BCM4345C5 compatible and its associated
properties like clock-names as lpo and max-speed.
Attach vbat and vddio supply rails as well.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Link: https://lore.kernel.org/r/20211112142359.320798-1-jagan@amarulasolutions.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add second DSI compatible to comply with DT schema validation
comming in the second patch.
Signed-off-by: David Heidelberg <david@ixit.cz>
Link: https://lore.kernel.org/r/20211211233818.88482-1-david@ixit.cz
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the watchdog node which also enables reboot support on the t8103.
Signed-off-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Hector Martin <marcan@marcan.st>
This new SoC uses the same pinctrl hardware, so just add a new per-SoC
compatible.
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
This new SoC is compatible with the existing driver, but the block
supports 4 downstream ports, so we need to adjust the binding to
allow that.
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
This block is compatible with t8103, so just add the new per-SoC
compatible under apple,i2c.
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
This is required for DCP to boot successfully; it seems if power gating
is allowed, they do not wake up properly.
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Hector Martin <marcan@marcan.st>
A few devices (DCP/DCPEXT) need to have the minimum power state for
auto-PM configured. Add a property that allows the DT to specify this
value.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
The Quartz64 Model A has the SPI pins broken out on its pin
header. The actual pins being used though are not the m0
variant, but the m1 variant, which also lacks the cs1 pin.
This commit overrides pinctrl-0 accordingly for this board.
spi1 is intentionally left disabled, as anyone wishing to add
SPI devices needs to edit the dts anyway, and the pins are more
useful as GPIOs for the rest of the users.
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Link: https://lore.kernel.org/r/20211127141910.12649-4-frattaroli.nicolas@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This adds the four spi nodes (spi0, spi1, spi2, spi3) to the
rk356x dtsi. These are from the downstream device tree, though
I have double-checked that their interrupts and DMA numbers are
correct. I have also tested spi1 with an SPI device.
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Link: https://lore.kernel.org/r/20211127141910.12649-3-frattaroli.nicolas@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
I/O voltage for eMMC is always 3.3V because PA11__SDMMC0_VDDSEL is
tied with 10K resistor to GND. U13 switch S1 is always selected as
voltage rail of 3.3V for VCCQ power pin from MPU controller and eMMC flash.
Removing PA11 from pinctrl because it remains unused.
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211026132034.678655-1-eugen.hristev@microchip.com
The alternate function of PD20 is 4 as per the datasheet of
sama7g5 and not 5 as defined earlier.
Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com>
Fixes: 7540629e2f ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek")
Cc: <stable@vger.kernel.org> # v5.15+
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211208063553.19807-1-Hari.PrasathGE@microchip.com
The driver doesn't support these, they shouldn't be in the SoC include
anyway, and we're now configuring this in the bootloader instead. This
also solves the j274 1G/10G Ethernet variant discrepancy, since that
will now be configured properly based on the dynamic ADT property.
Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
Expose the PCI node corresponding to the WiFi device and give it
a 'local-mac-address' property. The bootloader will update it
(m1n1 already has the required feature).
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Acked-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
This UART is connected to the debug port of the WLAN module. It is
mostly useless, but makes for a good test case for runtime-pm without
having to unbind the console from the main system UART.
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
This adds the two PMGR nodes and all known power state subnodes. Since
there are a large number of them, let's put them in a separate file to
include.
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Hector Martin <marcan@marcan.st>
The PMGR block in Apple Silicon SoCs is responsible for SoC power
management. There are two PMGRs in T8103, with different register
layouts but compatible registers. In order to support this as well
as future SoC generations with backwards-compatible registers, we
declare these blocks as syscons and bind to individual registers
in child nodes. Each register controls one SoC device.
The respective apple compatibles are defined in case device-specific
quirks are necessary in the future, but currently these nodes are
expected to be bound by the generic syscon driver.
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
This syscon child node represents a single SoC device controlled by the
PMGR block. This layout allows us to declare all device power state
controls (power/clock gating and reset) in the device tree, including
dependencies, instead of hardcoding it into the driver. The register
layout is uniform.
Each pmgr-pwrstate node provides genpd and reset features, to be
consumed by downstream device nodes.
Future SoCs are expected to use backwards compatible registers, and the
"apple,pmgr-pwrstate" represents any such interfaces (possibly with
additional features gated by the more specific compatible), allowing
them to be bound without driver updates. If a backwards incompatible
change is introduced in future SoCs, it will require a new compatible,
such as "apple,pmgr-pwrstate-v2".
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
This covers the PMGR power state driver and its DT bindings,
as well as any other future stuff in drivers/soc/apple.
Signed-off-by: Hector Martin <marcan@marcan.st>
Apple SoCs come with a simple embedded watchdog. This watchdog is also
required in order to reset the SoC.
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sven Peter <sven@svenpeter.dev>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Hector Martin <marcan@marcan.st>
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
board.
Genaral features:
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- 10" LVDS Panel (SN65DSI84 DSI-LVDS bridge on SoM)
i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.
10.1" OF is a capacitive touch 10.1" Open Frame panel solutions.
i.Core STM32MP1 needs to mount on top of C.TOUCH 2.0 carrier with
pluged 10.1" OF for creating complete i.Core STM32MP1 C.TOUCH 2.0
10.1" Open Frame board.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.
C.TOUCH 2.0 is a general purpose carrier board with capacitive
touch interface support.
10.1" OF is a capacitive touch 10.1" Open Frame panel solutions.
i.Core STM32MP1 needs to mount on top of C.TOUCH 2.0 carrier with
pluged 10.1" OF for creating complete i.Core STM32MP1 C.TOUCH 2.0
10.1" Open Frame board.
Add bindings for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit has plugged with
7" LVDS panel.
Engicam i.Core STM32MP1 SoM has SN65DSI84 DSI to LVDS bridge.
This patch adds a display pipeline to connect DSI to SN65DSI84
to 7" LVDS panel.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
This adds a device tree for the Goramo MultiLink IXP425-based
WAN router.
Cc: Krzysztof Hałasa <khalasa@piap.pl>
Cc: openwrt-devel@lists.openwrt.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This will bind to the PMGR pwrstate nodes that control power/clock
gating to SoC blocks. The AIC driver doesn't do runtime-pm and likely
never will (since it is system-critical), but it makes sense to describe
the power domain relationship the devicetree properly.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
This will bind to the PMGR pwrstate nodes that control power/clock
gating to SoC blocks. The pinctrl driver doesn't do runtime-pm yet, so
initially this will just keep the domain on permanently.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
