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1,399,042 commits

Author SHA1 Message Date
Raphael Gallais-Pou
092f7634ff arm64: dts: st: add clock-cells to syscfg node on stm32mp251
Make the syscfg node a clock provider so clock consumers can reach child
clocks through device-tree.

Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
Acked-by: Yannick Fertre <yannick.fertre@foss.st.com>
Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-12-9c825e28f733@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15 17:51:31 +02:00
Raphael Gallais-Pou
c067119b07 arm64: dts: st: add lvds support on stm32mp255
The LVDS is used on STM32MP2 as a display interface.

Add the LVDS node.

Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
Acked-by: Yannick Fertre <yannick.fertre@foss.st.com>
Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-11-9c825e28f733@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15 17:51:31 +02:00
Raphael Gallais-Pou
84b78bc2cb arm64: dts: st: add ltdc support on stm32mp255
Add the LTDC node for stm32mp255 SoC and handle its loopback clocks.

ck_ker_ltdc has the CLK_SET_RATE_PARENT flag.  While having this flag is
semantically correct, it for now leads to an improper setting of the
clock rate.  The ck_ker_ltdc parent clock is the flexgen 27, which does
not support changing rates yet.  To overcome this issue, a fixed clock
can be used for the kernel clock.

Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
Acked-by: Yannick Fertre <yannick.fertre@foss.st.com>
Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-10-9c825e28f733@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15 17:51:31 +02:00
Raphael Gallais-Pou
114e282d51 arm64: dts: st: add ltdc support on stm32mp251
The LCD-TFT Display Controller (LTDC) handles display composition,
scaling and rotation.  It provides a parallel digital RGB flow to be
used by display interfaces.

Add the LTDC node.

Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
Acked-by: Yannick Fertre <yannick.fertre@foss.st.com>
Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-9-9c825e28f733@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15 17:51:30 +02:00
Marc Kleine-Budde
6bb200f11a ARM: dts: stm32: add resets property to m_can nodes in the stm32mp153
On the STM32MP153 the m_cam IP cores (a.k.a. FDCAN) have an external
shared reset in the RCC. Add the reset to both m_can nodes.

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Link: https://lore.kernel.org/r/20250807-stm32mp15-m_can-add-reset-v2-2-f69ebbfced1f@pengutronix.de
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15 17:51:30 +02:00
Marc Kleine-Budde
dd1704a507 dt-binding: can: m_can: add optional resets property
The m_can IP core has an external reset line. Add it to the bindings
documentation.

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250807-stm32mp15-m_can-add-reset-v2-1-f69ebbfced1f@pengutronix.de
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15 17:51:30 +02:00
Christian Bruel
30793e0108 arm64: dts: st: Enable PCIe on the stm32mp257f-ev1 board
Add PCIe RC and EP support on stm32mp257f-ev1 board.
Default to RC mode.

Signed-off-by: Christian Bruel <christian.bruel@foss.st.com>
Link: https://lore.kernel.org/r/20250820075411.1178729-12-christian.bruel@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15 17:51:30 +02:00
Christian Bruel
73d536ae1a arm64: dts: st: Add PCIe Endpoint mode on stm32mp251
Add pcie_ep node to support STM32 MP25 PCIe driver based on the
DesignWare PCIe core configured as Endpoint mode

Signed-off-by: Christian Bruel <christian.bruel@foss.st.com>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://lore.kernel.org/r/20250820075411.1178729-11-christian.bruel@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15 17:51:30 +02:00
Christian Bruel
0ecdf6d2f5 arm64: dts: st: Add PCIe Root Complex mode on stm32mp251
Add pcie_rc node to support STM32 MP25 PCIe driver based on the
DesignWare PCIe core configured as Root Complex mode

Supports Gen1/Gen2, single lane, MSI interrupts using the ARM GICv2m

Signed-off-by: Christian Bruel <christian.bruel@foss.st.com>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://lore.kernel.org/r/20250820075411.1178729-10-christian.bruel@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15 17:51:30 +02:00
Christian Bruel
7e4479c924 arm64: dts: st: add PCIe pinctrl entries in stm32mp25-pinctrl.dtsi
Add PCIe pinctrl entries in stm32mp25-pinctrl.dtsi
init: forces GPIO to low while probing so CLKREQ is low for
phy_init
default: restore the AFMUX after controller probe

Add Analog pins of PCIe to perform power cycle

Signed-off-by: Christian Bruel <christian.bruel@foss.st.com>
Link: https://lore.kernel.org/r/20250820075411.1178729-9-christian.bruel@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15 17:51:30 +02:00
Patrice Chotard
27cd5cd8bd arm64: defconfig: Enable STMicroelectronics STM32 DMA3 support
Enable STMicroelectronics STM32 DMA3 support as module.
STM32 DMA3 is used among others by STM32 Octo SPI driver on
STM32MP257F-EV1 board.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250821-upstream_defconfig_enable_stm32_dma3-v1-1-d9c1b71883d9@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15 17:51:30 +02:00
Clément Le Goffic
d0647b20d1 ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp157c-dk2 board
On the stm32mp157fc-dk2 board, we can observe the hdp GPOVAL function on
SoC pin E13 accessible on the pin 5 on the Arduino connector CN13.
Add the relevant configuration but keep it disabled as it's used for
debug only.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Link: https://lore.kernel.org/r/20250711-hdp-upstream-v7-8-faeecf7aaee1@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15 17:51:30 +02:00
Clément Le Goffic
3d42567279 ARM: dts: stm32: add alternate pinmux for HDP pin and add HDP pinctrl node
Introduce hdp node to output a user defined value on port hdp2.
Add pinctrl nodes to be able to output this signal on one SoC pin.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20250711-hdp-upstream-v7-7-faeecf7aaee1@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15 17:51:30 +02:00
Clément Le Goffic
f398bb6183 arm64: dts: st: add Hardware debug port (HDP) on stm32mp25
Add the hdp devicetree node for stm32mp25 SoC family

Keep the node disabled as HDP needs the pinctrl SoC configuration to be
able to output its mux output signal outside of the SoC, on the SoC pad.
This configuration is provided in the board dtsi file through 'pinctrl-*'
properties as well as HDP mux configuration.
Thus, if needed, HDP should be enabled in board dtsi file.

Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com>
Link: https://lore.kernel.org/r/20250711-hdp-upstream-v7-6-faeecf7aaee1@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-09-15 17:51:02 +02:00
Thorsten Blum
4c8bad3ed0 xtensa: use HZ_PER_MHZ in platform_calibrate_ccount
Replace the hardcoded 1000000UL with the HZ_PER_MHZ unit macro, and add
a space in "10 MHz" to improve the readability of the error message.

Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev>
Message-Id: <20250915120540.2150841-3-thorsten.blum@linux.dev>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2025-09-15 08:37:28 -07:00
Amirreza Zarrabi
dcc7a571a3 Documentation: tee: Add Qualcomm TEE driver
Add documentation for the Qualcomm TEE driver.

Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2025-09-15 17:34:06 +02:00
Amirreza Zarrabi
87ab676d90 tee: qcom: enable TEE_IOC_SHM_ALLOC ioctl
Enable userspace to allocate shared memory with QTEE. Since
QTEE handles shared memory as object, a wrapper is implemented
to represent tee_shm as an object. The shared memory identifier,
obtained through TEE_IOC_SHM_ALLOC, is transferred to the driver using
TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF_INPUT/OUTPUT.

Tested-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Tested-by: Harshal Dev <quic_hdev@quicinc.com>
Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2025-09-15 17:34:06 +02:00
Amirreza Zarrabi
0f7bfdcb7c tee: qcom: add primordial object
After booting, the kernel provides a static object known as the
primordial object. This object is utilized by QTEE for native
kernel services such as yield or privileged operations.

Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Harshal Dev <quic_hdev@quicinc.com>
Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2025-09-15 17:34:06 +02:00
Amirreza Zarrabi
d6e290837e tee: add Qualcomm TEE driver
Introduce qcomtee_object, which represents an object in both QTEE and
the kernel. QTEE clients can invoke an instance of qcomtee_object to
access QTEE services. If this invocation produces a new object in QTEE,
an instance of qcomtee_object will be returned.

Similarly, QTEE can request services from by issuing a callback
request, which invokes an instance of qcomtee_object.

Implement initial support for exporting qcomtee_object to userspace
and QTEE, enabling the invocation of objects hosted in QTEE and userspace
through the TEE subsystem.

Tested-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Harshal Dev <quic_hdev@quicinc.com>
Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2025-09-15 17:34:06 +02:00
Amirreza Zarrabi
bd51393068 tee: increase TEE_MAX_ARG_SIZE to 4096
Increase TEE_MAX_ARG_SIZE to accommodate worst-case scenarios where
additional buffer space is required to pass all arguments to TEE.
This change is necessary for upcoming support for Qualcomm TEE, which
requires a larger buffer for argument marshaling.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Tested-by: Harshal Dev <quic_hdev@quicinc.com>
Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2025-09-15 17:34:06 +02:00
Amirreza Zarrabi
d5b8b0fa17 tee: add TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF
The TEE subsystem allows session-based access to trusted services,
requiring a session to be established to receive a service. This
is not suitable for an environment that represents services as objects.
An object supports various operations that a client can invoke,
potentially generating a result or a new object that can be invoked
independently of the original object.

Add TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF_INPUT/OUTPUT/INOUT to represent an
object. Objects may reside in either TEE or userspace. To invoke an
object in TEE, introduce a new ioctl. Use the existing SUPPL_RECV and
SUPPL_SEND to invoke an object in userspace.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Harshal Dev <quic_hdev@quicinc.com>
Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2025-09-15 17:34:06 +02:00
Amirreza Zarrabi
54a53e95a9 tee: add TEE_IOCTL_PARAM_ATTR_TYPE_UBUF
For drivers that can transfer data to the TEE without using shared
memory from client, it is necessary to receive the user address
directly, bypassing any processing by the TEE subsystem. Introduce
TEE_IOCTL_PARAM_ATTR_TYPE_UBUF_INPUT/OUTPUT/INOUT to represent
userspace buffers.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Harshal Dev <quic_hdev@quicinc.com>
Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2025-09-15 17:34:06 +02:00
Amirreza Zarrabi
0cbaf65c91 tee: add close_context to TEE driver operation
The tee_context can be used to manage TEE user resources, including
those allocated by the driver for the TEE on behalf of the user.
The release() callback is invoked only when all resources, such as
tee_shm, are released and there are no references to the tee_context.

When a user closes the device file, the driver should notify the
TEE to release any resources it may hold and drop the context
references. To achieve this, a close_context() callback is
introduced to initiate resource release in the TEE driver when
the device file is closed.

Relocate teedev_ctx_get, teedev_ctx_put, tee_device_get, and
tee_device_get functions to tee_core.h to make them accessible
outside the TEE subsystem.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Harshal Dev <quic_hdev@quicinc.com>
Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2025-09-15 17:34:06 +02:00
Amirreza Zarrabi
6dbcd5a9ab tee: allow a driver to allocate a tee_device without a pool
A TEE driver doesn't always need to provide a pool if it doesn't
support memory sharing ioctls and can allocate memory for TEE
messages in another way. Although this is mentioned in the
documentation for tee_device_alloc(), it is not handled correctly.

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2025-09-15 17:34:06 +02:00
Fushuai Wang
84afb84bcc drm/xe: Use ERR_CAST instead of ERR_PTR(PTR_ERR(...))
Use ERR_CAST inline function instead of ERR_PTR(PTR_ERR(...)).

Signed-off-by: Fushuai Wang <wangfushuai@baidu.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20250914101630.17719-1-wangfushuai@baidu.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
2025-09-15 08:32:51 -07:00
Jens Wiklander
36629d5224 Merge branch '20250911-qcom-tee-using-tee-ss-without-mem-obj-v12-2-17f07a942b8d@oss.qualcomm.com' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux
firmware: qcom: tzmem: export shm_bridge create/delete
      firmware: qcom: scm: add support for object invocation

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2025-09-15 17:27:31 +02:00
David Kaplan
9a9f8147ae x86/bugs: Use early_param() for spectre_v2
Most of the mitigations in bugs.c use early_param() for command line parsing.
Rework the spectre_v2 and nospectre_v2 command line options to be
consistent with the others.

Remove spec_v2_print_cond() as informing the user of the their cmdline
choice isn't interesting.

  [ bp: Zap spectre_v2_check_cmd(). ]

Signed-off-by: David Kaplan <david.kaplan@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Link: https://lore.kernel.org/r/20250819192200.2003074-3-david.kaplan@amd.com
2025-09-15 17:26:49 +02:00
Martin George
6ff1bd7846 nvme-auth: update bi_directional flag
While setting chap->s2 to zero as part of secure channel
concatenation, the host missed out to disable the bi_directional
flag to indicate that controller authentication is not requested.
Fix the same.

Fixes: e88a7595b5 ("nvme-tcp: request secure channel concatenation")
Signed-off-by: Martin George <marting@netapp.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Keith Busch <kbusch@kernel.org>
2025-09-15 08:26:30 -07:00
Alok Tiwari
c5e389cc6b net/mlx5: fix typo in pci_irq.c comment
Fix a typo in a comment in pci_irq.c:
 "ssigned" → "assigned"

Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/20250912135050.3921116-1-alok.a.tiwari@oracle.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-09-15 08:24:23 -07:00
Jens Axboe
1b3aa39007 io_uring/uring_cmd: correct signature for io_uring_mshot_cmd_post_cqe()
The !CONFIG_IO_URING signature is wrong, fix that up. The non stub
signature got updated for the io_br_sel changes that happened before
this patch went in, but the stub one did not.

Fixes: 620a50c927 ("io_uring: uring_cmd: add multishot support")
Signed-off-by: Jens Axboe <axboe@kernel.dk>
2025-09-15 09:17:24 -06:00
Linus Torvalds
46a51f4f5e Power Supply Fixes for 6.17 cycle
* bq27xxx: avoid spamming the log for missing bq27000 battery
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Merge tag 'for-v6.17-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply

Pull power supply fixes from Sebastian Reichel:

 - bq27xxx: avoid spamming the log for missing bq27000 battery

* tag 'for-v6.17-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply:
  power: supply: bq27xxx: restrict no-battery detection to bq27000
  power: supply: bq27xxx: fix error return in case of no bq27000 hdq battery
2025-09-15 08:15:11 -07:00
Jakub Kicinski
8c42986b02 Merge branch 'dpll-zl3073x-add-support-for-devlink-flash'
Ivan Vecera says:

====================
dpll: zl3073x: Add support for devlink flash

Add functionality for accessing device hardware registers, loading
firmware bundles, and accessing the device's internal flash memory,
and use it to implement the devlink flash functionality.
====================

Link: https://patch.msgid.link/20250909091532.11790-1-ivecera@redhat.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-09-15 08:08:41 -07:00
Ivan Vecera
a1e891fe4a dpll: zl3073x: Implement devlink flash callback
Use the introduced functionality to read firmware files and flash their
contents into the device's internal flash memory to implement the devlink
flash update callback.

Sample output on EDS2 development board:
 # devlink -j dev info i2c/1-0070 | jq '.[][]["versions"]["running"]'
 {
   "fw": "6026"
 }
 # devlink dev flash i2c/1-0070 file firmware_fw2.hex
 [utility] Prepare flash mode
 [utility] Downloading image 100%
 [utility] Flash mode enabled
 [firmware1-part1] Downloading image 100%
 [firmware1-part1] Flashing image
 [firmware1-part2] Downloading image 100%
 [firmware1-part2] Flashing image
 [firmware1] Flashing done
 [firmware2] Downloading image 100%
 [firmware2] Flashing image 100%
 [firmware2] Flashing done
 [utility] Leaving flash mode
 Flashing done
 # devlink -j dev info i2c/1-0070 | jq '.[][]["versions"]["running"]'
 {
   "fw": "7006"
 }

Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
Signed-off-by: Ivan Vecera <ivecera@redhat.com>
Link: https://patch.msgid.link/20250909091532.11790-6-ivecera@redhat.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-09-15 08:08:39 -07:00
Ivan Vecera
ebb1031c51 dpll: zl3073x: Refactor DPLL initialization
Refactor DPLL initialization and move DPLL (de)registration, monitoring
control, fetching device invariant parameters and phase offset
measurement block setup to separate functions.

Use these new functions during device probe and teardown functions and
during changes to the clock_id devlink parameter.

These functions will also be used in the next patch implementing devlink
flash, where this functionality is likewise required.

Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
Signed-off-by: Ivan Vecera <ivecera@redhat.com>
Link: https://patch.msgid.link/20250909091532.11790-5-ivecera@redhat.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-09-15 08:08:39 -07:00
Ivan Vecera
ca017409da dpll: zl3073x: Add firmware loading functionality
Add functionality for loading firmware files provided by the vendor
to be flashed into the device's internal flash memory. The firmware
consists of several components, such as the firmware executable itself,
chip-specific customizations, and configuration files.

The firmware file contains at least a flash utility, which is executed
on the device side, and one or more flashable components. Each component
has its own specific properties, such as the address where it should be
loaded during flashing, one or more destination flash pages, and
the flashing method that should be used.

Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
Signed-off-by: Ivan Vecera <ivecera@redhat.com>
Link: https://patch.msgid.link/20250909091532.11790-4-ivecera@redhat.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-09-15 08:08:39 -07:00
Ivan Vecera
3639bd0876 dpll: zl3073x: Add low-level flash functions
To implement the devlink device flash functionality, the driver needs
to access both the device memory and the internal flash memory. The flash
memory is accessed using a device-specific program (called the flash
utility). This flash utility must be downloaded by the driver into
the device memory and then executed by the device CPU. Once running,
the flash utility provides a flash API to access the flash memory itself.

During this operation, the normal functionality provided by the standard
firmware is not available. Therefore, the driver must ensure that DPLL
callbacks and monitoring functions are not executed during the flash
operation.

Add all necessary functions for downloading the utility to device memory,
entering and exiting flash mode, and performing flash operations.

Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
Signed-off-by: Ivan Vecera <ivecera@redhat.com>
Link: https://patch.msgid.link/20250909091532.11790-3-ivecera@redhat.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-09-15 08:08:39 -07:00
Ivan Vecera
259ede9da4 dpll: zl3073x: Add functions to access hardware registers
Besides the device host registers that are directly accessible, there
are also hardware registers that can be accessed indirectly via specific
host registers.

Add register definitions for accessing hardware registers and provide
helper functions for working with them. Additionally, extend the number
of pages in the regmap configuration to 256, as the host registers used
for accessing hardware registers are located on page 255.

Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
Signed-off-by: Ivan Vecera <ivecera@redhat.com>
Link: https://patch.msgid.link/20250909091532.11790-2-ivecera@redhat.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-09-15 08:08:38 -07:00
David Kaplan
8edb9e7711 x86/bugs: Use early_param() for spectre_v2_user
Most of the mitigations in bugs.c use early_param() to parse their command
line options.  Modify spectre_v2_user to use early_param() for consistency.

Remove spec_v2_user_print_cond() because informing a user about their
cmdline choice isn't very interesting and the chosen mitigation is already
printed in spectre_v2_user_update_mitigation().

Signed-off-by: David Kaplan <david.kaplan@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Link: https://lore.kernel.org/r/20250819192200.2003074-2-david.kaplan@amd.com
2025-09-15 17:07:22 +02:00
Hans de Goede
b8cac8c98e power: supply: intel_dc_ti_battery: Drop no longer relevant comment
Drop the comment about not being able to use devm_iio_channel_get().
The code has actually already successfully been switched over to
devm_iio_channel_get(). This is just a no longer applicable left-over
comment, drop it.

Signed-off-by: Hans de Goede <hansg@kernel.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2025-09-15 17:06:55 +02:00
Lucas De Marchi
19baa830fb drm/xe: Use ARRAY_SIZE in guc_waklv_init()
Prefer using ARRAY_SIZE where needed and just passing 1 instead of
calculating the size of one element.

Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202508130158.eogeBZQT-lkp@intel.com/
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Link: https://lore.kernel.org/r/20250912-guc-ads-array-size-v1-1-a6555392a1f8@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
2025-09-15 07:50:53 -07:00
Vlastimil Babka
3864e4d5a5 slab: don't validate slab pointer in free_debug_processing()
The struct slab pointer has been obtained from the object being freed on
all the paths that lead to this function. In all cases this already
includes the test for slab type of the struct page which struct slab is
overlaying. Thus we would not reach this function if it was not a valid
slab pointer in the first place.

One less obvious case is that kmem_cache_free() trusts virt_to_slab()
blindly so it may be NULL if the slab type check is false. But with
SLAB_CONSISTENCY_CHECKS, cache_from_obj() called also from
kmem_cache_free() catches this and returns NULL, which terminates
freeing immediately.

Reviewed-by: Harry Yoo <harry.yoo@oracle.com>
Signed-off-by: Vlastimil Babka <vbabka@suse.cz>
2025-09-15 16:48:03 +02:00
Vlastimil Babka
a21fe7b010 slab: validate slab before using it in alloc_single_from_partial()
We touch slab->freelist and slab->inuse before checking the slab pointer
is actually sane. Do that validation first, which will be safer. We can
thus also remove the check from alloc_debug_processing().

This adds a new "s->flags & SLAB_CONSISTENCY_CHECKS" test but
alloc_single_from_partial() is only called for caches with debugging
enabled so it's acceptable.

In alloc_single_from_new_slab() we just created the struct slab and call
alloc_debug_processing() to mainly set up redzones, tracking etc, while
not really expecting the consistency checks to fail. Thus don't validate
it there.

Reviewed-by: Harry Yoo <harry.yoo@oracle.com>
Signed-off-by: Vlastimil Babka <vbabka@suse.cz>
2025-09-15 16:47:36 +02:00
Rob Herring (Arm)
a409fac1f7
ARM: dts: socionext: Drop "linux,spdif-dit" port node unit-address
A single graph port node without an address (i.e. "reg") should not have
a unit-address, drop it from the "linux,spdif-dit" port node.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250910233740.777077-2-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15 16:43:56 +02:00
Arnd Bergmann
9674bc8805 mtk-svs:
* Drop reference taken on probe failure
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Merge tag 'v6.17-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/drivers

mtk-svs:
* Drop reference taken on probe failure

* tag 'v6.17-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
  soc: mediatek: mtk-svs: fix device leaks on mt8192 probe failure
  soc: mediatek: mtk-svs: fix device leaks on mt8183 probe failure

Link: https://lore.kernel.org/r/87c8f50b-90a5-47ed-af60-99a4e075a266@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15 16:43:16 +02:00
Arnd Bergmann
6c1c107bf5 i.MX arm64 device tree changes for 6.18:
- New device trees: TQMa91xx/MBa91xxCA, Ultratronik Ultra-MACH SBC,
   SolidRun i.MX8MP SoM, i.MX8ULP EVK9, TQMLS1012AL, i.MX91 11x11 EVK,
   EDM-G-IMX8M-PLUS SOM
 - A bunch of Kontron boards update from Annette Kobou and Frieder Schrempf,
   adding overlay for LTE extension board, fixing GPIO for panel regulator,
   removing unused regulators, fixing USB hub reset and USB port etc.
 - A number of s32g updates from Dan Carpenter and Daniel Lezcano, adding
   OCOTP, timers and watchdog support
 - An i.MX95 update from Frank Li to add msi-map for pci-ep device
 - A series from Joy Zou to add i.MX91 support
 - A series from Krzysztof Kozlowski to add default GIC address cells for
   LS and i.MX8 SoCs
 - A set of changes from Peng Fan to improve i.MX95 support with more devices
   enabled
 - A series from Shengjiu Wang to support more sample rates for wm8524 card
   on i.MX8M EVK boards
 - Other random updates and cleanups on various boards
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Merge tag 'imx-dt64-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt

i.MX arm64 device tree changes for 6.18:

- New device trees: TQMa91xx/MBa91xxCA, Ultratronik Ultra-MACH SBC,
  SolidRun i.MX8MP SoM, i.MX8ULP EVK9, TQMLS1012AL, i.MX91 11x11 EVK,
  EDM-G-IMX8M-PLUS SOM
- A bunch of Kontron boards update from Annette Kobou and Frieder Schrempf,
  adding overlay for LTE extension board, fixing GPIO for panel regulator,
  removing unused regulators, fixing USB hub reset and USB port etc.
- A number of s32g updates from Dan Carpenter and Daniel Lezcano, adding
  OCOTP, timers and watchdog support
- An i.MX95 update from Frank Li to add msi-map for pci-ep device
- A series from Joy Zou to add i.MX91 support
- A series from Krzysztof Kozlowski to add default GIC address cells for
  LS and i.MX8 SoCs
- A set of changes from Peng Fan to improve i.MX95 support with more devices
  enabled
- A series from Shengjiu Wang to support more sample rates for wm8524 card
  on i.MX8M EVK boards
- Other random updates and cleanups on various boards

* tag 'imx-dt64-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (75 commits)
  arm64: dts: s32g: Add device tree information for the OCOTP driver
  arm64: dts: add description for solidrun imx8mp hummingboard variants
  arm64: dts: imx8mm-phycore-som: optimize drive strengh
  arm64: dts: freescale: imx93-phycore-som: Remove "fsl,magic-packet"
  arm64: dts: freescale: imx93-phyboard-nash: Current sense via iio-hwmon
  arm64: dts: imx95: add standard PCI device compatible string to NETC Timer
  arm64: dts: freescale: add initial device tree for TQMa91xx/MBa91xxCA
  arm64: dts: imx93-11x11-evk: remove fec property eee-broken-1000t
  arm64: dts: freescale: add i.MX91 11x11 EVK basic support
  arm64: dts: imx91: add i.MX91 dtsi support
  arm64: dts: freescale: rename imx93.dtsi to imx91_93_common.dtsi and modify them
  arm64: dts: freescale: move aliases from imx93.dtsi to board dts
  arm64: dts: lx2160a-clearfog-itx: enable pcie nodes for x4 and x8 slots
  arm64: dts: lx2160a-cex7: add interrupts for rtc and ethernet phy
  arm64: dts: add description for solidrun imx8mp som and cubox-m
  arm64: dts: imx8: Use GIC_SPI for interrupt-map for readability
  arm64: dts: imx8qxp: Add default GIC address cells
  arm64: dts: imx8qm: Add default GIC address cells
  arm64: dts: imx8mq: Add default GIC address cells
  arm64: dts: imx8mp: Add default GIC address cells
  ...

Link: https://lore.kernel.org/r/20250915132535.253859-3-shawnguo2@yeah.net
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15 16:36:50 +02:00
Arnd Bergmann
636d134e3c i.MX ARM device tree changes for 6.18:
- A series from Alexander Stein to clean up the most of dt-schema warnings
   for LS1021A
 - A couple of changes from Bence Csókás to replace license text comment
   with SPDX identifier for imx6-display5 and imx6-aristainetos2 board
 - A couple of vfxxx dt-schema cleanups from Fabio Estevam
 - A bunch of changes from Frank Li to clean up dt-schema warnings on
   various platforms, VF610, LS1021A, i.MX6, etc.
 - Minor whitespace cleanup on i.MX8ULL from Krzysztof Kozlowski
 - An imx6ulz-bsh-smm-m2 workaround from Wolfgang Birkner to get resume
   via console work
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Merge tag 'imx-dt-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt

i.MX ARM device tree changes for 6.18:

- A series from Alexander Stein to clean up the most of dt-schema warnings
  for LS1021A
- A couple of changes from Bence Csókás to replace license text comment
  with SPDX identifier for imx6-display5 and imx6-aristainetos2 board
- A couple of vfxxx dt-schema cleanups from Fabio Estevam
- A bunch of changes from Frank Li to clean up dt-schema warnings on
  various platforms, VF610, LS1021A, i.MX6, etc.
- Minor whitespace cleanup on i.MX8ULL from Krzysztof Kozlowski
- An imx6ulz-bsh-smm-m2 workaround from Wolfgang Birkner to get resume
  via console work

* tag 'imx-dt-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (44 commits)
  ARM: dts: imx6sll: Use 'dma-names'
  ARM: dts: imx6: change rtc compatible string to st,m41t00 from m41t00
  ARM: dts: imx6: remove undefined linux,default-trigger source
  ARM: dts: imx6ul-pico: add power-supply for vxt,vl050-8048nt-c01
  ARM: dts: imx6ul-14x14-evk: add regulator for ov5640
  ARM: dts: imx6: replace isl,isl12022 with isil,isl12022 for RTC
  ARM: dts: imx6: replace gpio-key with gpio-keys compatible string
  ARM: dts: imx6: rename i2c<n>mux i2c-mux-<n>
  ARM: dts: imx6: rename node name flash to eeprom
  ARM: dts: imx6: rename node i2c-gpio to i2c.
  ARM: dts: imx6: rename touch screen's node name to touchscreen
  ARM: dts: imx6: remove redundant pinctrl-names
  ARM: dts: imx6qdl-aristainetos2: rename ethernet-phy to ethernet-phy@0
  ARM: dts: imx6: add interrupt-cells for dlg,da9063 pmic
  ARM: dts: imx6: align rtc chip node name to 'rtc'
  ARM: dts: imx6: add key- prefix for gpio-keys
  ARM: dts: imx6: add #address-cells for gsc@20
  ARM: dts: imx6ul-tx6ul: Switch away from deprecated `phy-reset-gpios`
  ARM: dts: mba6ul: Add MicIn routing
  ARM: dts: ls1021a-tsn: Remove redundant #address-cells for ethernet-switch@1
  ...

Link: https://lore.kernel.org/r/20250915132535.253859-2-shawnguo2@yeah.net
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15 16:34:11 +02:00
Arnd Bergmann
1c615dd303 i.MX DT bindings changes for 6.18:
- New board compatibles: TQMa91xx SOM, Ultratronik Ultra-MACH SBC,
   SolidRun i.MX8MP SoM, i.MX8ULP EVK9, TQMLS1012AL, i.MX91 11x11 EVK,
   EDM-G-IMX8M-PLUS SOM
 - Update imx95-scmi firmware bindings to allow linux,code for protocol@81
 - Add i.MX53 compatible for fsl,imx-iomuxc-gpr bindings
 - Update fsl,imx7ulp-smc1 bindings to allow clocks and clock-names
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Merge tag 'imx-bindings-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt

i.MX DT bindings changes for 6.18:

- New board compatibles: TQMa91xx SOM, Ultratronik Ultra-MACH SBC,
  SolidRun i.MX8MP SoM, i.MX8ULP EVK9, TQMLS1012AL, i.MX91 11x11 EVK,
  EDM-G-IMX8M-PLUS SOM
- Update imx95-scmi firmware bindings to allow linux,code for protocol@81
- Add i.MX53 compatible for fsl,imx-iomuxc-gpr bindings
- Update fsl,imx7ulp-smc1 bindings to allow clocks and clock-names

* tag 'imx-bindings-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  dt-bindings: arm: fsl: add TQMa91xx SOM series
  dt-bindings: fsl: fsl,imx7ulp-smc1: Allow clocks and clock-names
  dt-bindings: arm: fsl: Add bindings for SolidRun i.MX8MP SoM and boards
  dt-bindings: soc: fsl,imx-iomuxc-gpr: Document i.MX53
  dt-bindings: arm: fsl: Add EDM-G-IMX8M-PLUS SOM and WB-EDM-G carrier board
  dt-bindings: firmware: imx95-scmi: Allow linux,code for protocol@81
  dt-bindings: arm: fsl: add i.MX91 11x11 evk board
  dt-bindings: arm: fsl: add TQMLS1012AL
  dt-bindings: arm: fsl: add i.MX8ULP EVK9 board
  dt-bindings: arm: imx8mp: Add Ultratronik Ultra-MACH SBC

Link: https://lore.kernel.org/r/20250915132535.253859-1-shawnguo2@yeah.net
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15 16:33:16 +02:00
Arnd Bergmann
8193017c71 i.MX defconfig changes for 6.18:
- Enable i.MX91 pinctrl driver and Marvell WiFi-Ex USB driver in arm64
   defconfig
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Merge tag 'imx-defconfig-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/defconfig

i.MX defconfig changes for 6.18:

- Enable i.MX91 pinctrl driver and Marvell WiFi-Ex USB driver in arm64
  defconfig

* tag 'imx-defconfig-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: defconfig: Enable Marvell WiFi-Ex USB driver
  arm64: defconfig: enable i.MX91 pinctrl

Link: https://lore.kernel.org/r/20250915132535.253859-4-shawnguo2@yeah.net
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15 16:32:06 +02:00
Arnd Bergmann
dc16fd9dd0 Microchip ARM64 SoC updates for v6.18:
This update includes:
 - basic infrastructure support for Microchip LAN969x SoC
 - SoC ARCH symbols (existing SparX-5, new LAN969x) under the
   ARCH_MICROCHIP hidden symbol (already in use by AT91 in 6.17)
 - addition of that new symbol for drivers that are shared by
   Microchip SoC-s now and in the future
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Merge tag 'microchip-soc-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/drivers

Microchip ARM64 SoC updates for v6.18:

This update includes:
- basic infrastructure support for Microchip LAN969x SoC
- SoC ARCH symbols (existing SparX-5, new LAN969x) under the
  ARCH_MICROCHIP hidden symbol (already in use by AT91 in 6.17)
- addition of that new symbol for drivers that are shared by
  Microchip SoC-s now and in the future

* tag 'microchip-soc-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  crypto: atmel-aes: make it selectable for ARCH_MICROCHIP
  char: hw_random: atmel: make it selectable for ARCH_MICROCHIP
  i2c: at91: make it selectable for ARCH_MICROCHIP
  spi: atmel: make it selectable for ARCH_MICROCHIP
  tty: serial: atmel: make it selectable for ARCH_MICROCHIP
  mfd: at91-usart: Make it selectable for ARCH_MICROCHIP
  arm64: lan969x: Add support for Microchip LAN969x SoC
  arm64: Add config for Microchip SoC platforms

Link: https://lore.kernel.org/r/20250915123548.13722-1-nicolas.ferre@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-09-15 16:23:42 +02:00
Shubhrajyoti Datta
d5fe2fec6c EDAC: Add a driver for the AMD Versal NET DDR controller
Add a driver for the AMD Versal NET DDR memory controller which supports
single bit error correction, double bit error detection and other system
errors from various IP subsystems (e.g., RPU, NOCs, HNICX, PL).

The driver listens for notifications from the NMC (Network management
controller) using RPMsg (Remote Processor Messaging).

The channel used for communicating to RPMsg is named "error_edac".  Upon
receipt of a notification, the driver sends a RAS event trace.

  [ bp:
    - Fixup title
    - Rewrite commit message
    - Fixup Kconfig text
    - Zap unused defines and align them
    - Simplify rpmsg_cb() considerably
    - Drop silly double-brackets in conditionals
    - Use proper void * type in mcdi_request()
    - Do not clear chinfo in rpmsg_probe() unnecessarily
    - Fix indentation
    - Do a proper err unwind path in init_versalnet()
    - Redo the error unwind path in mc_probe() properly
    - Fix the ordering in mc_remove()
    ]

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/20250908115649.22903-1-shubhrajyoti.datta@amd.com
Link: https://lore.kernel.org/r/20250703173105.GLaGa-WQCESDNsqygm@fat_crate.local
2025-09-15 16:22:27 +02:00