The argument has been unused since the function was added, so remove it.
Signed-off-by: Caleb Sander Mateos <csander@purestorage.com>
Reviewed-by: Ming Lei <ming.lei@redhat.com>
Link: https://lore.kernel.org/r/20250521160720.1893326-1-csander@purestorage.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
This enables some drivers as modules to enable fully booting
some of the supported MediaTek boards;
In particular, this enables the following drivers as module:
- PHYs for PCIe, HDMI, DSI and DisplayPort for all boards
- MediaTek UART DMA Controller, also for all boards
- MDP3 driver for MT8186/88/95 (Chromebooks and Genio variants)
- Auxiliary ADC for the MT6357/58/59 PMICs found on both Genio EVK
and Chromebooks based on designs with MT8183/86/88/92/95 SoCs
- iTE IT5205 Type-C USB Alternate Mode Passive MUX, found
on both Chromebooks and Genio EVKs with MT8188/95
- Richtek RT1715 Type-C PD Controller, found on all Genio boards
- Himax HX8279 DSI panel DriverIC and KD070FHFID015 panel, found
on various revisions of the Genio Evaluation Kit boards.
-----BEGIN PGP SIGNATURE-----
iJ4EABYKAEYWIQQn3Xxr56ypAcSHzXSaNgTPrZeEeAUCaCxpdSgcYW5nZWxvZ2lv
YWNjaGluby5kZWxyZWdub0Bjb2xsYWJvcmEuY29tAAoJEJo2BM+tl4R4+7kA/j5c
urmSN7qrFH6EWcguxQlDBIUvQebQm+4HeGC4bbHHAQCxiNrsAgzCsG4cYe8BN2Lz
uzDsHBEJIn+T/rBHFfAwDg==
=h8po
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmgvA7wACgkQmmx57+YA
GNk5LhAAwQ+3FCFBCrpxV9ohzKJ9EpHHDMrKzCjLPS6Opulszk7YMfNcamk5934+
D0FAZU5KQWv89w4UoFUB38TE8qpvHXRW6wWcqTDsFtUpzN3kXQyU/E7mzxU6Jek7
oOwVbk4tIlv+Kyy7tuvy+BufoAPs24i24su5KNdEO/8FlxggBSWml7P+Iw9uGgcF
V4ke0ojZvBKPnBSFkxCCDQ/DQBOKQkyPJT3n1vouxEHQoFhRcQchXxRsikrN4VSN
o1R38LJ4v1iX4HtXqbflfgrofBTxAPPFxjobfZFXxVBpaX50jQTC6pg/OAH2bViH
WDyAq+gEVESM2zvjyk89jyD307HojLlh/NOsL7Rdbwwx3FpAW/vAx1u/GONW9mLX
Ku7Q6gnBRAnmks4Ic40lEP+mPomDLVvaocn3xd0Gyovun8vHTszLn6rPUGYYmEMo
/wFYGCtiEPeYKxh+pX10WeGwNXUd/IN5GlyHHNIAa2eae9mSUesL0vCvIBK4dIu5
0zUz+FePuoSbyep7R+Hc9ezaqQEmTTATK3tz1G6Nnp6RPGihBUvFkUNxRa2Nrrth
RaVswHgst9xAcU8yn4Fb2WPNjPZpIuTQZteJDhDtRFFTScJs6uG9GinZeRAd5TfI
IFdQpblo/I7spI3rRtx03OxLIK8nFhAIZ0yN7OOpAiq1TCIeENs=
=GJ3+
-----END PGP SIGNATURE-----
Merge tag 'mtk-defconfig-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/defconfig
MediaTek ARM64 defconfig updates for v6.16
This enables some drivers as modules to enable fully booting
some of the supported MediaTek boards;
In particular, this enables the following drivers as module:
- PHYs for PCIe, HDMI, DSI and DisplayPort for all boards
- MediaTek UART DMA Controller, also for all boards
- MDP3 driver for MT8186/88/95 (Chromebooks and Genio variants)
- Auxiliary ADC for the MT6357/58/59 PMICs found on both Genio EVK
and Chromebooks based on designs with MT8183/86/88/92/95 SoCs
- iTE IT5205 Type-C USB Alternate Mode Passive MUX, found
on both Chromebooks and Genio EVKs with MT8188/95
- Richtek RT1715 Type-C PD Controller, found on all Genio boards
- Himax HX8279 DSI panel DriverIC and KD070FHFID015 panel, found
on various revisions of the Genio Evaluation Kit boards.
* tag 'mtk-defconfig-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
arm64: defconfig: Enable configs for MediaTek Genio EVK boards
arm64: defconfig: mediatek: enable PHY drivers
Link: https://lore.kernel.org/r/20250520114356.1194450-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
In the pci_acpi_scan_root() function, when creating a PCI bus fails,
we need to free up the previously allocated memory, which can avoid
invalid memory usage and save resources.
Fixes: 789befdfa3 ("arm64: PCI: Migrate ACPI related functions to pci-acpi.c")
Signed-off-by: Zhe Qiao <qiaozhe@iscas.ac.cn>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://lore.kernel.org/r/20250430060603.381504-1-qiaozhe@iscas.ac.cn
Enable global clock controller and TLMM pinctrl drivers for IPQ5424 to
make this boot.
-----BEGIN PGP SIGNATURE-----
iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmgr7f0VHGFuZGVyc3Nv
bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FjsgP/Rz5VWfsMwCZejAub3yHEFA/HVcy
U1JYYlNXl6BBPV8ta6LhC5AkhF8DMaKw850spzog1nDKdTdnI7jNU70ouprJW8G1
mUQa1pM/VD5KyWeF67WH9sl9p/kcHSxyxWoIfpXbZ43cvGZ+bCk8dNGS6wMJJa9h
ebjpQIFEX8tSPm+HnQuW9uExE0UJD/1zeB5f8Nr6YUv1J1P/Z1WHst2z4OY41atL
aiNh/uaAWhqad6C6JWcvrFS2+O2dY3ZbB3n8NhgDM1pW6d9gFnRXS+NaE/zc4PtN
GqSEo9wgxLJayvHfc5pp/glLqwq8G948IGVLN3aXl+ZZfsSJRnOWEwm5iHmjAQaW
kFxH4ePDpctueiiMkxeqRRxt9IzLmoVc8JrQcpsHTECAJEsTx1kqzoLzPDy+ZUeK
gbU+I1HmNRY+cIl916ShocF1MLfLgDnUimbWJg3+cfXi44EKsvvh0OHUKsePGo68
wKmQXEYM5w8oR4caQIYaARkRSwTD9MxApUZK5PLWzAXepIGUkULKFyyh65eA1jya
CL4UtI76AMVHqXpfGth7p3g4i3K6h9ZGOfb9dVKBHnsdbZmbvfo6tzg9tiD5UV52
lPvwG3dpN8/YCj85J08PYQZYDTCZ8VVZseRWFctIHf+yFyf4sQxrJwfMuMrA7bQy
gTdp2o4Ut/wxKIjC
=sw/L
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmgvA6IACgkQmmx57+YA
GNnrbA/+IXEZjtmuEV6o470/Jghi2f6GzSqQ+AXXXlayvSXspP25odjAFLjYWxwC
MTlNERTktsJb2HffClhK+0kmcKRyy09edkjsfdZI0HJ9OpDnnsd+4CsHhxNQs/IF
0Xz2/zpxsKwywlV5Av4MP7sT0YdWH8PnlwMZSczWc1cckD07zyL5drwpch7gJsSm
pJQM7MCmDdiFZKjSji8mzveBFyOCiaKHtWrqEI2ZPxhbb2jpch3qaBNJgW1rvIZa
Art4niZHoDMgSlI2RrYdXNr8oG9gayCchFy3FxhGhtqoeEZ/U2vNdHJOgAWDxLuL
1HryRst1H/1zzf3Xl/XWpz6xaa1vBQromSzREh/XlpCE48MymgujLNhBBAZM/SDP
sP2dW6Es1YL8O8BdyfKG/T61JNTj9o5aORmvAkiEtskfLc9AzPeizyfRmmHOqQru
2yqRhF+R6I5ofko9BXVOWwXKOl2sKz197iTCmxOsh1U9u3old4ea/F60yKJlAc2c
70zMmyPAXj3RBnwuo8FKFqt2v/LSVlSQbNGow+MO9mxHqtMiARG59LrlPex+pEHD
qe/i61TbXqPTzbRVDM1Q5oCoRAy2oI0RpoB/YX3CUGZQjBy191RmD95RBJPDSzMx
ONmA6BeUPGxVZoBaBsgsJNwBLhMecrDXcO8GqvpPydTpSDVFVVM=
=HAVp
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-defconfig-for-6.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/defconfig
One more Qualcomm Arm64 defconfig update for v6.16
Enable global clock controller and TLMM pinctrl drivers for IPQ5424 to
make this boot.
* tag 'qcom-arm64-defconfig-for-6.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
arm64: defconfig: Enable IPQ5424 RDP466 base configs
Link: https://lore.kernel.org/r/20250520025119.40021-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
PM_GENERIC_DOMAINS is enabled because T-Head SoCs need to use it and
spacemit's gpio and clock controller are enabled for more obvious
reasons.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCaCcUngAKCRB4tDGHoIJi
0ql4AQDUpYnIHRMVnyc9wrFl80N+ZM/up31SxVantNXs4aY6DAD/Q11CxeJB8UM4
QGsvAKvsNiySmr665PwgyUXj0SED9QQ=
=+zzo
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmgvA3gACgkQmmx57+YA
GNl8Mg//RWSc7kb88GT+f+XLvwgu0WIj0CZCh476qbHJ/Gp5hUIqMV4uJ7QETkp2
9JPGhyQteUFXk3ZpjSzctQv6fjFzKgEYeoil4ZCo4upyPyAnFu2mmyKyJ9ypYbJ/
hc5Mw/epwWX1S0bisMLW0bhRrq0ZBTAxEfKayoSynbKlE1JXjl1kYR7F+0hbTNFO
iWKJGp5VWDiq+N6ASEv/bRy1tJXPL0cjHaIuw06VRHIZgfXo+Y3RKyMxodRA+rk2
jHiPvEEeTUQBE+UUMOGESU09jOZOlF40bhMo5QLmmWOmCIeJ/mso7/FIqwPRP+ct
5lv+aiXurhxUxG6SKSEXh2jZ2mJbC3GWcyf/DpF8+ajt0aQ0blmIPve/A5tRgsLz
M2wz86Zlzb6Jvns7yYTTkQeGHAfdTxjZOHxgYJaOqgGH200elnpOGE1e5qRHJT9E
cxPNmhtqUnCIVP6jiKHdYPGqOZtDn92MJf9fPiW2MeL+xQRUtPyF2x0V/o1nefnV
xwicw1rCS21MDrc/K3Zi7zxMEQvv3oT9R0qw0fFIFP6s8o4+sRF/CNhqo8YgS6zL
Ck/BJDQEuBXU3bt0g022kTPh+N9QRu3gPsCK+RqcFRmhwU5OVanKNAx3N1rYj1d7
Jo8whaTm2nvBD/vxwdmMhSkZDQbfsBnC5iD4bPiSh/W5cnh1QeY=
=Xv8S
-----END PGP SIGNATURE-----
Merge tag 'riscv-config-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/defconfig
RISC-V config for v6.16
PM_GENERIC_DOMAINS is enabled because T-Head SoCs need to use it and
spacemit's gpio and clock controller are enabled for more obvious
reasons.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-config-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: defconfig: spacemit: enable clock controller driver for SpacemiT K1
riscv: defconfig: spacemit: enable gpio support for K1 SoC
riscv: Enable PM_GENERIC_DOMAINS for T-Head SoCs
Link: https://lore.kernel.org/r/20250516-joystick-mortified-385820b1ad0b@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
One variant of MT7992 has 5 TX paths, so extend the power delta function
to support it. Also, rename nss_delta to path_delta since the value is
based on the number of TX paths rather tha the number of spatial streams.
(path delta [0.5 dBm] = 10 * log(path number) [dBm] * 2)
Co-developed-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com>
Signed-off-by: StanleyYP Wang <StanleyYP.Wang@mediatek.com>
Signed-off-by: Shayne Chen <shayne.chen@mediatek.com>
Link: https://patch.msgid.link/20250515032952.1653494-9-shayne.chen@mediatek.com
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Check if available_antennas_tx and available_antennas_rx are already set
during the per-chip initialization phase; otherwise, they could be
overwritten with incorrect values.
Fixes: 69d54ce749 ("wifi: mt76: mt7996: switch to single multi-radio wiphy")
Signed-off-by: Shayne Chen <shayne.chen@mediatek.com>
Link: https://patch.msgid.link/20250515032952.1653494-8-shayne.chen@mediatek.com
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Some management frames are first processed by the firmware and then
passed to the driver through the MCU event rings. In CONNAC3, event rings
do not support scatter-gather and have a size limitation of 2048 bytes.
If a packet sized between 1728 and 2048 bytes arrives from an event ring,
the ring will hang because the driver attempts to use scatter-gather to
process it.
To fix this, include the size of struct skb_shared_info in the MCU RX
buffer size to prevent scatter-gather from being used for event skb in
mt76_dma_rx_fill_buf().
Fixes: 98686cd216 ("wifi: mt76: mt7996: add driver for MediaTek Wi-Fi 7 (802.11be) devices")
Co-developed-by: Peter Chiu <chui-hao.chiu@mediatek.com>
Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com>
Signed-off-by: Shayne Chen <shayne.chen@mediatek.com>
Link: https://patch.msgid.link/20250515032952.1653494-7-shayne.chen@mediatek.com
Signed-off-by: Felix Fietkau <nbd@nbd.name>
According to hardware capability, the maximum beacon size is 2048 bytes
minus the size of TLV headers.
Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com>
Signed-off-by: Shayne Chen <shayne.chen@mediatek.com>
Link: https://patch.msgid.link/20250515032952.1653494-6-shayne.chen@mediatek.com
Signed-off-by: Felix Fietkau <nbd@nbd.name>
The maximum TX path and NSS may differ on a band. For example, one variant
of the MT7992 has 5 TX paths and 4 NSS on the 5 GHz band. To address this,
add orig_antenna_mask to record the maximum NSS and prevent setting an
invalid NSS in mt7996_set_antenna().
Fixes: 69d54ce749 ("wifi: mt76: mt7996: switch to single multi-radio wiphy")
Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com>
Signed-off-by: Shayne Chen <shayne.chen@mediatek.com>
Link: https://patch.msgid.link/20250515032952.1653494-5-shayne.chen@mediatek.com
Signed-off-by: Felix Fietkau <nbd@nbd.name>
IEEE 802.11 fragmentation can only be applied to unicast frames.
Therefore, drop fragments with multicast or broadcast RA. This patch
addresses vulnerabilities such as CVE-2020-26145.
Signed-off-by: Benjamin Lin <benjamin-jw.lin@mediatek.com>
Signed-off-by: Shayne Chen <shayne.chen@mediatek.com>
Link: https://patch.msgid.link/20250515032952.1653494-4-shayne.chen@mediatek.com
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Set the max AMPDU length in the EHT MAC CAP. Without this patch, the
peer station cannot obtain the correct capability, which prevents
achieving peak throughput on the 2 GHz band.
Fixes: 1816ad9381 ("wifi: mt76: mt7996: add max mpdu len capability")
Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com>
Signed-off-by: Shayne Chen <shayne.chen@mediatek.com>
Link: https://patch.msgid.link/20250515032952.1653494-3-shayne.chen@mediatek.com
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Fix the beamformee SS field for the mt7996, mt7992 and mt7990 chipsets.
For the mt7992, this value shall be set to 0x4, while the others shall
be set to 0x3.
Fixes: 5b20557593 ("wifi: mt76: connac: adjust phy capabilities based on band constraints")
Signed-off-by: Howard Hsu <howard-yh.hsu@mediatek.com>
Signed-off-by: Shayne Chen <shayne.chen@mediatek.com>
Link: https://patch.msgid.link/20250515032952.1653494-2-shayne.chen@mediatek.com
Signed-off-by: Felix Fietkau <nbd@nbd.name>
The firmware only supports full bandwidth UL MU-MIMO, so remove the
partial bandwidth capability from HE PHY CAP.
Signed-off-by: Howard Hsu <howard-yh.hsu@mediatek.com>
Signed-off-by: Shayne Chen <shayne.chen@mediatek.com>
Link: https://patch.msgid.link/20250515032952.1653494-1-shayne.chen@mediatek.com
Signed-off-by: Felix Fietkau <nbd@nbd.name>
The test mode interface allows controlled execution of chip-level
operations such as continuous transmission, reception tests, and
register access, which are essential during bring-up, diagnostics,
and factory testing.
Co-developed-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Michael Lo <michael.lo@mediatek.com>
Link: https://patch.msgid.link/20250505233618.1951021-2-sean.wang@kernel.org
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Add MCU command and its handling needed for testmode support on
MT7925. This enables low-level chip testing features such as
continuous TX/RX..
Co-developed-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Michael Lo <michael.lo@mediatek.com>
Link: https://patch.msgid.link/20250505233618.1951021-1-sean.wang@kernel.org
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Modify MCU command sending functions to wait for a response,
ensuring consistent behavior across all commands and improves
reliability by confirming that each command is processed
successfully.
Fixes: c948b5da6b ("wifi: mt76: mt7925: add Mediatek Wi-Fi7 driver for mt7925 chips")
Signed-off-by: Michael Lo <michael.lo@mediatek.com>
Signed-off-by: Ming Yen Hsieh <mingyen.hsieh@mediatek.com>
Link: https://patch.msgid.link/20250414013954.1151774-3-mingyen.hsieh@mediatek.com
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Remove a duplicate call to `mt76_mcu_send_msg` to fix redundant operations
in the sniffer command handling.
Fixes: c948b5da6b ("wifi: mt76: mt7925: add Mediatek Wi-Fi7 driver for mt7925 chips")
Signed-off-by: Ming Yen Hsieh <mingyen.hsieh@mediatek.com>
Link: https://patch.msgid.link/20250414013954.1151774-2-mingyen.hsieh@mediatek.com
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Add a check to ensure only one scan command is active at a time
by testing the MT76_HW_SCANNING state.
Fixes: c948b5da6b ("wifi: mt76: mt7925: add Mediatek Wi-Fi7 driver for mt7925 chips")
Signed-off-by: Ming Yen Hsieh <mingyen.hsieh@mediatek.com>
Link: https://patch.msgid.link/20250414013954.1151774-1-mingyen.hsieh@mediatek.com
Signed-off-by: Felix Fietkau <nbd@nbd.name>
devm_ioremap() returns NULL on error. Currently, mt7915_mmio_wed_init()
does not check for this case, which results in a NULL pointer
dereference.
Prevent null pointer dereference in mt7915_mmio_wed_init().
Fixes: 4f831d18d1 ("wifi: mt76: mt7915: enable WED RX support")
Signed-off-by: Henry Martin <bsdhenrymartin@gmail.com>
Link: https://patch.msgid.link/20250407061900.85317-1-bsdhenrymartin@gmail.com
Signed-off-by: Felix Fietkau <nbd@nbd.name>
devm_ioremap() returns NULL on error. Currently, mt7996_mmio_wed_init()
does not check for this case, which results in a NULL pointer
dereference.
Prevent null pointer dereference in mt7996_mmio_wed_init()
Fixes: 83eafc9251 ("wifi: mt76: mt7996: add wed tx support")
Signed-off-by: Henry Martin <bsdhenrymartin@gmail.com>
Link: https://patch.msgid.link/20250407032349.83360-1-bsdhenrymartin@gmail.com
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Introduce mt76_connac_mcu_build_rnr_scan_param routine for handling
RNR scan. This is a preliminary patch to enable RNR scan in mt7921 and
mt7925 driver.
Signed-off-by: Ming Yen Hsieh <mingyen.hsieh@mediatek.com>
Link: https://patch.msgid.link/20250321013829.3598-1-mingyen.hsieh@mediatek.com
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Few updates to the Arm FVP(Fixed Virtual Platform) device tree, enhancing
support for system tracing, power management, and firmware coexistence:
1. ETE and TRBE support
Adds CoreSight ETE and TRBE nodes for the FVP Rev C model. These are
disabled by default as they need to be enabled explicitly via model
parameters.
2. CPU idle states and system timer for idle broadcast
Introduces CPU idle state definitions but disabled by default due to
potential performance impact on the model. Also adds a system-level
broadcast timer for use when CPUs enter deep idle states where local
timers stop.
3. Firmware memory reservation
Reserves 64MB at the end of the first DRAM bank to prevent conflicts
with FF-A firmware or similar configurations that rely on this region.
4. Drop the unnecessary clock-frequency property in the timer nodes
The boot/secure firmware must configure the timer clock frequency and
the non-secure OS must be able to read the same. The clock-frequency is
generally used when the firmware is broken which is not the case on
most of the fast models and Juno platform.
As noted above some of the changes are disabled by default where applicable
to ensure backward compatibility and avoid unintended performance impact
on platforms using default model parameters.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAmgiNcUACgkQAEG6vDF+
4pi4pA/9EoZFtzrkCmdEYvXeXwe8rkxUukR+kt8inwbZ1ES+BnaAop4qBWDfTQt/
0d2B3jWy5PBtVSqmSVOnqJromiKMwvWCrmg7bHMz8yMaP8xGduuAcOpUgqX5eXmo
VO/F3as9BXVYGQBSn4JqpHTpp7Y5WJBYVV+N8CZDABQXfMafDEXAxqiBEXGoTaiZ
lECMNzTo5WLnRUL4PrZjIxSGoeh2NApPzoBi5V02G6lWa2Do1WsnKS6/wYAwiSlz
rGkpCYp8g1qA+KxxOh9QUiUOPOndk8NwWH/ldgIUCYOR7C1tTp1ICBvhLNqbA596
pv58Y8MYjX9R22n/MHGjzIXLVxWGm8b7HclDzwMNYt0pWdRrtSRIuf5ltdsbEW4S
wlT5FuVrYUiLeLpGi77hqTlyHaAFS1e+wZJwEu1jcgUW73WAJnh+t6UPRfGtGf4L
yXrVqEZQmABmX/IhYrpe6v623n+gS4qfxzM7Vz5TpzzApY057qbngD2d+ZUFpryt
JuhRLl+pCo/EfMhrYap1QptxLc2Mjh+NkCnlN8D/ExpBevWxEY6vwRIagrmbD1km
lO0T6QWpevahU4Wfl/tiyExW3ciE52RhQ2PlgX30edQKXlZZu5s2RISNYzXRCHmt
cOiU6jVo2HE6iqxXhLgwYycl5rLWJl3FcJmNlXSkBxLWZYHrN10=
=dPTB
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmgvArUACgkQmmx57+YA
GNm4phAAoGrzPSjTSEThKNdD2p9PZ5ZL87b2zcI/SD+DVMsppv8AyOPL36u1YOUE
eianNg/oYOlbGufN2hJyaZJ5it6Zm9vo9GblvBwq5ICc0ogY5uaMqaLUhsRddT5x
FQwv7sWXDtbJRkFYDkiUpNx+a9p82tia8mb941R6EMCjoS5U/h6is5s52P53i/WX
5UUAAbvtkiBV874P8RIbOXnZUEohYvrhs2UKW8pCUbPt7hU7SzDl8dpljNqFxBFF
ZmQfJFCLulfJ1ObfxTu5Ixu6rDJnyDzAYyMXYXHBwzpYZbdDcvBOYKn6kCQMP70C
6MJJvuQCsDy5TL5j19rrGP9EPO0fyLF4BP5giMBmZOUMTbcuJyhkzWucT4cPXeDB
h4XAjPNa6oqeJ3wd+Ak5uxq/J73iLjdTfnahZLWCz5Q5mGfXBvicTWJY+ylqPys9
sJdiVZZGdY287GzKrLKClL7ee9urdqazVdB/3WQUwK8pSJ+5OgC1DJzs0w1VRmgE
HM615IOKKmM5amjJLJbCr370s6OtNQNThZWOJbIVv1YlyTyLaqFglIccGCGdRUfs
h7ptiq+HwRUs7mrGGGOIETyk2tc/OcesDm+BHtTXxZWO76O8uC1mvTDUp810XPnj
8myhcVslEjH+mR0SIbs+m8PNMgAo1l0YyN1YjgINpVbUx0WkiJM=
=oTg4
-----END PGP SIGNATURE-----
Merge tag 'juno-updates-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt
Armv8 Juno/FVP updates for v6.16
Few updates to the Arm FVP(Fixed Virtual Platform) device tree, enhancing
support for system tracing, power management, and firmware coexistence:
1. ETE and TRBE support
Adds CoreSight ETE and TRBE nodes for the FVP Rev C model. These are
disabled by default as they need to be enabled explicitly via model
parameters.
2. CPU idle states and system timer for idle broadcast
Introduces CPU idle state definitions but disabled by default due to
potential performance impact on the model. Also adds a system-level
broadcast timer for use when CPUs enter deep idle states where local
timers stop.
3. Firmware memory reservation
Reserves 64MB at the end of the first DRAM bank to prevent conflicts
with FF-A firmware or similar configurations that rely on this region.
4. Drop the unnecessary clock-frequency property in the timer nodes
The boot/secure firmware must configure the timer clock frequency and
the non-secure OS must be able to read the same. The clock-frequency is
generally used when the firmware is broken which is not the case on
most of the fast models and Juno platform.
As noted above some of the changes are disabled by default where applicable
to ensure backward compatibility and avoid unintended performance impact
on platforms using default model parameters.
* tag 'juno-updates-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: fvp: Add ETE and TRBE nodes for Rev C model
arm64: dts: arm: Drop the clock-frequency property from timer nodes
arm64: dts: fvp: Reserve 64MB for the FF-A firmware in memory map
arm64: dts: fvp: Add CPU idle states for Rev C model
arm64: dts: fvp: Add system timer for broadcast during CPU idle
Link: https://lore.kernel.org/r/20250513143827.3606686-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The subsystem-internal header pci.h still contains the function
prototype of pcim_intx(), which has since been made public in the global
header.
Remove the redundant function prototype.
Signed-off-by: Philipp Stanner <phasta@kernel.org>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20250522084626.150148-2-phasta@kernel.org
-----BEGIN PGP SIGNATURE-----
iQFHBAABCgAxFiEEn/sM2K9nqF/8FWzzDHRl3/mQkZwFAmgtivcTHG1rbEBwZW5n
dXRyb25peC5kZQAKCRAMdGXf+ZCRnHdfB/9xpi2QMYgjWn5CWHaRT5JAt1BTVTAW
g7W1iddSkw18T/+FalxSjYPZKoE+6k2AcI/VTLbjEnv4bOPlmE48dItB8WsQnwHc
1Jjbvc861HTYL51UuYH3oqXH4MrY2BiPk2aoCOuT7vPDsn/PISbfIZ41eBK3noTS
TCY3DLV7u6tnureaCqGnl2M9lBfgF86rtn+d5vza2IFDu49b2J+Cv41CRkEIbP9P
kujiCAxStN+neCKd1LtZgFbmfy63xUujPtZR2h0oYiOK9X/Nz2bjmFu40zyC+vCn
z9P0oSXx2yaJCHiDrdzMM1McHhdpU4rNjVlYMKFQBNy/WfEvFHt+Eydy
=dV2M
-----END PGP SIGNATURE-----
Merge tag 'linux-can-fixes-for-6.15-20250521' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can
Marc Kleine-Budde says:
====================
pull-request: can 2025-05-22
this is a pull request of 4 patches for net/main.
The first 3 patches are by Axel Forsman and fix a ISR race condition
in the kvaser_pciefd driver.
The last patch is by Carlos Sanchez and fixes the reception of short
error messages in the slcan driver.
* tag 'linux-can-fixes-for-6.15-20250521' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can:
can: slcan: allow reception of short error messages
can: kvaser_pciefd: Continue parsing DMA buf after dropped RX
can: kvaser_pciefd: Fix echo_skb race
can: kvaser_pciefd: Force IRQ edge in case of nested IRQ
====================
Link: https://patch.msgid.link/20250522082344.490913-1-mkl@pengutronix.de
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Commit 5b39db6037 ("arm64: el2_setup.h: Rename some labels to be more
diff-friendly") reworked the labels in __init_el2_fgt to say what's
skipped rather than what the target location is. The exception was
"set_fgt_" which is where registers are written. In reviewing the BRBE
additions, Will suggested "set_debug_fgt_" where HDFGxTR_EL2 are
written. Doing that would partially revert commit 5b39db6037 undoing
the goal of minimizing additions here, but it would follow the
convention for labels where registers are written.
So let's do both. Branches that skip something go to a "skip" label and
places that set registers have a "set" label. This results in some
double labels, but it makes things entirely consistent.
While we're here, the SME skip label was incorrectly named, so fix it.
Reported-by: Will Deacon <will@kernel.org>
Cc: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250520-arm-brbe-v19-v22-2-c1ddde38e7f8@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Geetha sowjanya says:
====================
octeontx2-af: APR Mapping Fixes
This patch series includes fixes related to APR (LMT)
mapping and debugfs support.
Changes include:
Patch 1:Set LMT_ENA bit for APR table entries.
Enables the LMT line for each PF/VF by setting
the LMT_ENA bit in the APR_LMT_MAP_ENTRY_S
structure.
Patch-2:Fix APR entry in debugfs
The APR table was previously mapped using a fixed size,
which could lead to incorrect mappings when the number
of PFs and VFs differed from the assumed value.
This patch updates the logic to calculate the APR table
size dynamically, based on values from the APR_LMT_CFG
register, ensuring correct representation in debugfs.
====================
Link: https://patch.msgid.link/20250521060834.19780-1-gakula@marvell.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
The current implementation maps the APR table using a fixed size,
which can lead to incorrect mapping when the number of PFs and VFs
varies.
This patch corrects the mapping by calculating the APR table
size dynamically based on the values configured in the
APR_LMT_CFG register, ensuring accurate representation
of APR entries in debugfs.
Fixes: 0daa55d033 ("octeontx2-af: cn10k: debugfs for dumping LMTST map table").
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Link: https://patch.msgid.link/20250521060834.19780-3-gakula@marvell.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This patch enables the LMT line for a PF/VF by setting the
LMT_ENA bit in the APR_LMT_MAP_ENTRY_S structure.
Additionally, it simplifies the logic for calculating the
LMTST table index by consistently using the maximum
number of hw supported VFs (i.e., 256).
Fixes: 873a1e3d20 ("octeontx2-af: cn10k: Setting up lmtst map table").
Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com>
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Reviewed-by: Michal Swiatkowski <michal.swiatkowski@linux.intel.com>
Link: https://patch.msgid.link/20250521060834.19780-2-gakula@marvell.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
The post-migration recovery needs to be fully implemented for a
specific platform in order to make continuation of workloads
possible.
New platforms introduce changes which affect the recovery procedure,
and without a clear verification of support this leads to errors
with no straight forward error message explaining the cause.
This patch fixes that issue - it introduces a message to be logged
when the current driver is known to not support the current platform.
Wedging the driver immediately also decreases the amount of
additional errors which would come afterwards if the driver continued
operation.
v2: Show the message during probe as well as during recovery; do not
perform any recovery steps if the recovery is bound to fail
v3: Use SRIOV-specific logging, fix typos
v4: XE_DEBUG_SRIOV to XE_DEBUG check switch, to make testing more
straightforward
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Acked-by: Michał Winiarski <michal.winiarski@intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Link: https://lore.kernel.org/r/20250519230035.3143966-1-tomasz.lis@intel.com
Add Tegra264 AHUB support with following changes:
- Update Tegra264 IP instances: DMIC(2), DSPK(1), AMX(6), ADX(6), I2S(8).
- Update register offsets for Tegra264.
- Add soc_data for Tegra264 chip-specific variations.
- Increase channels_max to 32 for Tegra264 DAIs.
Signed-off-by: Sheetal <sheetal@nvidia.com>
Link: https://patch.msgid.link/20250512051747.1026770-11-sheetal@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Add Tegra264 ADX support with following changes:
- Add soc_data for Tegra264-specific variations
- Tegra264 ADX supports 32 input channels, hence update the playback DAI
channels_max parameter and CIF configuration API.
- Register offsets and default values are updated to align with Tegra264.
- Add 128 byte map controls for Tegra264 to accommodate each byte per
channel (32channels x 32bits).
Signed-off-by: Sheetal <sheetal@nvidia.com>
Link: https://patch.msgid.link/20250512051747.1026770-10-sheetal@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Add Tegra264 AMX support with following changes:
- Add soc_data for Tegra264-specific variations
- Tegra264 AMX supports 32 output channels, hence update the capture DAI
channels_max parameter and CIF configuration API.
- Register offsets and default values are updated to align with Tegra264.
- Add 128 byte map controls for Tegra264 to accommodate each byte per
channel (32channels x 32bits).
Signed-off-by: Sheetal <sheetal@nvidia.com>
Link: https://patch.msgid.link/20250512051747.1026770-9-sheetal@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Add Tegra264 I2S support with following changes:
- Add soc_data for Tegra264-specific variations
- Tegra264 I2S supports 32 audio channels, hence update the TDM config,
CIF configuration API and DAI channel_max parameter.
- Register offsets and default values are updated to align with Tegra264.
Signed-off-by: Sheetal <sheetal@nvidia.com>
Link: https://patch.msgid.link/20250512051747.1026770-8-sheetal@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
The PLLs should be set with a VCO frequency in the 900MHz – 1GHz range
to minimize jitter and ppm error for Tegra264. Add the PLLA rate
accordingly.
Therefore, use 983040000 frequency is for multiple of 8K frequencies
and 993484800 frequency is for multiple of 11.025K frequencies.
Signed-off-by: Sheetal <sheetal@nvidia.com>
Link: https://patch.msgid.link/20250512051747.1026770-7-sheetal@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
The ARAM address for Tegra264 has been updated. To maintain backward
compatibility given its chip-specific nature, it's now included in the
soc_data.
Signed-off-by: Sheetal <sheetal@nvidia.com>
Link: https://patch.msgid.link/20250512051747.1026770-6-sheetal@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Add Tegra264 I2S support with following changes:
- Add soc_data for Tegra264-specific variations
- Tegra264 supports 32 RX and 32 TX ADMAIF channels and each ADMAIF
stream supports max 32 channels. To accommodate the change dais, CIF
configuration API and driver components are updated.
- Register offsets and default values are updated to align with Tegra264.
Signed-off-by: Sheetal <sheetal@nvidia.com>
Link: https://patch.msgid.link/20250512051747.1026770-5-sheetal@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
In Tegra264, the CIF register data bit positions are changed for I2S,
AMX, ADX and ADMAIF AHUB modules, as they now support a maximum of
32 channels. tegra264_set_cif API added to set the CIF for IPs supporting
32 channels.
Signed-off-by: Sheetal <sheetal@nvidia.com>
Link: https://patch.msgid.link/20250512051747.1026770-4-sheetal@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Add Tegra264 compatible strings to APE subsystem device bindings:
- audio-graph-card: Due to different PLL clock rate.
- admaif: Due to 32 channels supported and register offset changes.
- i2s: Due to 32 channels supported and register offset changes.
- amx/adx: Due to 32 channels supported and register offset changes.
- asrc: Due to different ARAM address.
- ahub: Due to AHUB IPs number of instances updates.
- for future proofing the T264 compatibility is added for other device
nodes.
These bindings enable the enhanced audio features of Tegra264
while maintaining compatibility with existing platforms.
Signed-off-by: Sheetal <sheetal@nvidia.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20250512051747.1026770-3-sheetal@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Add optional interconnect and iommu properties to admaif yaml. These
properties are supported from Tegra186 SoC onwards.
This fixes below dtbs_check error for Tegra194 and Tegra234:
'interconnect-names', 'interconnects', 'iommus' do not match any of the regexes: 'pinctrl-[0-9]+'
Signed-off-by: Sheetal <sheetal@nvidia.com>
Acked-by: "Rob Herring (Arm)" <robh@kernel.org>
Link: https://patch.msgid.link/20250512051747.1026770-2-sheetal@nvidia.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Developers are indeed hitting other of the `noreturn` slice symbols in
Nova [1], thus relax the last check in the list so that we catch all of
them, i.e.
*_4core5slice5index22slice_index_order_fail
*_4core5slice5index24slice_end_index_len_fail
*_4core5slice5index26slice_start_index_len_fail
*_4core5slice5index29slice_end_index_overflow_fail
*_4core5slice5index31slice_start_index_overflow_fail
These all exist since at least Rust 1.78.0, thus backport it too.
See commit 56d680dd23 ("objtool/rust: list `noreturn` Rust functions")
for more details.
Cc: stable@vger.kernel.org # Needed in 6.12.y and later.
Cc: John Hubbard <jhubbard@nvidia.com>
Cc: Timur Tabi <ttabi@nvidia.com>
Cc: Kane York <kanepyork@gmail.com>
Cc: Josh Poimboeuf <jpoimboe@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Reported-by: Joel Fernandes <joelagnelf@nvidia.com>
Fixes: 56d680dd23 ("objtool/rust: list `noreturn` Rust functions")
Closes: https://lore.kernel.org/rust-for-linux/20250513180757.GA1295002@joelnvbox/ [1]
Tested-by: Joel Fernandes <joelagnelf@nvidia.com>
Link: https://lore.kernel.org/r/20250520185555.825242-1-ojeda@kernel.org
Signed-off-by: Miguel Ojeda <ojeda@kernel.org>
Add basic examples for the structure "List", which also serve as unit
tests for basic list methods. It includes the following manipulations:
* List creation
* List emptiness check
* List insertion through push_front(), push_back()
* List item removal through pop_front(), pop_back()
* Push one list to another through push_all_back()
The method "remove()" doesn't have an example here because insertion
with push_front() or push_back() will take the ownership of the item,
which means we can't keep any valid reference to the node we want to
remove, unless Cursor is used. The "remove" example through Cursor is
already demonstrated with commit 52ae96f518 ("rust: list: make the
cursor point between elements").
Link: https://github.com/Rust-for-Linux/linux/issues/1121
Signed-off-by: I Hsin Cheng <richard120310@gmail.com>
Reviewed-by: Alice Ryhl <aliceryhl@google.com>
Reviewed-by: Benno Lossin <lossin@kernel.org>
Link: https://lore.kernel.org/r/20250311133357.90322-1-richard120310@gmail.com
[ Removed prelude import and spurious newlines. Formatted comments
with the usual style. Reworded slightly. - Miguel ]
Signed-off-by: Miguel Ojeda <ojeda@kernel.org>
"List::is_empty()" provides a straight forward convention to check
whether a given "List" is empty or not. There're numerous places in the
current implementation still use "self.first.is_null()" to perform the
equivalent check, replace them with "List::is_empty()".
Signed-off-by: I Hsin Cheng <richard120310@gmail.com>
Link: https://lore.kernel.org/r/20250310073853.427954-1-richard120310@gmail.com
Reviewed-by: Benno Lossin <lossin@kernel.org>
[ Rebased dropping the cases that do not apply anymore. - Miguel ]
Signed-off-by: Miguel Ojeda <ojeda@kernel.org>
Commit 5164553d73 ("drm/bridge: add devm_drm_put_bridge()") adds two
declarations for devm_drm_put_bridge():
1) an inline declaration in the #else branch of
'#if defined(CONFIG_OF)...'
2) one outside of the same #if
This results in a build failure with CONFIG_OF=n:
../drivers/gpu/drm/drm_bridge.c:1406:6: error: redefinition of ‘devm_drm_put_bridge’
The function has nothing to do with OF, thus fix by removing declaration 1.
Fixes: 5164553d73 ("drm/bridge: add devm_drm_put_bridge()")
Reported-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Closes: https://oftc.catirclogs.org/dri-devel/2025-05-21#34288266;
Tested-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://lore.kernel.org/r/20250522-devm_drm_put_bridge-fix-non-of-build-v1-1-a05234dea046@bootlin.com
Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
The BCM59056 and BCM59054 are very similar in terms of regulators. Add
the register definitions for the BCM59054 and enable support for it in
the driver.
Signed-off-by: Artur Weber <aweber.kernel@gmail.com>
Reviewed-by: Stanislav Jakubek <stano.jakubek@gmail.com>
Reviewed-by: Mark Brown <brooni@kernel.org>
Link: https://lore.kernel.org/r/20250515-bcm59054-v9-8-14ba0ea2ea5b@gmail.com
Signed-off-by: Lee Jones <lee@kernel.org>
