In configurations with CONFIG_TICK_ONESHOT but no CONFIG_NO_HZ or
CONFIG_HIGH_RES_TIMERS, tick_sched_timer_dying() is stubbed out,
but still defined as a global function as well:
kernel/time/tick-sched.c:1599:6: error: redefinition of 'tick_sched_timer_dying'
1599 | void tick_sched_timer_dying(int cpu)
| ^
kernel/time/tick-sched.h:111:20: note: previous definition is here
111 | static inline void tick_sched_timer_dying(int cpu) { }
| ^
This configuration only appears with ARM CONFIG_ARCH_BCM_MOBILE,
which should not actually select CONFIG_TICK_ONESHOT.
Adjust the #ifdef for the stub to match the condition for building the
tick-sched.c file for consistency with the definition and to avoid
the build regression.
Fixes: 3aedb7fcd8 ("tick/sched: Remove useless oneshot ifdeffery")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20240228123850.3499024-1-arnd@kernel.org
Even if the roll forward recovery stopped due to any error, we have to fix
the write pointers in order to mount the disk from the previous checkpoint.
Reviewed-by: Chao Yu <chao@kernel.org>
Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
In cfd66bb715 ("f2fs: fix deadloop in foreground GC"), we needed to check
the number of blocks in a section instead of the segment.
Fixes: cfd66bb715 ("f2fs: fix deadloop in foreground GC")
Reviewed-by: Chao Yu <chao@kernel.org>
Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
Don't get stuck in the f2fs_gc loop while disabling checkpoint. Instead, we have
a time-based management.
Reviewed-by: Chao Yu <chao@kernel.org>
Reviewed-by: Daeho Jeong <daehojeong@google.com>
Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
Use it to simulate no free segment case during block allocation.
Signed-off-by: Chao Yu <chao@kernel.org>
Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
It needs to check compress flag w/ .i_sem lock, otherwise, compressed
inode may be disabled after the check condition, it's not needed to
set compress option on non-compress inode.
Fixes: e1e8debec6 ("f2fs: add F2FS_IOC_SET_COMPRESS_OPTION ioctl")
Signed-off-by: Chao Yu <chao@kernel.org>
Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
If CONFIG_F2FS_CHECK_FS is off, and for very rare corner case that
we run out of free segment, we should not panic kernel, instead,
let's handle such error correctly in its caller.
Signed-off-by: Chao Yu <chao@kernel.org>
Tested-by: Zhiguo Niu <zhiguo.niu@unisoc.com>
Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
There is low probability that an out-of-bounds segment will be got
on a small-capacity device. In order to prevent subsequent write requests
allocating block address from this invalid segment, which may cause
unexpected issue, stop checkpoint should be performed.
Also introduce a new stop cp reason: STOP_CP_REASON_NO_SEGMENT.
Note, f2fs_stop_checkpoint(, false) is complex and it may sleep, so we should
move it outside segmap_lock spinlock coverage in get_new_segment().
Signed-off-by: Zhiguo Niu <zhiguo.niu@unisoc.com>
Reviewed-by: Chao Yu <chao@kernel.org>
Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
Commit 093749e296 ("f2fs: support age threshold based garbage
collection") added this declaration, but w/ definition, delete
it.
Signed-off-by: Chao Yu <chao@kernel.org>
Signed-off-by: Jaegeuk Kim <jaegeuk@kernel.org>
It's possible that mtk_crtc->event is NULL in
mtk_drm_crtc_finish_page_flip().
pending_needs_vblank value is set by mtk_crtc->event, but in
mtk_drm_crtc_atomic_flush(), it's is not guarded by the same
lock in mtk_drm_finish_page_flip(), thus a race condition happens.
Consider the following case:
CPU1 CPU2
step 1:
mtk_drm_crtc_atomic_begin()
mtk_crtc->event is not null,
step 1:
mtk_drm_crtc_atomic_flush:
mtk_drm_crtc_update_config(
!!mtk_crtc->event)
step 2:
mtk_crtc_ddp_irq ->
mtk_drm_finish_page_flip:
lock
mtk_crtc->event set to null,
pending_needs_vblank set to false
unlock
pending_needs_vblank set to true,
step 2:
mtk_crtc_ddp_irq ->
mtk_drm_finish_page_flip called again,
pending_needs_vblank is still true
//null pointer
Instead of guarding the entire mtk_drm_crtc_atomic_flush(), it's more
efficient to just check if mtk_crtc->event is null before use.
Fixes: 119f517362 ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Link: https://patchwork.kernel.org/project/dri-devel/patch/20240223212404.3709690-1-hsinyi@chromium.org/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Move rxrpc_send_ACK() to output.c to so that it is with
rxrpc_send_ack_packet() prior to merging the two.
Signed-off-by: David Howells <dhowells@redhat.com>
cc: Marc Dionne <marc.dionne@auristor.com>
cc: "David S. Miller" <davem@davemloft.net>
cc: Eric Dumazet <edumazet@google.com>
cc: Jakub Kicinski <kuba@kernel.org>
cc: Paolo Abeni <pabeni@redhat.com>
cc: linux-afs@lists.infradead.org
cc: netdev@vger.kernel.org
Don't pick values out of the wire header in rxkad when setting up DATA
packet security, but rather use other sources. This makes it easier to get
rid of txb->wire.
Signed-off-by: David Howells <dhowells@redhat.com>
cc: Marc Dionne <marc.dionne@auristor.com>
cc: "David S. Miller" <davem@davemloft.net>
cc: Eric Dumazet <edumazet@google.com>
cc: Jakub Kicinski <kuba@kernel.org>
cc: Paolo Abeni <pabeni@redhat.com>
cc: linux-afs@lists.infradead.org
cc: netdev@vger.kernel.org
Split (sub)packet preparation and timestamping out of the DATA packet
transmission function to make it easier to glue multiple txbufs together
into a jumbo DATA packet. This will require preparation and timestamping
of all the subpackets in a txbuf, and these functions provide convenient
points to place the required iteration.
Signed-off-by: David Howells <dhowells@redhat.com>
cc: Marc Dionne <marc.dionne@auristor.com>
cc: "David S. Miller" <davem@davemloft.net>
cc: Eric Dumazet <edumazet@google.com>
cc: Jakub Kicinski <kuba@kernel.org>
cc: Paolo Abeni <pabeni@redhat.com>
cc: linux-afs@lists.infradead.org
cc: netdev@vger.kernel.org
Add a kvec[] to the rxrpc_txbuf struct to point to the contributory buffers
for a packet. Start with just a single element for now, but this will be
expanded later.
Make the ACK sending function use it, which means that rxrpc_fill_out_ack()
doesn't need to return the size of the sack table, padding and trailer.
Make the data sending code use it, both in where sendmsg() packages code up
into txbufs and where those txbufs are transmitted.
Signed-off-by: David Howells <dhowells@redhat.com>
cc: Marc Dionne <marc.dionne@auristor.com>
cc: "David S. Miller" <davem@davemloft.net>
cc: Eric Dumazet <edumazet@google.com>
cc: Jakub Kicinski <kuba@kernel.org>
cc: Paolo Abeni <pabeni@redhat.com>
cc: linux-afs@lists.infradead.org
cc: netdev@vger.kernel.org
Merge together the DF and non-DF branches of the transmission function and
always set the flag to the right thing before transmitting. If we see
-EMSGSIZE from udp_sendmsg(), turn off DF and retry.
Signed-off-by: David Howells <dhowells@redhat.com>
cc: Marc Dionne <marc.dionne@auristor.com>
cc: "David S. Miller" <davem@davemloft.net>
cc: Eric Dumazet <edumazet@google.com>
cc: Jakub Kicinski <kuba@kernel.org>
cc: Paolo Abeni <pabeni@redhat.com>
cc: linux-afs@lists.infradead.org
cc: netdev@vger.kernel.org
Don't reset the DF flag after transmission, but rather set it when needed
since it should be a fast op now that we call IP directly.
This includes turning it off for RESPONSE packets and, for the moment, ACK
packets. In future, we will need to turn it on for ACK packets used to do
path MTU discovery.
Signed-off-by: David Howells <dhowells@redhat.com>
cc: Marc Dionne <marc.dionne@auristor.com>
cc: "David S. Miller" <davem@davemloft.net>
cc: Eric Dumazet <edumazet@google.com>
cc: Jakub Kicinski <kuba@kernel.org>
cc: Paolo Abeni <pabeni@redhat.com>
cc: linux-afs@lists.infradead.org
cc: netdev@vger.kernel.org
call->tx_transmitted and call->acks_prev_seq don't need to be managed with
cmpxchg() and barriers as it's only used within the singular I/O thread.
Signed-off-by: David Howells <dhowells@redhat.com>
cc: Marc Dionne <marc.dionne@auristor.com>
cc: "David S. Miller" <davem@davemloft.net>
cc: Eric Dumazet <edumazet@google.com>
cc: Jakub Kicinski <kuba@kernel.org>
cc: Paolo Abeni <pabeni@redhat.com>
cc: linux-afs@lists.infradead.org
cc: netdev@vger.kernel.org
Strip the atomic ops and barriering off of the call timer tracking as this
is handled solely within the I/O thread, except for expect_term_by which is
set by sendmsg().
Signed-off-by: David Howells <dhowells@redhat.com>
cc: Marc Dionne <marc.dionne@auristor.com>
cc: "David S. Miller" <davem@davemloft.net>
cc: Eric Dumazet <edumazet@google.com>
cc: Jakub Kicinski <kuba@kernel.org>
cc: Paolo Abeni <pabeni@redhat.com>
cc: linux-afs@lists.infradead.org
cc: netdev@vger.kernel.org
From AFS-3.3 a trailer containing extra info was added to the ACK packet
format - but AF_RXRPC has the names of some of the fields mixed up compared
to other AFS implementations.
Rename the struct and the fields to make them match.
Signed-off-by: David Howells <dhowells@redhat.com>
cc: Marc Dionne <marc.dionne@auristor.com>
cc: "David S. Miller" <davem@davemloft.net>
cc: Eric Dumazet <edumazet@google.com>
cc: Jakub Kicinski <kuba@kernel.org>
cc: Paolo Abeni <pabeni@redhat.com>
cc: linux-afs@lists.infradead.org
cc: netdev@vger.kernel.org
Add a field to rxrpc_txbuf in which to store the checksum to go in the
header as this may get overwritten in the wire header struct when
transmitting as part of a jumbo packet.
Signed-off-by: David Howells <dhowells@redhat.com>
cc: Marc Dionne <marc.dionne@auristor.com>
cc: "David S. Miller" <davem@davemloft.net>
cc: Eric Dumazet <edumazet@google.com>
cc: Jakub Kicinski <kuba@kernel.org>
cc: Paolo Abeni <pabeni@redhat.com>
cc: linux-afs@lists.infradead.org
cc: netdev@vger.kernel.org
Convert the transmission buffer flags into a mask and use | and & rather
than bitops functions (atomic ops are not required as only the I/O thread
can manipulate them once submitted for transmission).
The bottom byte can then correspond directly to the Rx protocol header
flags.
Signed-off-by: David Howells <dhowells@redhat.com>
cc: Marc Dionne <marc.dionne@auristor.com>
cc: "David S. Miller" <davem@davemloft.net>
cc: Eric Dumazet <edumazet@google.com>
cc: Jakub Kicinski <kuba@kernel.org>
cc: Paolo Abeni <pabeni@redhat.com>
cc: linux-afs@lists.infradead.org
cc: netdev@vger.kernel.org
Each Rx protocol packet contains a per-connection monotonically increasing
serial number used to correlate outgoing messages with their replies -
something that can be used for RTT calculation.
Note this value in the rxrpc_txbuf struct in addition to the wire header
and then log it in the rxrpc_retransmit trace for reference.
Signed-off-by: David Howells <dhowells@redhat.com>
cc: Marc Dionne <marc.dionne@auristor.com>
cc: "David S. Miller" <davem@davemloft.net>
cc: Eric Dumazet <edumazet@google.com>
cc: Jakub Kicinski <kuba@kernel.org>
cc: Paolo Abeni <pabeni@redhat.com>
cc: linux-afs@lists.infradead.org
cc: netdev@vger.kernel.org
- Use the "mtd-rom" compatible for the Realview ROM
- Fix up two VGA connector cells and labels
- Fix up the Cortex spelling
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmXWedgACgkQQRCzN7AZ
XXPplg/+IZaEpq/diyrYylaaU4yHuMJBPcY5B29TDLKK6ZSWGYoN1yfvvKdtCaAc
Gn8mkLUgctDbYVXqbnlAQtaEYLUKj3xu7jwPgs2tUVr9qnqRWiXjbd0M2V4I1yvu
c1zMT7ca/HlZF9AMT9yNGS8mRWLBkePMSI6bfktwymWRTOJ3Z1xeKUIBFBf8QW5Q
3wClEHDxcK2ACHmAnUXVbvsv3FBdt3z/GTFSF+fd6WH2mafuzAHCbS6ygRLsnbUz
aURM0W/lEJxMRPC8Kr4vI41Ot9A+8haBd79bjHXsf516Dxd/GvAf5eA2/4IscX3f
E78PK9UsB2RZMsL0gNQQBsCR/WGT94N/8ltyWtSBvVhefr81Z1z9jC7pAFtq7Bm1
m/l4eJo3xMtvp1Cs9QZRmETxVaAAtOyRby4prdoKA1BeLNa2RG1OaGyfpQCSp6oj
ignFckpPNXvpwLOSaJOWJyUwZSAYv+rcUZPrUtjrMfvLZjnTwT93Rz/QTLdW7ilv
s0wulpP9RY72VdQu64iebMa9pz7v1dkXlV/LKmfGdcY8VotHYuLhzEIyBQDvEarC
NJhWGhVXgPtyJ62n3iKywkcS8fneCU+UytQLgsafQRHu9om5Uybtcx0Dd5F9u6g/
Li6XTgPKvxxd+kO52H+H/TGuRoH1F5rca2si6BWgTjdhxqKQsZc=
=hncO
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmXgoLIACgkQYKtH/8kJ
UieymxAAh3qf5NZEgX/wzBFWg7HZau8HUupke+GcOn0c8LXrw1eD8jJCfHiR7FoM
wk/P+kb7LA/wSzYN7Z5fVp/TxRYeaHJXTwOejUwZP0TX2GMGSDmXNhZyxXXx7J4X
Y1RBPLWa9RPYeHRktqoz6ASG0TEdX/gAyx+jJY2SJRhtUg4Si0lYHPqutWjaMX6a
JVF7korL2Pf/tv6N2oOVSSDVYbu5v28T9P9gzKXS/CZpFL38N8WO1W2h2WWG/BM4
mKBtZckeTNjRt9Qdw00ZQIfvzGRAu2FBYwOpMWS0fThme0/hoK03VBUMEnO+kfFF
txW8ZozeFdpomKJWwGU71Ftmtsb5wVWsBuon83MmQIaK6Rsq9qaGtTFWGCSyxacU
9QJehMrEZJveZ6C2mLyV4ElWdY0dh/I/PVtGXAAbBuDg5lELSkD5aZJx/GU1in1U
AtpP8WsqNmwaD0x4VcuGR3x9SieNSjvyG/02OxxcRzLi/1//SG9Jp1940JwWCD+1
brOi6aXvLrYQq7+2ku6XZ1kAHZXt3j8Konav+I2ILbn8H7e1dskoKoC5tSsOVdo7
JiJsYU9tvXkaLBV81M8zIC9w9BF1Z3Jiu65ctJWbHsd4ppl1xp+m2Iih6n4NTjGC
g5uwHGzJgmOSw6IVQEtU7ldCGnfvk9fRMQBUYttO2CVIHcX6UT0=
=Ah8J
-----END PGP SIGNATURE-----
Merge tag 'versatile-dts-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into soc/dt
DTS fixes for the ARM Versatile boards:
- Use the "mtd-rom" compatible for the Realview ROM
- Fix up two VGA connector cells and labels
- Fix up the Cortex spelling
* tag 'versatile-dts-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
dt-bindings: arm: realview: Spelling s/ARM 11/Arm11/, s/Cortex A-/Cortex-A/
ARM: dts: integrator: Fix up VGA connector
ARM: dts: versatile: Fix up VGA connector
ARM: dts: arm: realview: Fix development chip ROM compatible value
Link: https://lore.kernel.org/r/CACRpkdaL6j6OdixHFHoMms4e=tXEw_6ynBMFb6m8=7KkVgEedA@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Fix the node names of the DSA switch in DIR-685.
- Fix the node names of the Vitesse DSA switches.
- Fix up the Wiligear compatible strings
- Use KEY_RESTART where applicable.
-----BEGIN PGP SIGNATURE-----
iQIyBAABCgAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmXV+ccACgkQQRCzN7AZ
XXNVCw/3XFUYTCF9hxV68KfWa+ejm6JcSXq49QT4h7qoIxx3oP+DcqffYyJYrMOO
CoEvRQP3PmGFix0PPGKXltiWnbS7qfG9KSL6dub7OKdMo3oX8I9ejw2KzGDDxrqR
XmGiGIrQuVsBPD382mxXOND3RyweJ1AyUJ8FDLOQ2DlxKIoeCQaJPKru3YdLRvfV
QlwEDxG014D1jdQ8Mv75is27ET932ggeeGs4ZrWFArFXD3768b0/5dXZkB9WPDNW
oZDhEHzl4QL543XkAj0xUX0zRF23XO5m+QBYUP5JTkTz7yA3kZzN1GftGMsR+FE8
jspNg8KARBYCN/mq3HFa0gFParN78Cm4mtF6LQRauiDwBFagZa2bBf3cPHCy7Cra
+WWXPlllXgdJbYYz+qbktkZsZLk5skbojJmL2egN3y+dVCmJyniXSMbCRLZeXIT9
0gmOjSGfqqxyWDumVPwG58nBvXhDU8fSq6Tf0esP5Y1VDAUhC9TcA6LD7rxDKFhs
HWHNvMBT53h+pfAUxnQkqrcmPQaBoAdbDjSi4uETeXOyO3CVYJ6nU4A2pASNDqb5
PIZ1kVXUuxsmZeM7b1RXe7ydiP8q3gs1Ros/uPBFA1bZoE+aCbwvv02pIJ2Pa9C9
JhqLIMjAiG5Bpg8gcTiE0OOIaAMRwZ/uYVwWVgiY8CbnBtAl7w==
=47BO
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmXgoHYACgkQYKtH/8kJ
UicudQ//Ssu30IGtfQUcqPNWTc/v3jBCUY+wtiedOQmk/DUtvCzVoREQ/ktT75HR
TBDgkSQFVB38ha7EUwcej+Bcm8/SrImzDOLRxqn+nMaZcoclzbyZ5inxidCNhIf7
Rf8xSmx3e8jltIyRP8oIPkFbaABpIsHraD9UqDr3DFXr/gUQzwYnT7vveol+xZ6p
FSLQcbgd2jLRLEGPnfS4wstrOsPcyNAWz1doW7GTJoRRo8EFge4hdmqo/sN+grts
0EBdqTlO9oZAmScfviR34StaWCMpAQ3Yn9knyQarEhIMTaWPS4QGpz3RstWGlL6/
bbm7mkO4aCgN4LC8ZPNMkeMphhu98UJp5SfWFcWGI3CA77OT8/ewr0knoaZ7tXq9
CtJw+bYxDO7TzJKO3oPx3W8M5jE3+7qupo5fA1ovXYBxTR2fXY8Qn1rcjanx3T+C
bzV+z2q3sIn8XEby85uKGF2RHO30HZasf/e1vqeYrRF2LbEsptoE8V0p/rnEn6sb
OvpPnMmYPNBWtceZ73iOXD5PDC83hfoLx3wguhUjy1B991UDRpt4i8ZPUeIWklRF
6xl1RyPUKPw5k/VbS044y1Qna7rVI/urMNBXGbfrPIeKnZSKpsA3lCcCO1g1UI8b
tvC9+j8ohQlCF9DMJXBkDnDGdXhKOe81/oitTBTXVSpbjbwySbY=
=O15M
-----END PGP SIGNATURE-----
Merge tag 'gemini-dts-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into soc/dt
Gemini DTS changes for the v6.9 kernel:
- Fix the node names of the DSA switch in DIR-685.
- Fix the node names of the Vitesse DSA switches.
- Fix up the Wiligear compatible strings
- Use KEY_RESTART where applicable.
* tag 'gemini-dts-v6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: dts: gemini: Fix switch node names on Vitesse switches
ARM: dts: gemini: Map reset keys to KEY_RESTART
ARM: dts: gemini: Fix wiligear compatible strings
ARM: dts: gemini: Fix switch node names in the DIR-685
Link: https://lore.kernel.org/r/CACRpkdYQv9cyCZyjgQB4FTrxek9Hfu4EZ3syfHqHF7P6gzddvA@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This adds support for the following new machines:
- MT7981B: Xiaomi AX3000T
- MT7986A: Acelink EW-7886CAX
- MT7988A: BananaPi BPI-R4
- MT8186 Chromebooks: Tentacruel, Tentacool, Steelix, Rusty, Magneton
- MT8395/MT8195: Radxa NIO 12L
Also adds more support for the MediaTek MT8186 SoC's Video and JPEG
encoders and for MT7988 clocks, enables wakeup support for the CrOS
EC on SPI in all MediaTek Chromebooks, performs some cleanups and
includes some spare fixes.
-----BEGIN PGP SIGNATURE-----
iJ4EABYKAEYWIQQn3Xxr56ypAcSHzXSaNgTPrZeEeAUCZdNPiigcYW5nZWxvZ2lv
YWNjaGluby5kZWxyZWdub0Bjb2xsYWJvcmEuY29tAAoJEJo2BM+tl4R4XOYBAPIL
G/Y4jGNfCPPS4gFPt7y7WKG6nT270msgGFOFELszAP0WSpiOp0rBUS8oXY+NKchd
gxMuvBtfHE05/shSxasKBw==
=VN5r
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmXgn4YACgkQYKtH/8kJ
UicNaA/+NtgifoCRIko1BsATmNs5c/W5bBaU0w9NHhTDjFVHP6CZzEfFfkU5irK5
5cUZ8InXEa4/34YVcMHjHvuXhZ2jbrEHU7G1tR52z9wSQz8TQf5wiwgD+dCsFXaq
m43l3aArTQVGOgkdU4+U/AsGyNLR94snHaDXZPweVXTnPMBv9+FDObbIROvX7H6k
iRoEwfZuoaZj2gLX+RezhhqususwsnDMugBWRICgaaCGOuM07EWrmfgHUrujq9E/
nV+L2cBjjqDKqeKVL8wdznQz02uA4uWw/0jswwXd8AWyu1CSmOrb1mDlOnRGh02/
DvktM1mzIMMlnCZvbIxzqn/Pawsgo1t7aVO5LFUF5p1jYppzS+pUcIcmPi/Dq0K6
PDYlmj+70ieNqIur3BjHG1I4RAba01MDB5Ov5w6P8m+5AUTDMsA+6Z2xNR+QCGla
ca62a2KmQK0lvDZg3HHaVKCYNreV2QLP+7FukghpQ5x2TN1nGHFz2ZHedvcbxVPE
ol9IoB3qogSsCR7lSoYjthOzJl3yUBEjz5619jVBLkqGXQX1A7Dcdx9bs7zZ8tfl
3Bb5Yi+1EDH9Bk7UOE6FBA84HTpp5vU8YyWKdPR6s3mdZXKNrhepjajhPHfR2LuE
Pl4USZxL9pKMle/oB1oqsQH2vzIVqF7kgXPkRoHoNMM/oajkIX0=
=Ac61
-----END PGP SIGNATURE-----
Merge tag 'mtk-dts64-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
MediaTek ARM64 DeviceTree updates for v6.9
This adds support for the following new machines:
- MT7981B: Xiaomi AX3000T
- MT7986A: Acelink EW-7886CAX
- MT7988A: BananaPi BPI-R4
- MT8186 Chromebooks: Tentacruel, Tentacool, Steelix, Rusty, Magneton
- MT8395/MT8195: Radxa NIO 12L
Also adds more support for the MediaTek MT8186 SoC's Video and JPEG
encoders and for MT7988 clocks, enables wakeup support for the CrOS
EC on SPI in all MediaTek Chromebooks, performs some cleanups and
includes some spare fixes.
* tag 'mtk-dts64-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: (51 commits)
arm64: dts: mt8195-cherry-tomato: change watchdog reset boot flow
arm64: dts: mt7986: add port@5 as CPU port
arm64: dts: mt7622: add port@5 as CPU port
arm64: dts: mediatek: Replace deprecated extcon-usb-gpio id-gpio/vbus-gpio properties
arm64: dts: mediatek: replace underscores in node names
arm64: dts: mediatek: mt8186: Add missing xhci clock to usb controllers
arm64: dts: mediatek: mt8186: Add missing clocks to ssusb power domains
arm64: dts: mediatek: mt7622: add missing "device_type" to memory nodes
arm64: dts: mediatek: mt7986: reorder nodes
arm64: dts: mediatek: mt7986: reorder properties
arm64: dts: mediatek: Add Acelink EW-7886CAX
dt-bindings: arm64: dts: mediatek: Add Acelink EW-7886CAX access point
dt-bindings: vendor-prefixes: add acelink
arm64: dts: mediatek: Introduce the MT8395 Radxa NIO 12L board
dt-bindings: arm64: mediatek: Add MT8395 Radxa NIO 12L board compatible
arm64: dts: mediatek: mt8186: Add video decoder device nodes
arm64: dts: mediatek: mt8195: Add MTU3 nodes and correctly describe USB
arm64: dts: mediatek: Add MT8186 Magneton Chromebooks
arm64: dts: mediatek: Add MT8186 Steelix platform based Rusty
arm64: dts: mediatek: Introduce MT8186 Steelix
...
Link: https://lore.kernel.org/r/20240219131230.157792-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
1. Marvell MMP2: Very old issue, for which I sent patch back in 2014.
Patch was never picked up and now another try to fix the same
happened, so here it goes: use proper compatible MAX8925.
2. Marvell Dove: add proper unit-addresses.
3. TI DA850: add MMC interrupts.
4. STI: minor white-space fixes.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmXSS6UQHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD12z+EACatUsFDZvmp7OyzHHKYD79PDiFafeQ42g5
zlWhw28jKBJf656c8+57k9SLXgt6xBLtam10ebDYbn7nXJUoQiq5X8oaFdtvAqo8
nDtZBnPHgSH1mejLdBKzC/5JQYmIfheBvYxSFdhA5y1qIVL7/kAAfnQLMzOnwlSt
MNkY/gFaGz5djDRRa+2VAOxER1VDRV1wkKE0Ik3NSN6WQWDrcKbZnaiZHjQuRRca
9b52QQexFSHSd68qhtQqZiMYW7YgWD9xzpkuj87BdPBgO4zkrSJRTA2MpM4kVy6w
53HjXDQ+frNM7/CTwP7xDBqnJBUz9SHUyWlSNLE5f3/yC6t5zoQ7B1cGOwp6AzA6
PjXISyWIN98nvBGbmSGvw9C7duREZXwk4C/t3b5jp7Z0sixBW9OkwVuFcWoXaCQg
ib91iWUdZT8JwTH1Nu+hVlWezqZpyj7R/J20CKvEzUYc3rMpznC91OLQA9VcMDPJ
RVFU1FEj44Wzsl31wyCvOKmLeEmmbQVtaKygC9SFOi5Z0xQgSK1i+XtqxIl4UQ2g
zz2LVX3xf7H7OHGoISdEnq0L/P/u8cxWJ8OrzZfnDn2wPS7gPHJtn7sV2tylCT1W
OcJK4AWLPMQM0IjIFsBv0AkBHgLMLqMX3FTGahnX2QpXT1ZjFxc5GWlx721rOZ8b
6kOrRb0hRQ==
=YXMH
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmXgnu4ACgkQYKtH/8kJ
UicOwxAA3pub77030UyFD7f6zAMn+tl0h5Bq+Lsgo5z5AprJezggQ672cUb7nMgF
OpDTg/oGiROe9665C7iUgaiZnBG8g2TT4G0+WbsH5K0PfZRk7Cbit68Ya4UWeStT
szt1ErDq4foxG7AwZsW3gazboHg4CjEKiP6IrhBy/NHC8A13q4lMdj/HKjclyVjl
XBbOegKPQiguwI2DcITrYCkwc3mPz7SE7V9ueiLal1+rc5PdpCuHEvmZ9DLmMlXF
46ANRGIpko746KARUCI2bUKZiaulhq8c9VqVNzgGrhm76k/Su6OjPp6koxdUO/oF
kD7f19RgTj92pEQuiobkZTbAMJfxrJJns+rzx9yE+Pvv63hXeLaVeJV9X1XgzJZI
l2w4X79vD6Q/+vGGSOXBhEDk+jS5j9ebeMC/qP/Zl1sybUpXNFqTvkvAKM+EbCgz
K8skxkGgOw9RTKR0slrwH5PxqDElnm4h56lrff7dRrdZjctcFUmqp1g20uUoG4p/
XrZBlLVtEwY4Is0bkSMCYsNx2vBoEFP9HM+rqfR+GgxqXV8T4YeYE5hSdScIUbn5
bzu2Mf2jGx0N4jVfxV55+Ti7Z3J/OfPqeJ4nKY5FCU2FHyxTLvQiKTZxgaUysWYS
4MnC2AabiJcmcK6M3GI3ht+aO2K5i7ybPTiqFsuDG9t+cLMcKTc=
=3tRR
-----END PGP SIGNATURE-----
Merge tag 'dt-cleanup-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
Minor improvements in ARM DTS for v6.9
1. Marvell MMP2: Very old issue, for which I sent patch back in 2014.
Patch was never picked up and now another try to fix the same
happened, so here it goes: use proper compatible MAX8925.
2. Marvell Dove: add proper unit-addresses.
3. TI DA850: add MMC interrupts.
4. STI: minor white-space fixes.
* tag 'dt-cleanup-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt:
ARM: dts: sti: minor whitespace cleanup around '='
ARM: dts: da850: add MMD SDIO interrupts
ARM: dts: marvell: dove-cubox: fix si5351 node names
arm: dts: marvell: Fix maxium->maxim typo in brownstone dts
Link: https://lore.kernel.org/r/20240218182656.32103-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Now that the BLOCKED and IDENTITY behaviors are managed with their own
domains change to the domain_alloc_paging() op.
For now SVA remains using the old interface, eventually it will get its
own op that can pass in the device and mm_struct which will let us have a
sane lifetime for the mmu_notifier.
Call arm_smmu_domain_finalise() early if dev is available.
Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Tested-by: Moritz Fischer <moritzf@google.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/16-v6-96275f25c39d+2d4-smmuv3_newapi_p1_jgg@nvidia.com
Signed-off-by: Will Deacon <will@kernel.org>
Instead of putting container_of() casts in the internals, use the proper
type in this call chain. This makes it easier to check that the two global
static domains are not leaking into call chains they should not.
Passing the smmu avoids the only caller from having to set it and unset it
in the error path.
Reviewed-by: Michael Shavit <mshavit@google.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Tested-by: Moritz Fischer <moritzf@google.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/15-v6-96275f25c39d+2d4-smmuv3_newapi_p1_jgg@nvidia.com
Signed-off-by: Will Deacon <will@kernel.org>
Consolidate some more code by having release call
arm_smmu_attach_dev_identity/blocked() instead of open coding this.
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Tested-by: Moritz Fischer <moritzf@google.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/14-v6-96275f25c39d+2d4-smmuv3_newapi_p1_jgg@nvidia.com
Signed-off-by: Will Deacon <will@kernel.org>
Using the same design as the IDENTITY domain install an
STRTAB_STE_0_CFG_ABORT STE.
Reviewed-by: Michael Shavit <mshavit@google.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Tested-by: Moritz Fischer <moritzf@google.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/13-v6-96275f25c39d+2d4-smmuv3_newapi_p1_jgg@nvidia.com
Signed-off-by: Will Deacon <will@kernel.org>
Move to the new static global for identity domains. Move all the logic out
of arm_smmu_attach_dev into an identity only function.
Reviewed-by: Michael Shavit <mshavit@google.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Tested-by: Moritz Fischer <moritzf@google.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/12-v6-96275f25c39d+2d4-smmuv3_newapi_p1_jgg@nvidia.com
Signed-off-by: Will Deacon <will@kernel.org>
The SVA code only works if the RID domain is a S1 domain and has already
installed the cdtable.
Originally the check for this was in arm_smmu_sva_bind() but when the op
was removed the test didn't get copied over to the new
arm_smmu_sva_set_dev_pasid().
Without the test wrong usage usually will hit a WARN_ON() in
arm_smmu_write_ctx_desc() due to a missing ctx table.
However, the next patches wil change things so that an IDENTITY domain is
not a struct arm_smmu_domain and this will get into memory corruption if
the struct is wrongly casted.
Fail in arm_smmu_sva_set_dev_pasid() if the STE does not have a S1, which
is a proxy for the STE having a pointer to the CD table. Write it in a way
that will be compatible with the next patches.
Fixes: 386fa64fd5 ("arm-smmu-v3/sva: Add SVA domain support")
Reported-by: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
Closes: https://lore.kernel.org/linux-iommu/2a828e481416405fb3a4cceb9e075a59@huawei.com/
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/11-v6-96275f25c39d+2d4-smmuv3_newapi_p1_jgg@nvidia.com
Signed-off-by: Will Deacon <will@kernel.org>
Introducing global statics which are of type struct iommu_domain, not
struct arm_smmu_domain makes it difficult to retain
arm_smmu_master->domain, as it can no longer point to an IDENTITY or
BLOCKED domain.
The only place that uses the value is arm_smmu_detach_dev(). Change things
to work like other drivers and call iommu_get_domain_for_dev() to obtain
the current domain.
The master->domain is subtly protecting the master->domain_head against
being unused as only PAGING domains will set master->domain and only
paging domains use the master->domain_head. To make it simple keep the
master->domain_head initialized so that the list_del() logic just does
nothing for attached non-PAGING domains.
Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Tested-by: Moritz Fischer <moritzf@google.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/10-v6-96275f25c39d+2d4-smmuv3_newapi_p1_jgg@nvidia.com
Signed-off-by: Will Deacon <will@kernel.org>
The caller already has the domain, just pass it in. A following patch will
remove master->domain.
Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Tested-by: Moritz Fischer <moritzf@google.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/9-v6-96275f25c39d+2d4-smmuv3_newapi_p1_jgg@nvidia.com
Signed-off-by: Will Deacon <will@kernel.org>
Get closer to the IOMMU API ideal that changes between domains can be
hitless. The ordering for the CD table entry is not entirely clean from
this perspective.
When switching away from a STE with a CD table programmed in it we should
write the new STE first, then clear any old data in the CD entry.
If we are programming a CD table for the first time to a STE then the CD
entry should be programmed before the STE is loaded.
If we are replacing a CD table entry when the STE already points at the CD
entry then we just need to do the make/break sequence.
Lift this code out of arm_smmu_detach_dev() so it can all be sequenced
properly. The only other caller is arm_smmu_release_device() and it is
going to free the cdtable anyhow, so it doesn't matter what is in it.
Reviewed-by: Michael Shavit <mshavit@google.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Tested-by: Moritz Fischer <moritzf@google.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/8-v6-96275f25c39d+2d4-smmuv3_newapi_p1_jgg@nvidia.com
Signed-off-by: Will Deacon <will@kernel.org>
This was needed because the STE code required the STE to be in
ABORT/BYPASS inorder to program a cdtable or S2 STE. Now that the STE code
can automatically handle all transitions we can remove this step
from the attach_dev flow.
A few small bugs exist because of this:
1) If the core code does BLOCKED -> UNMANAGED with disable_bypass=false
then there will be a moment where the STE points at BYPASS. Since
this can be done by VFIO/IOMMUFD it is a small security race.
2) If the core code does IDENTITY -> DMA then any IOMMU_RESV_DIRECT
regions will temporarily become BLOCKED. We'd like drivers to
work in a way that allows IOMMU_RESV_DIRECT to be continuously
functional during these transitions.
Make arm_smmu_release_device() put the STE back to the correct
ABORT/BYPASS setting. Fix a bug where a IOMMU_RESV_DIRECT was ignored on
this path.
As noted before the reordering of the linked list/STE/CD changes is OK
against concurrent arm_smmu_share_asid() because of the
arm_smmu_asid_lock.
Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Tested-by: Moritz Fischer <moritzf@google.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/7-v6-96275f25c39d+2d4-smmuv3_newapi_p1_jgg@nvidia.com
Signed-off-by: Will Deacon <will@kernel.org>
Currently arm_smmu_install_ste_for_dev() iterates over every SID and
computes from scratch an identical STE. Every SID should have the same STE
contents. Turn this inside out so that the STE is supplied by the caller
and arm_smmu_install_ste_for_dev() simply installs it to every SID.
This is possible now that the STE generation does not inform what sequence
should be used to program it.
This allows splitting the STE calculation up according to the call site,
which following patches will make use of, and removes the confusing NULL
domain special case that only supported arm_smmu_detach_dev().
Reviewed-by: Michael Shavit <mshavit@google.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Tested-by: Moritz Fischer <moritzf@google.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/6-v6-96275f25c39d+2d4-smmuv3_newapi_p1_jgg@nvidia.com
Signed-off-by: Will Deacon <will@kernel.org>
The BTM support wants to be able to change the ASID of any smmu_domain.
When it goes to do this it holds the arm_smmu_asid_lock and iterates over
the target domain's devices list.
During attach of a S1 domain we must ensure that the devices list and
CD are in sync, otherwise we could miss CD updates or a parallel CD update
could push an out of date CD.
This is pretty complicated, and almost works today because
arm_smmu_detach_dev() removes the master from the linked list before
working on the CD entries, preventing parallel update of the CD.
However, it does have an issue where the CD can remain programed while the
domain appears to be unattached. arm_smmu_share_asid() will then not clear
any CD entriess and install its own CD entry with the same ASID
concurrently. This creates a small race window where the IOMMU can see two
ASIDs pointing to different translations.
CPU0 CPU1
arm_smmu_attach_dev()
arm_smmu_detach_dev()
spin_lock_irqsave(&smmu_domain->devices_lock, flags);
list_del(&master->domain_head);
spin_unlock_irqrestore(&smmu_domain->devices_lock, flags);
arm_smmu_mmu_notifier_get()
arm_smmu_alloc_shared_cd()
arm_smmu_share_asid():
// Does nothing due to list_del above
arm_smmu_update_ctx_desc_devices()
arm_smmu_tlb_inv_asid()
arm_smmu_write_ctx_desc()
** Now the ASID is in two CDs
with different translation
arm_smmu_write_ctx_desc(master, IOMMU_NO_PASID, NULL);
Solve this by wrapping most of the attach flow in the
arm_smmu_asid_lock. This locks more than strictly needed to prepare for
the next patch which will reorganize the order of the linked list, STE and
CD changes.
Move arm_smmu_detach_dev() till after we have initialized the domain so
the lock can be held for less time.
Reviewed-by: Michael Shavit <mshavit@google.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Tested-by: Moritz Fischer <moritzf@google.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/5-v6-96275f25c39d+2d4-smmuv3_newapi_p1_jgg@nvidia.com
Signed-off-by: Will Deacon <will@kernel.org>
Half the code was living in arm_smmu_domain_finalise_s2(), just move it
here and take the values directly from the pgtbl_ops instead of storing
copies.
Reviewed-by: Michael Shavit <mshavit@google.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Tested-by: Moritz Fischer <moritzf@google.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/4-v6-96275f25c39d+2d4-smmuv3_newapi_p1_jgg@nvidia.com
Signed-off-by: Will Deacon <will@kernel.org>
This is preparation to move the STE calculation higher up in to the call
chain and remove arm_smmu_write_strtab_ent(). These new functions will be
called directly from attach_dev.
Reviewed-by: Moritz Fischer <mdf@kernel.org>
Reviewed-by: Michael Shavit <mshavit@google.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Tested-by: Moritz Fischer <moritzf@google.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/3-v6-96275f25c39d+2d4-smmuv3_newapi_p1_jgg@nvidia.com
Signed-off-by: Will Deacon <will@kernel.org>
This allows writing the flow of arm_smmu_write_strtab_ent() around abort
and bypass domains more naturally.
Note that the core code no longer supplies NULL domains, though there is
still a flow in the driver that end up in arm_smmu_write_strtab_ent() with
NULL. A later patch will remove it.
Remove the duplicate calculation of the STE in arm_smmu_init_bypass_stes()
and remove the force parameter. arm_smmu_rmr_install_bypass_ste() can now
simply invoke arm_smmu_make_bypass_ste() directly.
Rename arm_smmu_init_bypass_stes() to arm_smmu_init_initial_stes() to
better reflect its purpose.
Reviewed-by: Michael Shavit <mshavit@google.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Tested-by: Moritz Fischer <moritzf@google.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/2-v6-96275f25c39d+2d4-smmuv3_newapi_p1_jgg@nvidia.com
Signed-off-by: Will Deacon <will@kernel.org>
As the comment in arm_smmu_write_strtab_ent() explains, this routine has
been limited to only work correctly in certain scenarios that the caller
must ensure. Generally the caller must put the STE into ABORT or BYPASS
before attempting to program it to something else.
The iommu core APIs would ideally expect the driver to do a hitless change
of iommu_domain in a number of cases:
- RESV_DIRECT support wants IDENTITY -> DMA -> IDENTITY to be hitless
for the RESV ranges
- PASID upgrade has IDENTIY on the RID with no PASID then a PASID paging
domain installed. The RID should not be impacted
- PASID downgrade has IDENTIY on the RID and all PASID's removed.
The RID should not be impacted
- RID does PAGING -> BLOCKING with active PASID, PASID's should not be
impacted
- NESTING -> NESTING for carrying all the above hitless cases in a VM
into the hypervisor. To comprehensively emulate the HW in a VM we
should assume the VM OS is running logic like this and expecting
hitless updates to be relayed to real HW.
For CD updates arm_smmu_write_ctx_desc() has a similar comment explaining
how limited it is, and the driver does have a need for hitless CD updates:
- SMMUv3 BTM S1 ASID re-label
- SVA mm release should change the CD to answert not-present to all
requests without allowing logging (EPD0)
The next patches/series are going to start removing some of this logic
from the callers, and add more complex state combinations than currently.
At the end everything that can be hitless will be hitless, including all
of the above.
Introduce arm_smmu_write_ste() which will run through the multi-qword
programming sequence to avoid creating an incoherent 'torn' STE in the HW
caches. It automatically detects which of two algorithms to use:
1) The disruptive V=0 update described in the spec which disrupts the
entry and does three syncs to make the change:
- Write V=0 to QWORD 0
- Write the entire STE except QWORD 0
- Write QWORD 0
2) A hitless update algorithm that follows the same rational that the driver
already uses. It is safe to change IGNORED bits that HW doesn't use:
- Write the target value into all currently unused bits
- Write a single QWORD, this makes the new STE live atomically
- Ensure now unused bits are 0
The detection of which path to use and the implementation of the hitless
update rely on a "used bitmask" describing what bits the HW is actually
using based on the V/CFG/etc bits. This flows from the spec language,
typically indicated as IGNORED.
Knowing which bits the HW is using we can update the bits it does not use
and then compute how many QWORDS need to be changed. If only one qword
needs to be updated the hitless algorithm is possible.
Later patches will include CD updates in this mechanism so make the
implementation generic using a struct arm_smmu_entry_writer and struct
arm_smmu_entry_writer_ops to abstract the differences between STE and CD
to be plugged in.
At this point it generates the same sequence of updates as the current
code, except that zeroing the VMID on entry to BYPASS/ABORT will do an
extra sync (this seems to be an existing bug).
Going forward this will use a V=0 transition instead of cycling through
ABORT if a hitfull change is required. This seems more appropriate as ABORT
will fail DMAs without any logging, but dropping a DMA due to transient
V=0 is probably signaling a bug, so the C_BAD_STE is valuable.
Add STRTAB_STE_1_SHCFG_INCOMING to s2_cfg, this was editing the STE in
place and subtly inherited the value of data[1] from abort/bypass.
Signed-off-by: Michael Shavit <mshavit@google.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/1-v6-96275f25c39d+2d4-smmuv3_newapi_p1_jgg@nvidia.com
Signed-off-by: Will Deacon <will@kernel.org>
- Add GPIO keys and watchdog support for the RZ/G3S SMARC development
board,
- Add GNSS support for Renesas ULCB development boards equipped with
the Shimafuji Kingfisher extension,
- Add support for the standalone White Hawk CPU board,
- Add support for the R-Car V4H ES2.0 (R8A779G2) SoC and the White
Hawk Single development board,
- Add initial support for the R-Car V4M (R8A779H0) SoC and the Gray
Hawk Single development board,
- Add camera support for the RZ/G2UL SoC,
- Miscellaneous fixes and improvements.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCZcYyKAAKCRCKwlD9ZEnx
cFKXAP9Irv4ndzv+HVaJQb9PzNUygshSLPw9+HR7dRn8E63X3wD6AxlgN8AVMxzp
FEF/6VMMzJ9lxKMh+1G4qjVL1xyi9Qg=
=UXce
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmXgnY8ACgkQYKtH/8kJ
UifBbQ/+OkG9Fm6/VUHWwroSszqWufQmXrMg7h28dhSJXukxif2ih26ZfUxIX6k7
aV5ghCEXJiZRr4vZCtHTnoXL/mx0Cdr2yAoleNtFK1WjPbC9J2vFRwA0szYPphbd
yCNyPdjm9Z0OP6itLei3gTyboI52lwJRA/81t9YZwj1kdZwGghhYacvv35am0IL2
QWHPCq+1k+2ItjxqdgxzytIsMmTUSt4kbnf/+TyHVg+ZPkVxc1oBxEkVLRVtmhsi
N0PHlPe9DM1s751S2kGW9dvLimO92MTZ4GisANUyHeyr5mRjSLhWdYKt4atXIzMU
fA7xNvCAc3NxbvE7nhWkdk5an2CTs7zVXBJtVLWB9bx0sEYBxsGoTvL8RVM0kJr5
lE9dPjDnde9UqnnSZZpwQgl1pePq4RhIQHIHtFCI13fAc1EVYyN+uzzz7UGK6IaW
UJBKx+6vXmuNJY8maGE9uWiE2L7gbiMfLGRDmgQvVAGgFFJXRYoDjQ6yQNKLutC3
0jj+47pzkqMf9RB+4weA9iPlULC9gYi5enFTOF7EiToffzcusAOkZPegbcbFV+4P
NxxPIEJ5BA//nPi6ot2AbtBxPQVnqeqXcVFh3wjVafzVG3W20BYz1VguiakRK/Ll
SPmmauMZ3Sub+Bt3CECw+Td8gm7NiDGaDG6TjZh6hxpGuWa2W0o=
=B1Cf
-----END PGP SIGNATURE-----
Merge tag 'renesas-dts-for-v6.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.9
- Add GPIO keys and watchdog support for the RZ/G3S SMARC development
board,
- Add GNSS support for Renesas ULCB development boards equipped with
the Shimafuji Kingfisher extension,
- Add support for the standalone White Hawk CPU board,
- Add support for the R-Car V4H ES2.0 (R8A779G2) SoC and the White
Hawk Single development board,
- Add initial support for the R-Car V4M (R8A779H0) SoC and the Gray
Hawk Single development board,
- Add camera support for the RZ/G2UL SoC,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (29 commits)
arm64: dts: renesas: gray-hawk-single: Enable watchdog timer
arm64: dts: renesas: r8a779h0: Add RWDT node
arm64: dts: renesas: Improve TMU interrupt descriptions
ARM: dts: renesas: Improve TMU interrupt descriptions
arm64: dts: renesas: r9a07g043u: Add CSI and CRU nodes
arm64: dts: renesas: Add Gray Hawk Single board support
arm64: dts: renesas: Add Renesas R8A779H0 SoC support
arm64: dts: renesas: rzg3s-smarc-som: Enable the watchdog interface
arm64: dts: renesas: r9a08g045: Add watchdog node
arm64: dts: renesas: r8a779g0: Add missing SCIF_CLK2
dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions
dt-bindings: clock: renesas,cpg-mssr: Document R-Car V4M support
dt-bindings: power: Add r8a779h0 SYSC power domain definitions
dt-bindings: power: renesas,rcar-sysc: Document R-Car V4M support
arm64: dts: renesas: r8a779g2: Add White Hawk Single support
arm64: dts: renesas: Add Renesas R8A779G2 SoC support
arm64: dts: renesas: white-hawk: Factor out common parts
arm64: dts: renesas: white-hawk-cpu: Factor out common parts
arm64: dts: renesas: white-hawk: Add SoC name to top-level comment
arm64: dts: renesas: white-hawk: Drop SoC parts from sub boards
...
Link: https://lore.kernel.org/r/cover.1707487834.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Document support for the Renesas R-Car V4M (R8A779H0) SoC, and the
White Hawk Single and Gray Hawk Single development boards.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCZcYvbQAKCRCKwlD9ZEnx
cKMUAP9UMVep3q3/Z8ZQvLmWGJYIldgBBJy5lYSB5dZyor8oowEAhOakeAhmHM1Z
wqA4PfWfDW0rtvpdYJb5DCiVKcr+fww=
=i8jD
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmXgkBgACgkQYKtH/8kJ
UictrhAAnW7pflU/AAaPM7nBCyb920rOcBbGqa0PPxRAsrHEXvKhS8ZRTR2bWzL0
hLrzY0QO1oWIG83BPDpyQyxaaBC6oGjqIMLzl3PkXAoBsmPstuoQwCkFPerjtpRd
vwd01mLTDRuJtJyRmV345E3rFj5SSkfX5pc5lIxmluPczUX6bxvadpViIkBAO79W
zWovJn4oUvPncfSYYJmKrxG1j10eltXDSjH1mSdoOsD9A+RTMzBqyqoLCWzAcOVY
7UhWfcZWj8TWgcQy33HkFyWr1dG153zlPPK0ZXe088lcdzteXNlw3e9rxXhlUcEe
C1eG9oHSQxkNUERnRof/0bq4Cam9VFJP6CV3C0wBHVeZBKGhZtBDSvn6kcgsNB/J
gzicQj0hjfmcqTzndJA8k6/FFTyLatLzyhpZhFpQk5TjN9C6YCs/G8UyxH6msp9m
lUT4D+8+K2BZHuV1+0yQssVe973UDQ+UTD5T3VaMm1dMegXY/3sVV+wy9+wHxkAj
O8L2vz3dqoTo9lNf2ukdL7lr405yAx49DpucV7JhckQ7SbzfL4hice/LN0ccRgc7
XqSChzS7daUd8Xd1KQK0NlI1FD0cDHbyqHuGyZXGEbYZjRK3bL5bsFMyKr24Y7Ap
wBDKsaQ6emTvgALL6iyOgPJGW4ypvM76sq8MkXrnLDMuhQeq+Ak=
=FAFP
-----END PGP SIGNATURE-----
Merge tag 'renesas-dt-bindings-for-v6.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DT binding updates for v6.9
- Document support for the Renesas R-Car V4M (R8A779H0) SoC, and the
White Hawk Single and Gray Hawk Single development boards.
* tag 'renesas-dt-bindings-for-v6.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
dt-bindings: soc: renesas: Document R-Car V4M Gray Hawk Single
dt-bindings: reset: renesas,rst: Document R-Car V4M support
dt-bindings: soc: renesas: Document R-Car V4H White Hawk Single
Link: https://lore.kernel.org/r/cover.1707487832.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add OF table as per the binding so that driver get instantiated and
bind automatically when the driver is built as a module.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20240226191607.397386-1-biju.das.jz@bp.renesas.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
