On BF548-EZKIT, build kernel faills with power management, video and audio enabled.
This patch fix this.
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
The memcpy() function returns the src pointer instead of the dst pointer.
This patch fix this bug.
Signed-off-by: Yi Li <yi.li@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3719
When the CPLBs get a miss, we do:
- find a victim in the HW table
- remove the victim
- find the replacement in the software table
- put it into the HW table.
If we can't find a replacement in the software table, we accidently
leave a duplicate in the HW table. This patch ensures that duplicate
is marked as not valid.
What we should do is find the replacement in the software table, before
we find a victim in the HW table - but its too late in the release cycle
to do that much restructuring of this code.
Rather that duplicate code, connect Hardware Errors (irq5) into trap_c,
so user space processes get killed properly.
The rest of irq_panic() can be moved into traps.c (later)
There is still a small corner case that causes problems when a
pheriperal interrupt goes off a single cycle before a user space
hardware error. This causes a kernel panic, rather than the user
space process being killed.
But, this checkin makes things work in 99.9% of the cases, and is a vast
improvement from what is there today (which fails 100% of the time).
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
The only user of get_wchan I was able to find is the proc fs - and proc
can't be built modular.
Signed-off-by: Adrian Bunk <bunk@kernel.org>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
The only user is the a.out support.
It was therefore removed prior to the blackfin merge from all
architectures not supporting a.out.
Currently, Blackfin doesn't suppport a.out.
Signed-off-by: Adrian Bunk <bunk@kernel.org>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
i'm *reasonably* confident that this is a typo that should be fixed.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Add throttling control via MSR when T-states uses
the FixHW Control Status registers.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Li Shaohua <shaohua.li@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] 4638/1: pxa: use PXA3xx specific macros to define clks
[ARM] remove useless setting of VM_RESERVED
This patch fixes the following section mismatches with CONFIG_HOTPLUG=n:
<-- snip -->
...
WARNING: vmlinux.o(.data+0x23640): Section mismatch: reference to .init.text.20:can_skip_ioresource_align (between 'acpi_pciprobe_dmi_table' and 'pcibios_irq_mask')
WARNING: vmlinux.o(.data+0x2366c): Section mismatch: reference to .init.text.20:can_skip_ioresource_align (between 'acpi_pciprobe_dmi_table' and 'pcibios_irq_mask')
WARNING: vmlinux.o(.data+0x23698): Section mismatch: reference to .init.text.20:can_skip_ioresource_align (between 'acpi_pciprobe_dmi_table' and 'pcibios_irq_mask')
...
<-- snip -->
Signed-off-by: Adrian Bunk <bunk@kernel.org>
Signed-off-by: Len Brown <len.brown@intel.com>
PXA3xx uses its own clk_pxa3xx_cken_ops, modify the code to use the
PXA3xx specific macros to define its clocks
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
[MIPS] N32 needs to use the compat version of sys_nfsservctl.
[MIPS] irq_cpu: use handle_percpu_irq handler to avoid dropping interrupts.
[MIPS] Sibyte: Fix name of clocksource.
[MIPS] SNI: s/achknowledge/acknowledge/
[MIPS] Makefile: Fix canonical system names
[MIPS] vpe: handle halting TCs in an errata safe way.
[MIPS] Sibyte: Stop timers before programming next even.
[MIPS] Sibyte: Increase minimum oneshot timer interval to two ticks.
[MIPS] Lasat: Fix overlap of interrupt number ranges.
[MIPS] SNI PCIT CPLUS: workaround for b0rked irq wiring of onboard PCI bus 1
[MIPS] Fix shadow register support.
[MIPS] Change get_cycles to always return 0.
[MIPS] Fix typo in R3000 TRACE_IRQFLAGS code
[MIPS] Sibyte: Replace use of removed IO_SPACE_BASE with IOADDR.
[MIPS] iounmap if in vr41xx_pciu_init() pci clock is over 33MHz
[MIPS] BCM1480: Remove duplicate acknowledge of timer interrupt.
[MIPS] Sibyte: pin timer interrupt to their cores.
[MIPS] Qemu: Add early printk, your friend in a cold night.
[MIPS] Convert reference to mem_map to pfn_to_page().
[MIPS] Sibyte: resurrect old cache hack.
This matters to any sort of device that is wired to one of the CPU
interrupt pins on an SMP system. Typically the scenario is most easily
triggered with the count/compare timer interrupt where the same interrupt
number and thus irq_desc is used on each processor.
CPU A CPU B
do_IRQ()
generic_handle_irq()
handle_level_irq()
spin_lock(desc_lock)
set IRQ_INPROGRESS
spin_unlock(desc_lock)
do_IRQ()
generic_handle_irq()
handle_level_irq()
spin_lock(desc_lock)
IRQ_INPROGRESS set => bail out
spin_lock(desc_lock)
clear IRQ_INPROGRESS
spin_unlock(desc_lock)
In case of the cp0 compare interrupt this means the interrupt will be
acked and not handled or re-armed on CPU b, so there won't be any timer
interrupt until the count register wraps around.
With kernels 2.6.20 ... 2.6.23 we usually were lucky that things were just
working right on VSMP because the count registers are synchronized on
bootup so it takes something that disables interrupts for a long time on
one processor to trigger this one.
For scenarios where an interrupt is multicasted or broadcasted over several
CPUs the existing code was safe and the fix will break it. There is no
way to know in the interrupt controller code because it is abstracted from
the platform code. I think we do not have such a setup currently, so this
should be ok.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The GNU `config.guess' uses "linux-gnu" as the canonical system name.
Fix the list of compiler prefixes checked to spell it correctly.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Adds a JR.HB after halting a TC, to ensure that the TC has really halted.
only modifies the TCSTATUS register when the TC is safely halted.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
We have no guarantee by the generic time code that the timer is stopped
when the ->next_event method is called. Modifying the Timer Initial Count
register while the timer is enabled has UNPREDICTABLE effect according to
the BCM1250/BCM1125/BCM1125H User Manual. So stop the timer before
reprogramming.
This is a paranoia fix; no ill effects have been observed previously.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
For the old minimum of a single tick a value of zero would be programmed
into the init value register which in the BCM1250/BCM1125/BCM1125H User
Manual in the Timer Special Cases section is documented to have
UNPREDICTABLE effect.
Observable sympthoms of this bug were hangs of several seconds on the
console during bootup and later if both dyntick and highres timer options
were activated.
In theory contiguous mode of the timers is also affected but in an act of
hopeless lack of realism I'll assume nobody will ever configure a KERNEL
for HZ > 500kHz but if so I leave that to evolution to sort out.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The range of MIPS_CPU IRQ and the range of LASAT IRQ overlap.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Shadow register support would not possibly have worked on multicore
systems. The support code for it was also depending not on MIPS R2 but
VSMP or SMTC kernels even though it makes perfect sense with UP kernels.
SR sets are a scarce resource and the expected usage pattern is that
users actually hardcode the register set numbers in their code. So fix
the allocator by ditching it. Move the remaining CPU probe bits into
the generic CPU probe.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
iounmap if pci clock is over 33MHz. Cosmetic because the iomap() in this
case is just a bit of address magic.
Signed-off-by: Roel Kluin <12o3l@tiscali.nl>
Acked-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The recent switch of the Sibyte SOCs from the processor specific cache
managment code in c-sb1.c to c-r4k.c lost this old hack
[MIPS] Hack for SB1 cache issues
Removing flush_icache_page a while ago broke SB1 which was using an empty
flush_data_cache_page function. This glues things well enough so a more
efficient but also more intrusive solution can be found later.
Signed-Off-By: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
in the hope it was no longer needed. As it turns it still is so resurrect
it until there is a better solution.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
since we have this always turned on now and dont want it off (and hasnt been an option in a while)
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
move the init sections to the end of memory, so that after they
are free, run time memory is all continugous - this should help decrease
memory fragementation. When doing this, we also pack some of the other
sections a little closer together, to make sure we don't waste memory.
To make this happen, we need to rename the .data.init_task section to
.init_task.data, so it doesn't get picked up by the linker script glob.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
