Commit graph

1,448,098 commits

Author SHA1 Message Date
Victor Skvortsov
7997cc1f01 drm/amdgpu: Disable ras_check_bad_page_status on VFs
Host driver determines the bad_page_status, not VF.
VFs do not have access to the EEPROM, and eeprom_init
is skipped. However, check_bad_page_status is called
outside of the eeprom_init sequence without any is_vf checks.

Add a return false in __is_ras_eeprom_supported for VFs, and use
that guard in amdgpu_ras_check_bad_page_status to prevent
incorrect access to un-initialized eeprom_control object.

Signed-off-by: Victor Skvortsov <victor.skvortsov@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:57:37 -04:00
Asad Kamal
b390cb9d77 drm/amd/pm: Validate OD DPM triples before mutating tables
vega10_odn_edit_dpm_table() and smu7_odn_edit_dpm_table() could mutate
the live ODN table for valid triples, then return 0 after detecting a
truncated buffer or out-of-range index. Validate all (index, clock,
voltage) triples first and return -EINVAL on any failure; only then
apply updates.

v2: Use distinct message for different error case, removed unused
input_level from validation loop (Lijo)

v3: Reject negative level indices, input[] is long but was compared only
against unsigned table bounds, so negative values could pass and truncate
when assigned to uint32_t input_level.

Set DPMTABLE_OD_UPDATE_SCLK/MCLK only after validation passes,
so a failed sysfs write does not leave need_update_dpm_table set for a
later commit.

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:57:33 -04:00
Lijo Lazar
921926a12e drm/amd/pm: Validate custom profile parameters
Add helpers to validate custom profile params against
negative/out-of-range values. Use the helpers to validate user passed
params.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Assisted-by: Claude Sonnet (Cursor AI)
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:57:27 -04:00
Asad Kamal
17ac73b240 drm/amdgpu: Gate debugfs MMIO access on kernel lockdown
amdgpu_regs, amdgpu_regs2, and related debugfs nodes allow
arbitrary MMIO read/write via RREG32/WREG32 without checking
security_locked_down(). On kernel_lockdown=integrity systems
this bypasses the same restrictions as /dev/mem and PCI config
space sysfs.

Check LOCKDOWN_PCI_ACCESS (matching pci-sysfs) at the entry of every
debugfs handler that performs direct register access.

v2: Use consistent check as per previous check to use
LOCKDOWN_DEBUGFS(Lijo)

v3: Do not create any entry from amdgpu_debugfs_regs_init() if
LOCKDOWN_PCI_ACCESS is active and log once. (Lijo)

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:36 -04:00
Yifan Zhang
445075e199 drm/amdgpu: add ioctl to handle RAS poison error
Add a new DRM_IOCTL_AMDGPU_PROC_OPTIONS ioctl with the
AMDGPU_PROC_OPTIONS_OP_KFD_SIGBUS_DELAY option, allowing userspace (ROCr)
to control per-process SIGBUS delivery.

Userspace for this can be found at:
https://github.com/ROCm/rocm-systems/pull/6190

Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:36 -04:00
Amber Lin
a665d09b10 drm/amdkfd: Pass known bad queue info to reset
suspend_all, resume_all, and remove bad queue has been integrated to a
centralized function, amdgpu_gfx_reset_mes_compute. Remove remove_queue
and resume_all in KFD and pass the known bad queue information required
for remove_queue to amdgpu_gfx_reset_mes_compute.

Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:36 -04:00
Amber Lin
c847c557bb drm/amdgpu: Expand MES queue/pipe reset support
MES in newer versions on gfx11 and gfx12 can support queue/pipe reset via
MES.

v2: update the fw version check (Jesse)

Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:36 -04:00
Amber Lin
f401a2633e drm/amdgpu: Remove faulty queue before resume
When driver already knows a bad queue but MES suspend_all is successful
and MES hung queue detection doesn't detect it, remove this queue refore
resume_all.

Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:36 -04:00
Alex Deucher
913c0d83be drm/amdgpu/mes12: enable compute MMIO pipe reset
Enable MMIO pipe reset for compute pipes.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:35 -04:00
Alex Deucher
1e9819678f drm/amdgpu/mes11: enable compute MMIO pipe reset
Enable MMIO pipe reset for compute pipes.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:35 -04:00
Alex Deucher
f94bbd648b drm/amdgpu: use a single entry point for mes compute reset
When we reset MES queues we need to coordinate across
KGD and KFD.  Use a single function to handle the
queue resets across KFD and KGD.

v2: squash in fixes for userqs

Co-developed-by: Jesse Zhang <jesse.zhang@amd.com>
Co-developed-by: Amber Lin <Amber.Lin@amd.com>
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Signed-off-by: Jesse Zhang <jesse.zhang@amd.com>
Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:35 -04:00
Alex Deucher
e49044061b drm/amdgpu/gfx: add a common helper to handle MES compute resets
Add helpers to handle MES compute queue resets when multiple queues
are affected.  Can you be used by both KGD and KFD.

v2: sqaush in updates
v3: squash in userq updates

Co-developed-by: Jesse Zhang <jesse.zhang@amd.com>
Co-developed-by: Amber Lin <Amber.Lin@amd.com>
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Signed-off-by: Jesse Zhang <jesse.zhang@amd.com>
Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:35 -04:00
Alex Deucher
b86e1ea9e2 drm/amdgpu/userq: add MES userq reset helper
Will be used by the common compute queue reset handler.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:35 -04:00
Alex Deucher
47f1a5dafd drm/amdkfd: plumb a helper to reset a KFD user queue
Can be called from KGD.

Reviewed-by: Amber Lin <Amber.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:35 -04:00
Alex Deucher
7b806702e0 drm/amdkfd: split out mes queue reset sequence into standalone function
No intended functional change.

Reviewed-by: Amber Lin <Amber.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:35 -04:00
Alex Deucher
b5ded03135 drm/amdgpu: Use a common KGQ and KCQ reset helper for gfx11/12
They are all the same so use a common implementation.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:35 -04:00
Alex Deucher
0268259988 drm/amdgpu: store whether to use MMIO or MES for reset
Separate settings for gfx (ME) and compute (MEC).
Use this rather than explicitly specifying it.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:35 -04:00
Alex Deucher
9b8a22c396 drm/amdgpu/gfx12: unmap the queue via MES on reset for MMIO path
To keep MES in sync.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:35 -04:00
Alex Deucher
2b8fb9308e drm/amdgpu/gfx11: unmap the queue via MES on reset for MMIO path
To keep MES in sync.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:35 -04:00
Alex Deucher
1563844c5b drm/amdgpu/gfx12: use the new MQD helper for queue reset
And while we are at it remove the reset parameter as it's
no longer needed.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:35 -04:00
Alex Deucher
0f1c75242b drm/amdgpu/gfx11: use the new MQD helper for queue reset
And while we are at it remove the reset parameter as it's
no longer needed.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:35 -04:00
Alex Deucher
a3cc796501 drm/amdgpu/gfx: add a helper for MQD restore
The handling is common so extract it to a helper.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:34 -04:00
Alex Deucher
c3e8df87af drm/amdkfd: rework MES queue reset sequence
Call MES with detect only to get the list of hung queues rather
than detecting an resetting.  Then loop over the bad queues
and reset them individually and finally remove them.  Skip
queues not owned by KFD.

v2: always call resume_all after queue reset

Reviewed-by: Amber Lin <Amber.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:34 -04:00
Amber Lin
fe5dfb55dd drm/amdgpu: Allocate enough space for hpd info on gfx11
MES in newer versions on gfx11 and gfx12 can support queue/pipe
reset via MES.

Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:34 -04:00
Shaoyun Liu
a5b9f68d38 drm/amd/amdgpu/include : update mes api header v11/v12
Update the parameter in SET_HW_RESOURCES API 1. Align with the setting
of enable_lr_compute_wa 2. Add enable_compute_pipe_reset to enable
pipe reset when compute queue reset failes

v2: add driver flags to track when we enable it

Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com>
Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:34 -04:00
Alex Deucher
7f95690063 drm/amdgpu/userq: drop detect_and_reset callback
No longer needed.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:34 -04:00
Alex Deucher
8505975d7b drm/amdgpu/userq: switch to per queue reset
Switch to using the per queue reset rather than
the detect and reset interface.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:34 -04:00
Alex Deucher
5f98f9d1a2 drm/amdgpu/userq: add mes userq reset callback
Enable per queue reset for MES managed queues.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:34 -04:00
Alex Deucher
6ecafeaba9 drm/amdgpu/userq: add per queue reset callback
Add a per queue reset callback.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:34 -04:00
Alex Deucher
9910d4df91 drm/amdgpu/userq: split the queue reset from adapter reset
No functional change intended.  Separate the per queue
reset handling from the adapter reset handling.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:34 -04:00
Alex Deucher
51fe463018 drm/amdgpu/mes: add a MMIO queue reset helper
Will be used by KFD for MMIO based resets.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:34 -04:00
Alex Deucher
b83490ad98 drm/amdgpu/mes: add userq reset helper
Implement a userq reset helper using the doorbell
index.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:34 -04:00
Alex Deucher
27c128973c drm/amdgpu/mes12: move pipe reset to mes use_mmio patch
This makes the code flows cleaner and it's only supported on
the use_mmio path.

v2: fix typo
v3: fix typo
v4: directly clear ACTIVE and DEQUEUE_REQUEST (Shaoyun Liu)

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:34 -04:00
Alex Deucher
fb1d4b2112 drm/amdgpu/mes11: move pipe reset to mes use_mmio patch
This makes the code flows cleaner and it's only supported on
the use_mmio path.

v2: fix typo
v3: fix typo
v4: directly clear ACTIVE and DEQUEUE_REQUEST (Shaoyun Liu)

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:34 -04:00
Jesse Zhang
2c476a67c6 drm/amdgpu/gfx12: Refactor compute pipe reset and add HQD cleanup
Refactor gfx_v12_0_reset_compute_pipe() to accept explicit me, pipe, and
queue parameters instead of deriving them from the ring structure. This
enables the function to be used in generic pipe reset flows.

Introduce gfx_v12_0_clear_hqds_on_mec_pipe() to properly clear
CP_HQD_ACTIVE and CP_HQD_DEQUEUE_REQUEST for all queues on a given MEC
pipe while the pipe reset is asserted, ensuring the HQDs are torn down
correctly before deasserting reset.

Switch the KCQ reset path to use the common MEC pipe reset helper
amdgpu_gfx_mec_pipe_reset_run(), which coordinates the reset sequence
including KFD suspend/resume to avoid conflicts with user mode queues.

v2: just update the sequence (Alex)
v3: directly clear ACTIVE and DEQUEUE_REQUEST (Shaoyun Liu)

Suggested-by:  Manu Rastogi <manu.rastogi@amd.com>
Suggested-by:  Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <jesse.zhang@amd.com>
Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Shaoyun Liu <shaoyun.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:34 -04:00
Jesse Zhang
5adb005e26 drm/amdgpu/gfx11: Refactor compute pipe reset and add HQD cleanup
Refactor gfx_v11_0_reset_compute_pipe() to accept explicit me, pipe, and
queue parameters instead of deriving them from the ring structure. This
enables the function to be used in generic pipe reset flows.

Introduce gfx_v11_0_clear_hqds_on_mec_pipe() to properly clear
CP_HQD_ACTIVE and CP_HQD_DEQUEUE_REQUEST for all queues on a given MEC
pipe while the pipe reset is asserted, ensuring the HQDs are torn down
correctly before deasserting reset.

Switch the KCQ reset path to use the common MEC pipe reset helper
amdgpu_gfx_mec_pipe_reset_run(), which coordinates the reset sequence
including KFD suspend/resume to avoid conflicts with user mode queues.

v2: just update the sequence (Alex)
v3: directly clear ACTIVE and DEQUEUE_REQUEST (Shaoyun Liu)

Suggested-by:  Manu Rastogi <manu.rastogi@amd.com>
Suggested-by:  Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <jesse.zhang@amd.com>
Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Shaoyun Liu <shaoyun.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:33 -04:00
Jesse Zhang
9d2da45b1d drm/amdgpu/mes_v12_1: use mes schedule pipe for legacy queues on unified MES
when suspend_all_gangs is issued to pipe0 MES during system suspend or runtime PM, pipe0 can only suspend and resume queues it has tracked.
KCQs registered with a non-zero pipe slot may not be correctly handled, leaving them in an inconsistent state after resume.

v3: fix the schedule pipe issue

Suggested-by: Michael Chen <michael.chen@amd.com>
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Suggested-by: Shaoyun Liu <shaoyun.liu@amd.com>
Signed-off-by: Jesse Zhang <jesse.zhang@amd.com>
Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:33 -04:00
Jesse Zhang
5ec4cc9170 drm/amdgpu/mes_v12_0: use mes schedule pipe for legacy queues on unified MES
when suspend_all_gangs is issued to pipe0 MES during system suspend or runtime PM, pipe0 can only suspend and resume queues it has tracked.
KCQs registered with a non-zero pipe slot may not be correctly handled, leaving them in an inconsistent state after resume.

v3: fix the schedule pipe issue
v4: use schedule pipe for KQ resets

Reviewed-by: Michael Chen <michael.chen@amd.com>
Suggested-by: Michael Chen <michael.chen@amd.com>
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Suggested-by: Shaoyun Liu <shaoyun.liu@amd.com>
Signed-off-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:33 -04:00
Alex Deucher
974fa2e7dc drm/amdgpu/gfx12: only need to remap KCQs when reset via MMIO
MES remaps kernels queues as part of it's reset sequence.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:33 -04:00
Alex Deucher
86a1b84d85 drm/amdgpu/gfx11: only need to remap KCQs when reset via MMIO
MES remaps kernels queues as part of it's reset sequence.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:33 -04:00
Alex Deucher
b54a809c29 drm/amdgpu/mes12: use proper grbm_select function
s/soc21_grbm_select/soc24_grbm_select/

No functional difference as the register offsets are
the same.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:33 -04:00
Alex Deucher
59c66cc360 drm/amdgpu/sdma: handle pipe reset more gracefully
Save any unprocessed work in the queues using the
new ring helper.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:33 -04:00
Alex Deucher
659fe71521 drm/amdgpu/vcn: handle pipe reset more gracefully
Save any unprocessed work in the queues using the
new ring helper.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:33 -04:00
Alex Deucher
714d354479 drm/amdgpu: amdgpu_ring_set_fence_errors_and_reemit() handle NULL fence
All the guilty fence parameter to be NULL.  Will be needed for
future functionality.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:33 -04:00
Alex Deucher
36ed61b1c0 drm/amdgpu/fence: add helper to extract the guilty fence
Add a helper to extract the first amdgpu_fence which has
not yet signalled and is thus guilty or at least collateral
damage.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:33 -04:00
Alex Deucher
ce3f23a780 drm/amdgpu: track guilty fence for queue reset
If we've already seen a fence, don't backup the
ring contents since presumably either the previous reset
was not successful or there was something wrong with the
data.

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:33 -04:00
Alex Deucher
930a915de8 drm/amdgpu: don't reemit if there is nothing to reemit
Return early in amdgpu_ring_set_fence_errors_and_reemit()
if ring_backup_entries_to_copy is 0.  That means that either
the ring is idle and there is nothing to reemit, or there
some reason why we should reemit, so return early and
signal the fences (if applicable).

Reviewed-by: Jesse Zhang <jesse.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17 15:51:33 -04:00
Dave Airlie
52d4ab1ca7 drm-misc-next-fixes for v7.2:
- Fix agp_amd64_probe error propagation.
 - Require carveout when PASID is not enabled amdxdna.
 - Clear variable to prevent second unbind in amdxdna.
 - Add separate Kconfig option for DMABUF_HEAPS_SYSTEM_CC_SHARED.
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Merge tag 'drm-misc-next-fixes-2026-06-11' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next

drm-misc-next-fixes for v7.2:
- Fix agp_amd64_probe error propagation.
- Require carveout when PASID is not enabled amdxdna.
- Clear variable to prevent second unbind in amdxdna.
- Add separate Kconfig option for DMABUF_HEAPS_SYSTEM_CC_SHARED.

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patch.msgid.link/c7a9dbb0-a5c8-4e67-904e-1a52b3de9bb4@linux.intel.com
2026-06-13 08:10:38 +10:00
Arnd Bergmann
f7606400f1 dma-buf: move system_cc_shared heap under separate Kconfig
While system heap and system_cc_shared heap share a lot of code
and hence the same source file, their users have different needs.

system heap users need it to be a loadable module, while
system_cc_shared heap users don't.

Building as a loadable module breaks system_cc_shared heap on
powerpc and s390 due to un-exported set_memory_encrypted /
set_memory_decrypted functions.

Fix these by reorganising code to put the system_cc_shared heap
under a new Kconfig symbol, which allows either building both
into the kernel, or leave encryption up to the consumers of the
system heap.

Fixes: fd55edff8a ("dma-buf: heaps: system: Turn the heap into a module")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
  [sumits: updated DMABUF_HEAPS_CC_SYSTEM to DMABUF_HEAPS_SYSTEM_CC_SHARED]
Reviewed-by: T.J. Mercier <tjmercier@google.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Link: https://patch.msgid.link/20260610142329.3836808-1-sumit.semwal@linaro.org
2026-06-11 20:21:44 +05:30
Lizhi Hou
2db6ddf1cb accel/amdxdna: Clear sva pointer after unbind
Add client->sva = NULL after the unbind makes it consistent with how
amdxdna_sva_fini() already clears the pointer after unbinding. The
IS_ERR_OR_NULL guard in sva_fini will then correctly skip the second
unbind.

Fixes: 3cc5d7a595 ("accel/amdxdna: Add carveout memory support for non-IOMMU systems")
Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>
Signed-off-by: Lizhi Hou <lizhi.hou@amd.com>
Link: https://patch.msgid.link/20260604202815.2425882-1-lizhi.hou@amd.com
2026-06-09 23:22:33 -07:00