amdgpu_dm_create_validate_stream_for_sink() walks encoding_order[] and
uses the first encoding that validates. YCbCr 4:4:4 is listed before
RGB, so an HDMI sink that advertises 4:4:4 gets YCbCr 4:4:4 whenever the
"color format" property is left at AUTO, even though RGB fits the same
link.
That contradicts the documented AUTO behaviour for HDMI in enum
drm_connector_color_format (RGB, falling back to YCbCr 4:2:0 only when
the bandwidth is not available or the mode is 4:2:0-only), which the
amdgpu implementation of the property also describes. It also leaves
the "Broadcast RGB" property without effect on such sinks, since the
quantization range it selects only applies to RGB output.
Try RGB first. The mask still holds every encoding the sink supports,
so a mode that cannot carry RGB falls back exactly as before.
For reference, v7.2 picked RGB here unless YCbCr 4:4:4 was forced
through debugfs, while earlier kernels picked YCbCr 4:4:4 for any HDMI
sink that advertised it.
Fixes: 0b0ff65d3c ("drm/amd/display: Refactor stream validation")
Suggested-by: Adolfo Rodrigues <adolfotregosa@gmail.com>
Assisted-by: Claude Code:claude-fable-5-1
Signed-off-by: Adrian Betschart <adrian.betschart@cinemaone.ch>
Reviewed-by: Fangzhi Zuo <jerry.zuo@amd.com>
Tested-by: Adolfo Rodrigues <adolfotregosa@gmail.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
amdgpu_ualink_export_handle() tests robj->ualink_handle_lo and stores
the generated handle into it without any lock; xa_lock only covers
handle generation and the xarray insert.
Two threads can therefore both observe a zero handle for the same BO and
both allocate an exporter node, take an amdgpu_bo_ref() and insert into
exp_xa, with the last store to ualink_handle_lo winning. Teardown only
erases the handle recorded in the BO, so the losing node keeps its BO
reference and pinned VRAM until device teardown.
Each racing thread still generates its own handle and inserts its own
node, but the handle is published to the BO under the BO reservation
lock after re-checking that ualink_handle_lo is still zero. Exactly one
thread makes that transition; the others find a non-zero value, roll
back their node (erase from exp_xa, drop the DMABuf and BO references,
free it) and return -EAGAIN so the caller retries and picks up the
winning handle. This keeps a single exporter node per BO.
Fixes: c67cb19811 ("drm/amdgpu: Implement UALink handle export")
Reported-by: Sashiko-bot <sashiko-bot@kernel.org>
Closes: https://sashiko.dev/#/patchset/20260914054604.12850-1-kmehltretter@gmail.com?part=1
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Use the right formatting for some fields which are encoded in Q10
format.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Allow RAS_MP1_MSG_ClearMcaOnRead MP1 message in Mode1 reset, to support
device debug mode setup on GPU recovery resume.
Signed-off-by: Ce Sun <cesun102@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Suppress warning for unsupported early init service.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Building x86_64 allmodconfig with clang fails:
.../dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c:10491:13:
error: stack frame size (3128) exceeds limit (3072) in
'dml_core_mode_programming' [-Werror,-Wframe-larger-than]
That config enables both KASAN and UBSAN, and should get the 4096
byte limit meant for clang COMPILE_TEST sanitizer builds. The check
in the dml and dml2_0 Makefiles concatenates the three symbols with
no separator:
ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)$(CONFIG_UBSAN)),y)
KASAN and KCSAN cannot be enabled together, so before UBSAN was
added the string was at most "y". UBSAN can be enabled alongside
either of them, and with both set the string becomes "yy",
$(filter y,yy) is empty, and the build falls through to the
non-sanitizer limit of 3072. Adding UBSAN to the check therefore
lowered the limit for the most heavily instrumented builds instead
of raising it.
Separate the symbols with spaces so that $(filter) sees individual
words, and test for a non-empty result. Only the configs with two
sanitizers enabled change behaviour.
Found by KernelCI builds of the linus-next tree.
Fixes: ebf8b0fd85 ("drm/amd/display: Relax DML frame limit with UBSAN")
Assisted-by: LLM
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
In gmc_v12_1_flush_gpu_tlb(), flush_type was not properly
passed to gmc_v12_1_flush_vm_hub(). This only affected
the MMIO path. In most cases the flush would go through
MES.
Reviewed-by: Mukul Joshi <mukul.joshi@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Not enabled in 7.1 so drop the assignment.
Cc: Horatio Zhang <hongkun.zhang@amd.com>
Cc: Hawking.Zhang@amd.com
Fixes: 4ed5116aac ("drm/amdgpu: Add sdma v7_1_0 support")
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The firmware requested in gfx_v6_0_init_microcode() is not released
when the GFX block is torn down, leaking the firmware resources.
Add gfx_v6_0_free_microcode() and call it from gfx_v6_0_sw_fini()
to release the PFP, ME, CE and RLC firmware.
Signed-off-by: Willian Oliveira <williandossantosdeoliveira287@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
acp_hw_init() registers ACP child devices with mfd_add_devices() before
attaching them to the ACP power domain and initializing the hardware.
If attaching a child to the power domain fails, or if the ACP reset or
clock enable operation times out, the failure path frees only the
source cell, resource, and platform-data allocations. The child
platform devices already registered by mfd_add_devices() remain
registered and are never released.
Remove the children from the power domain and unregister the MFD
devices on failures that occur after mfd_add_devices() succeeds. Keep
mfd_add_devices() failures on the existing cleanup path since the MFD
core already rolls back partially registered children itself.
The issue was identified by a static analysis tool I developed and
confirmed by manual review.
Fixes: 25030321ba ("drm/amd: add pm domain for ACP IP sub blocks")
Signed-off-by: Guangshuo Li <lgs201920130244@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
amdgpu_discovery_sysfs_ips() allocates ip_hw_instance with
kzalloc_flex() and initializes its embedded kobject before calling
kobject_add().
If kobject_add() fails, the return value is ignored and execution
continues without dropping the initial kobject reference. The failed
kobject is not retained in the kset list, so the normal sysfs teardown
path cannot find it. As a result, ip_hw_instance_release() is never
called and the ip_hw_instance allocation is leaked.
Call kobject_put() when kobject_add() fails so the initial reference is
dropped and ip_hw_instance_release() can free the allocation. Keep the
existing best-effort sysfs behavior by continuing with the remaining IP
entries after the failed registration.
The issue was identified by a static analysis tool I developed and
confirmed by manual review.
Fixes: a6c40b1780 ("drm/amdgpu: Show IP discovery in sysfs")
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Guangshuo Li <lgs201920130244@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Use kzalloc_objs() instead of kcalloc() to simplify object allocations.
Convert only the instances with sizeof() passed.
No functional change.
Signed-off-by: Lalit Shankar Chowdhury <lalitshankarch@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
amdgpu_pmops_suspend_noirq() resets the ASIC unconditionally. When the GPU
has been parked by vga_switcheroo it has neither power nor a PCIe link, so
the reset cannot reach it: pci_set_power_state() reports the device as
inaccessible and amdgpu_asic_reset() returns -EINVAL. A failure there
aborts the entire noirq suspend phase, and with it the system suspend, so
the machine cannot sleep at all while the GPU is switched off.
amdgpu_device_prepare(), amdgpu_device_suspend() and amdgpu_device_resume()
all bail out early on DRM_SWITCH_POWER_OFF. This callback was added later,
for an unrelated reason, and did not inherit the check. nouveau guards
every one of its PM callbacks the same way.
Bail out the same way here. On a single-GPU system switch_power_state is
never DRM_SWITCH_POWER_OFF, so this is a no-op there.
Found on a MacBookPro11,5, where the Radeon is powered down through
apple-gmux so that the internal panel can be driven by the iGPU instead.
Every suspend failed in amdgpu_pmops_suspend_noirq() while the card was
off; with this check a full S3 cycle completes.
Fixes: 9e051720f9 ("drm/amdgpu: Ensure HDA function is suspended before ASIC reset")
Signed-off-by: Theo Andersen Carton <andersen.theo@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Keep PER_PIPE disabled until the minimum CP firmware version for
warm reset is confirmed.
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Keep PER_PIPE disabled until the minimum CP firmware version for
warm reset is confirmed.
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Replace the disabled pipe-reset stub with the shared PER_PIPE capability
check, so GFX MMIO pipe reset follows gfx_supported_reset.
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Replace the disabled pipe-reset stub with the shared PER_PIPE capability
check, so GFX MMIO pipe reset follows gfx_supported_reset.
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Route GFX user queue resets through amdgpu_gfx_reset_mes_gfx() when
HQD detection and PER_PIPE are available, preserving collateral kernel
rings across a pipe reset.
If the HQD cannot be located, use MES packet reset and protect kernel
rings on all GFX pipes.
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
The user queue UAPI permits the WPTR at any 8-byte aligned offset within a
BO. amdgpu_userq_fence_read_wptr() locates the mapping containing the WPTR
address, but amdgpu_bo_kmap() returns the start of the BO, so the code read
the first u64 regardless of the WPTR offset. USERQ_SIGNAL uses this value as
the exported fence seqno, so a wrong read makes the fence signal early (or
never), breaking dependency synchronization.
Translate the WPTR GPU address to a byte offset within the BO, accounting
for the VA mapping start and the mapping's BO offset, before reading it.
Fixes: a292fdecd7 ("drm/amdgpu: Implement userqueue signal/wait IOCTL")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
In gmc_v12_0_flush_gpu_tlb(), flush_type was not properly
passed to gmc_v12_0_flush_vm_hub(). This only affected
the MMIO path. In most cases the flush would go through
MES.
Reviewed-by: Mukul Joshi <mukul.joshi@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add the MES firmware debug-extension ("mes_dbgext") API definitions to
the shared MES v11 and v12 interface headers: the
MESAPI_MISC__SETUP_MES_DBGEXT misc opcode, the MES_DBGEXT_INIT_DATA
struct (log buffer MC address + option bits), and the corresponding
dbgext_init_data member of union MESAPI__MISC.
These describe the SETUP_MES_DBGEXT packet the firmware expects and are
consumed by the per-IP mes_dbgext wiring for gfx11 and gfx12.
Signed-off-by: Yongqiang Sun <Yongqiang.Sun@amd.com>
Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
amdgpu_ualink_export_handle() takes an explicit amdgpu_bo_ref() before
building the exporter node, and the out: label only drops the reference
from drm_gem_object_lookup(). The xarray insert failure path unrefs the
BO, but the drm_gem_prime_handle_to_dmabuf() failure path does not.
Userspace can hit that path at will, for example by exhausting its file
descriptor table so the dmabuf export returns -EMFILE, leaking a BO
reference and its pinned VRAM on every attempt.
Fixes: c67cb19811 ("drm/amdgpu: Implement UALink handle export")
Reported-by: Sashiko-bot <sashiko-bot@kernel.org>
Closes: https://sashiko.dev/#/patchset/20260914054604.12850-1-kmehltretter@gmail.com?part=1
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Route kernel GFX resets through amdgpu_gfx_reset_mes_gfx() when PER_PIPE
is supported, so collateral kernel rings are preserved across a pipe
reset. Keep the existing queue reset path otherwise.
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
The MPCCs different gamut remap matrices allow for S2D13 and S3D12 floating
point formats, but only S2D13 is used. There may be cases where
more integer bits are required.
[How]
Switch to S3D12 if any entries in the remap matrix cannot fit in S2D13.
Otherwise, prefer the extra precision of S2D13. Communicate the max value
that hw can support to dm via dc color caps.
Signed-off-by: Clay King <clayking@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
Rounding up cursor width was only used to calculate total size in
previous generations. Do not use the rounded up cursor width in
hardware programming.
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
These are important for getting correct DP and audio output.
The wrong pixel clock will be used otherwise.
[How]
Update the default clocks for the DCN60 lite3 variant.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Set a flag to enable pstate pmo, we want to always allow pstate
support on dcn42
Partial application: DCN42B resource constructor only.
Fixes: 6352e60273 ("drm/amd/display: Enable dcn42 pstate pmo")
Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
- BSOD was found on a DP config due to incomplete DSC padding
implementation for DP
- Block DSC padding on DP until fully implemented
Signed-off-by: Relja Vojvodic <Relja.Vojvodic@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: George Shen <george.shen@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
drm_mode_config_validate() warns when a plane exposes an alpha-capable
pixel format without a blend_mode_property. amdgpu DM only created that
property for overlay planes, so PRIMARY and CURSOR triggered the warning
on every probe and reload in kernel 7.2.
Create the blend mode property for every plane that advertises an alpha
format. Keep overlay-only alpha_property. Cursor advertises only
pre-multiplied blend mode because native cursor programming is
pre-multiplied.
Assisted-by: Cursor:Claude-Opus-4.8
Signed-off-by: Ray Wu <ray.wu@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Sun peng (Leo) Li <sunpeng.li@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why & how]
Out-of-urgent bandwidth delivery to DCN is very poor under workloads.
Even after asserting urgent, empirical data shows urgent return BW
delays of up to 100 μs. Override the value when programming
watermarks to avoid modifying mode support. Maintain the DML's calculated
value as a floor.
Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY&HOW]
VTG params should be corrected based on HW expectation:
- FP2 = v_bp - vstartup_start (if vstartup is after vsync), else 0
- vcount_init = OTG SOF position from vsync (0) or vtotal
depending on vstartup position
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why/How]
Current method of keeping track of the LT timeout can cause the actual
elapsed time to creep past the spec-defined limits.
Adjust the behavior to make timeouts more consistent.
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Chris Park <chris.park@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why]
some panel will generate HPD if receive invalid the action.
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
The DCN10 post-unlock BLS path still emitted self-refresh suppression steps
that are dead for this flow. Keeping them also left non-compliant BLS enums
and documentation behind after the architecture cleanup.
[HOW]
Removed the dead DCN10 BLS producer path, dropped the associated BLS enums,
params, helpers, dispatcher cases, unit-test dumper cases, and updated the
BLS documentation. Kept the shared dcn10_update_pending_status consumer
because later DCN generations still use it.
Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
hubbub_soft_reset_params carried the callee itself as a function pointer,
so the step was not fully described by its parameters. The core_gtest
dumper could only record hubbub and reset, which means two sequences
calling different functions compare equal. It also forced dcn401_hwseq to
name the dcn10 symbol hubbub1_soft_reset directly, because hubbub_funcs
had no slot for a soft reset.
[HOW]
Added soft_reset to hubbub_funcs and pointed hubbub4_01_funcs,
hubbub42_funcs and hubbub60_funcs at hubbub1_soft_reset, the same way
allow_self_refresh_control is already shared. Dropped the function pointer
from the params struct and the add helper, and had the executor call
hubbub->funcs->soft_reset. The dcn10_hubbub.h include in dcn401_hwseq.c is
no longer needed.
Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
Besides programming the hubbub, the HUBBUB_ALLOW_SELF_REFRESH_CONTROL
executor wrote through an output pointer into hwseq->wa_state to record
that the MPO stutter workaround had been applied. That bookkeeping has no
relationship to the register write and makes the operation mutate a logical
object while the sequence runs.
[HOW]
Removed the pointer from hubbub_allow_self_refresh_control_params and from
the add helper, leaving the executor a plain pass through to
hubbub->funcs->allow_self_refresh_control.
hwss_build_post_unlock_full_sequence now sets the workaround flag itself,
inside the same condition that decides to emit the step. TG_GET_FRAME_COUNT
is left as is: its out parameter is the read back register value, and
reading it after the write matches the legacy implementations.
Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
hubbub_force_pstate_change_control_params::wait was passed as the allow
argument of hubbub_funcs::force_pstate_change_control, which drives
DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE. Sitting three lines above a
udelay(500), the name read as a timing control and invited the wrong
conclusion about what the field does.
[HOW]
Renamed the field to allow and updated the add helper signature, the
executor, the core_gtest dumper and comparator, and the affected
core_golden entry. No functional change.
Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
The operation wrote no hardware register. Its executor only set
opp->mpcc_disconnect_pending, a driver side flag, which breaks the rule
that a block sequence step programs a hardware block rather than mutating
logical objects. It was also split across phases: written while the
pre-unlock sequence executed, then read and cleared while the post-unlock
sequence was still being built.
[HOW]
Deleted the enum value, the params struct, the add helper, the executor and
the dispatch case. dcn401_plane_atomic_disconnect_sequence now sets the
flag during the build phase, matching what dcn10, dcn20, dcn201, dcn35,
dcn3ag and dcn42b already do. Updated the operation specs and the
core_gtest dumper.
Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
opp2_set_disp_pattern_generator read
debug.disable_dynamic_expansion_for_test_pattern through opp->ctx->dc while
the sequence was executing. A block sequence operation must take its inputs
from a flat parameter list resolved during the build phase, so this hid an
input from the recorded sequence and left the FMT_DYNAMIC_EXP_CNTL branch
unreachable from the OPP unit tests.
[HOW]
Added disable_dyn_exp_for_test_pattern to
opp_funcs::opp_set_disp_pattern_generator and to
opp_set_disp_pattern_generator_params, and updated every caller to pass
dc->debug.disable_dynamic_expansion_for_test_pattern explicitly. Updated
the unit test mocks and the core_gtest dumper, and extended opp_gtest to
cover both values of the new flag.
Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why/How]
On the PWM path, convert the userspace brightness to an input signal and
derive the target luminance from the custom backlight curve, then pass
the resulting millipercent to the power module.
This keeps PWM programming and backlight curve mapping in the power
module, aligning the Linux path with the Windows behavior.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/5723
Fixes: 3c108046e1 ("drm/amd/display: Add power module on Linux")
Assisted-by: Cursor:Claude-Opus-4.8
Signed-off-by: Ray Wu <ray.wu@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: ChiaHsuan (Tom) Chung <chiahsuan.chung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Description]
Add the POR setting for SDP_PORT_CONTROL into dc init sequence.
This is temporary until the initialization moves into pre-OS DMCUB.
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[why & how]
DCN60 supports cursor offload to DMU.
Request cursor offload in amdgpu_dm_init and initialize it after DMUB is up
(dc_dmub_srv_cursor_offload_init), which should be picked up by all the
ASICs that support cursor offload in the dcnX_resouce.c.
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why & How]
The copyright notice was carried over from code related to kernel
floating-point support. The associated DC_FP_START() and DC_FP_END() macros
are not present in SPL, so the notice is no longer applicable.
Remove the unused copyright notice from spl_os_types.h.
Signed-off-by: Jackson He <Jackson.He@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Samson Tam <samson.tam@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
why:
When a display is disabled the surviving DSC stream is committed with no
planes but the dynamic ODM policy still expands it to a four to one
combine. The added plane-less segments skip program_pipe so their OPP
formatter is never configured. The DPG blank then feeds an unprogrammed
formatter and the OPTC input underflows which flashes grey on screen.
how:
Program the OPP formatter for each plane-less OPP head in update_odm and
update_odm_sequence the same way program_pipe does for planed pipes. Both
function pointers are checked for null before calling. Every ODM segment
now feeds valid data to the OPTC so the four to one combine no longer
underflows.
Signed-off-by: Ashwin Santhosh <Ashwin.Santhosh@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
amdgpu_gem_ualink_handle_ioctl() dereferences adev->ualink.info before
validating it, but that structure is only allocated when the UALink IP
block is present, which is currently added only for GFX 12.1 only. The
ioctl is registered for every amdgpu device with DRM_RENDER_ALLOW, so
on any other ASIC a render node user can oops the kernel with a single
call.
Return -EOPNOTSUPP when the UALink software state is absent.
Fixes: 15d1c306d8 ("drm/amdgpu: Add ioctl infra for exporting/importing UALink handles")
Reported-by: Sashiko-bot <sashiko-bot@kernel.org>
Closes: https://sashiko.dev/#/patchset/20260914054604.12850-1-kmehltretter@gmail.com?part=1
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
Hotplugging an HDMI FRL sink can wedge DMCUB when a poll-driven retrain
lands on a link whose PHY has just been torn down. The status polling
path can program PHY EQ on the disabled PHY, after which the sink SCDC
reads back version 0 and the display fails to light up.
[HOW]
Skip FRL status polling unless the link is actively driving a stream.
The check runs under dc_lock, so it is serialized with link detection
and modesets while the PHY is being torn down.
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
