As we have deleted some flag, lets renumber them so there are no holes.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20220223134358.1914798-33-michael@walle.cc
Now that there is almost no special case code left in
spi_nor_sr_ready(), the return check looks odd. Move the function call
closer to the return code checking.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20220223134358.1914798-32-michael@walle.cc
Drop the generic spi_nor prefix for all the spansion functions.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20220223134358.1914798-31-michael@walle.cc
Now that all functions using that flag are local to the spansion module,
we can convert the flag to a manufacturer one.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20220223134358.1914798-30-michael@walle.cc
The clear status register flags is only available on spansion flashes.
Move all the functions around that into the spanion module.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20220223134358.1914798-29-michael@walle.cc
Don't return early when the flash is smaller than or equal to 16MiB. We
need to be able to register hooks for all sizes of flashes. This also has
the benefit that it increases the readability of the code because the
action, i.e. registering the fixups, is connected to the condition, i.e.
flashes larger than 16MiB.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20220223134358.1914798-28-michael@walle.cc
Drop the generic spi_nor prefix for all the micron-st functions.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20220223134358.1914798-27-michael@walle.cc
Now that all functions using that flag are local to the micron module,
we can convert the flag to a manufacturer one.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20220223134358.1914798-26-michael@walle.cc
The flag status register is only available on micron flashes. Move all
the functions around that into the micron module.
This is almost a mechanical move except for the spi_nor_fsr_ready()
which now also checks the normal status register. Previously, this was
done in spi_nor_ready().
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20220223134358.1914798-25-michael@walle.cc
XRDSR is a combination of xilinx and the RDSR opcode, but the register
is just the status register. Correct the debug message.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20220223134358.1914798-24-michael@walle.cc
Drop the generic spi_nor prefix for all the xilinx functions.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20220223134358.1914798-23-michael@walle.cc
Mechanically move all the xilinx functions to its own module.
Then register the new flash specific ready() function.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20220223134358.1914798-22-michael@walle.cc
The _page_size marco parameter was missing parentheses around it. Add
them.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20220223134358.1914798-21-michael@walle.cc
We will move vendor specific code into the vendor modules and thus we
will have to export these functions so they can be called.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20220223134358.1914798-20-michael@walle.cc
Xilinx and Micron flashes have their own implementation of the
spi_nor_ready() function. At the moment, the core will figure out
which one to call according to some flags. Lay the foundation to
make it possible that a flash can register its own ready()
function.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20220223134358.1914798-19-michael@walle.cc
Instead of always using a function pointer (and initializing it to our
default), just call the default function if the flash didn't set its own
one. That will make the call flow easier to follow.
Also mark the parameter as optional now.
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20220223134358.1914798-18-michael@walle.cc
Devices can also be child nodes when we also control that device
through the upstream device (ie, MIPI-DCS for a MIPI-DSI device).
drm_of_find_panel_or_bridge can lookup panel or bridge for a given
device has port and endpoint and it fails to lookup if the device
has a child nodes.
This patch add support to lookup for a child node of the given parent
that isn't either port or ports.
Example OF graph representation of DSI host, which has port but
not has ports and has child panel node.
dsi {
compatible = "allwinner,sun6i-a31-mipi-dsi";
#address-cells = <1>;
#size-cells = <0>;
port {
dsi_in_tcon0: endpoint {
remote-endpoint = <tcon0_out_dsi>;
};
panel@0 {
reg = <0>;
};
};
Example OF graph representation of DSI host, which has ports but
not has port and has child panel node.
dsi {
compatible = "samsung,exynos5433-mipi-dsi";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_to_mic: endpoint {
remote-endpoint = <&mic_to_dsi>;
};
};
};
panel@0 {
reg = <0>;
};
};
Example OF graph representation of DSI host, which has neither a port
nor a ports but has child panel node.
dsi0 {
compatible = "ste,mcde-dsi";
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
reg = <0>;
};
};
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20220202160414.16493-1-jagan@amarulasolutions.com
Highlights:
----------
-MCU:
-Fix W=1 warnings for timers (duplicate unit-address) for F4 and F7 series.
-Enable DMA2D on f469 disco.
- MPU:
-General:
- Add new board support: emSBS-Argon.
- Add dma configuration for all U(S)ART nodes and disable them in board files
when they are not needed in stm32mp15.
- Correct GIC PPI interrupts on stm32mp15 and stm32mp13.
- ST boards:
- Add EXTI support on stm32mp13
- Add DMA, MDMA and DMAmux support to stm32mp13 (iso feature than MP15)
- Update SDMMC1/2 support on stm32mp13: sleep config, update version to v2.2,
update the max frequency to 130 MHz.
- DH boards:
- Enable rproc to control the CM4 and IPCC mailbox to interact with it.
-----BEGIN PGP SIGNATURE-----
iQJRBAABCgA7FiEEctl9+nxzUSUqdELdf5rJavIecIUFAmIY7cYdHGFsZXhhbmRy
ZS50b3JndWVAZm9zcy5zdC5jb20ACgkQf5rJavIecIU+ARAAhKa66mPq5OyeaK5n
KC3JFupCSfMx9xIDaElFAEfmjYcju1ZEo9kXA8j7fIwjzcSmYzr7jFTPHu8Zd9Zb
SEjSS+5lLn/Lfps8xxI3sdhNRUob2MpOjptj2SYCTB4tXf9t0vc6+mB6Lr40RKXT
WS4wWCbVv8QZuDP5kQvvLaPNnPEA44BZhZ2DcqxunZvJejpBMMOMTx6FlKdovrBi
aWzKvN85Gjsa7gb4WUKxCPFTm2Ytl5+92squ/QAtDoKMT1AUcYGE4l9qgLNVhOHz
1pOY+JweeAHWcqUeYROh6x7KZ7mW7nSa4tIMsholOuebvn8OXinDZUgS7VaQtYDi
A/DGDwdhdSfuQal88BQeM4nSZ6Nixbd5ctFnN8SM+cBLV+x/ssgT/BP4x6xtcsGW
fBNdSmz7VvYQgY7e8ejDaXtokitZAtOFeWvssjZInjzfX6uo/uwGoXwQP2t7kYCZ
9S7jCRxDjilIJCh5medZHzfnXVRw5ywZKNb2qP6iKRYhLQ1KLsnDpPbMqujbCDWH
gFkws/YFvlKFnv5p/vp/dZFNCXSMGV+Pr30GSYSJCpUMlvKwhsuuywiQ26/rqGtP
DxfSK6p9cAq5Q4fl/xNN4q5IIs6UVrqhOr2flvK5qCUpeY1DzNrgFkun6sXqdAOl
wbajnzR1K0twmYaZTVFlTfJmQMM=
=VAh+
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY/tsACgkQmmx57+YA
GNnZSA//UglEJDhn9uyyuQMEgwpxFla3O1/iRQMKU/rojii8HLs8rypsJMr46KnV
Zl+jTeIUDH/VZX1Oz6dmV16X4c038he0hf5gDRJzq+5cOF5I/E/e4klsBXA49zhK
45f00RdtRPwD4m7wh9wcQ9kEmT8vNjDcu0E4m4NVVw4zohpiWKUxNjlg+rUNbDyo
K5rAPEVJpsOWGo9mf8W3rVZgtRwNVPKDjAd85MbEQZrCVeFR5cdugA9nWzbhX38I
ypZy5315pm7cq8ooFKV8I8pC+0pGJH5T1l0gb6kFAhuYhzonXkMTDIY/2+ggptGJ
9reTcJHo89Lx45uPJxgPQyAveiH5G1bDeK3bMIOWkVmuHXwkm3F8Tf8nihoMMPan
R9xWbmVTnHFPLOOeb9G6X9Bd1nO9mr/7HWXNxMubW9VTfZYCwu3GLsuAPbclT92z
J/Gu+VjWsveBZoqTK9tJImhpMtBx6bhykORfZf94ImXN9Jfx+CNl774xQyROXzrL
DJXzLSHgg5elvBW6gXy9gBHJqdhfu6yHsNQS/wE20g+Op2hVWvXmgOUI6XrJvw1l
WuqPD9eCpMvLKGJ0N9gMsuRmAiNGwtNmLMTozWOXMrM0QZ11hJkuHG6HXctrnWOD
edapidUssxPsm0upq+8S1CiGXuaj4qq1TDOaj1tSmrX6p0hf11I=
=4fl1
-----END PGP SIGNATURE-----
Merge tag 'stm32-dt-for-v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt
STM32 DT for v5.18, round 1
Highlights:
----------
-MCU:
-Fix W=1 warnings for timers (duplicate unit-address) for F4 and F7 series.
-Enable DMA2D on f469 disco.
- MPU:
-General:
- Add new board support: emSBS-Argon.
- Add dma configuration for all U(S)ART nodes and disable them in board files
when they are not needed in stm32mp15.
- Correct GIC PPI interrupts on stm32mp15 and stm32mp13.
- ST boards:
- Add EXTI support on stm32mp13
- Add DMA, MDMA and DMAmux support to stm32mp13 (iso feature than MP15)
- Update SDMMC1/2 support on stm32mp13: sleep config, update version to v2.2,
update the max frequency to 130 MHz.
- DH boards:
- Enable rproc to control the CM4 and IPCC mailbox to interact with it.
* tag 'stm32-dt-for-v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (43 commits)
ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp15
ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp13
ARM: dts: stm32: remove timer5 duplicate unit-address on stm32f7 series
ARM: dts: stm32: remove some timer duplicate unit-address on stm32f7 series
ARM: dts: stm32: Enable EXTI on stm32mp13
ARM: dts: stm32: keep uart nodes behavior on stm32mp15xx-dhcor-avenger96
ARM: dts: stm32: keep uart4 behavior on stm32mp15xx-dhcom-som
ARM: dts: stm32: keep uart nodes behavior on stm32mp15xx-dhcom-picoitx
ARM: dts: stm32: keep uart nodes behavior on stm32mp15xx-dhcom-pdk2
ARM: dts: stm32: keep uart nodes behavior on stm32mp15xx-dhcom-drc02
ARM: dts: stm32: keep uart4 behavior on stm32mp157c-odyssey
ARM: dts: stm32: keep uart4 behavior on stm32mp157c-lxa-mc1
ARM: dts: stm32: keep uart nodes behavior on stm32mp157a-stinger96
ARM: dts: stm32: keep uart nodes behavior on stm32mp1-microdev2.0
ARM: dts: stm32: keep uart nodes behavior on stm32mp1-microdev2.0-of7
ARM: dts: stm32: keep uart4 behavior on stm32mp157a-iot-box
ARM: dts: stm32: keep uart4 behavior on icore-stm32mp1-edimm2.2
ARM: dts: stm32: keep uart4 behavior on icore-stm32mp1-ctouch2
ARM: dts: stm32: keep uart4 and uart7 behavior on stm32mp15xx-dkx
ARM: dts: stm32: keep uart4 behavior on stm32mp157c-ed1
...
Link: https://lore.kernel.org/r/893924a9-bcc4-9fa9-4f8e-7f56e77f6854@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Few main additions include:
- Support for OPTEE based SCMI transport to enable using SCMI service
provided by OPTEE on some platforms
- Support for atomic SCMI transports which enables few SCMI transactions
to be completed in atomic context. This involves other refactoring work
associated with it. It also marks SMC and OPTEE as atomic transport as
the commands are completed once the return.
- Support for polling mode in SCMI VirtIO transport in order to support
atomic operations
- Support for atomic clock operations based on availability of atomic
capability in the underlying SCMI transport
Other changes involves some trace and log enhancements and miscellaneous
bug fixes.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAmIVQcYACgkQAEG6vDF+
4pgiLw/+NA01jx1VMNSUTCsSLvDQ0ZXCjEWEXaIR1KkdKELGu7wwItIqBSisXfmx
9/NBGBydz9q700NGevIjRDiBo6JThmDf/tTg21OdLvRY8Dwqfktz7JO4Jsne3cwW
hz1UTxyStUTNqt4Omprf1xzlKKerSuzav4KB1MtpAyzoBV6RFHglaznPCXL7mkic
9+9WPeVcwQxQ5ZXuwV2WDrJ9S8IZzMzZh6woIM/O4fdbyXGv28NfVt1oRidOPJOE
uMsxF/LcvUsQpQBOU9cTqkkmBCKRmzY7xT1JK58DcteSrleYoiZJqT7uFxI92i4Z
DqKMMUcbJVzKErBYyBHCA62cfRBvOV+OLhh8dzR2c40a+Ecoy5vQHGAEgMUwZBWx
8ztRDlBFzWxNSCyn5fh4IuV1POygrH8UTq57s+Mwr+hrr93Gb2JoxH3UL3kgGTJX
c9AFhLPNWDD+cwJouSD4y55kqik/53+vUqOrCHQkPjV4cz5Y3+P0uIraesh7NHo9
Mhnoudt7IZdJVowvEZyjQ4kp38t0G/M13BK/3Tw9EtlcFXoxOSP0AfLc1Il8nbRT
afKWVBfTZbxpTWnLsf5SkHXJgyO1tCEd51wZLqejWZqqwrhbNoqA+HyxdtIIvi1o
n5bS7qQ2wiuu3DsnJlYrJXTj2YlpUGm1MBHgmFUHtMUj55XpmEA=
=jIoO
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY/ksACgkQmmx57+YA
GNkNRw//YzZGhm0MtpPCe1jNv2bDWVq75v8bzDL217n9QJw1dpx0ru/xkDJDhmDP
t7vfSFFPfE2o/jXzMOuO8c6E1/b0cdxd9z8V1SPIHSwPXA/ZM4OdMKZJdwK6OK6T
HCW1PJJi+5ktu0mWbeflCW/isIQv0Y485yNH4q8gLSWisufevm+1LktErhNarQst
lG7CR9KclOZzqhVfT49vXhly/HSWVjUvYJfAPPERIQDwDvKSWjkx05ZPuc8l1DJU
8Z2164E04uTwU1p0154pmay9eY6xcBpTXhBkwFxwCfjKu0Yc2ViVRuGJh27x5TXB
ScAF7iRhjC2sk4v7H7UEFjVVAQix8aNyeueXcB1+6adSkCnerO/f4yT5uylbm7e0
Qj9XrqV1cF6GwE1ukRGa0hCySGH9xEz3No6ueEqCQQgbvVJ4o7RoUBoapnZUfx8J
ee/C4EHd/7uxBm0ygQ07F1+RbLeWw6aLSVeM03bY+bz9LKkPxELrgP98WLvvGtzy
Xj6k98DMdmZsCwcp3Z4va9gjopjgM4Z7pWnABihXEkidZXGodMMAQCAUU5gmZeKz
FSubYgjrGojOy00XOQsggw+CmNHLGNvQoFLjaRtRxHLJYewyjuE7zCcSOdqTsjI4
BKEUgtakDEEFoSA27ycjne23VyhxI3mF3yC8LBiAkzbksuMQXvA=
=qTGM
-----END PGP SIGNATURE-----
Merge tag 'scmi-updates-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/drivers
Arm SCMI firmware interface updates for v5.18
Few main additions include:
- Support for OPTEE based SCMI transport to enable using SCMI service
provided by OPTEE on some platforms
- Support for atomic SCMI transports which enables few SCMI transactions
to be completed in atomic context. This involves other refactoring work
associated with it. It also marks SMC and OPTEE as atomic transport as
the commands are completed once the return.
- Support for polling mode in SCMI VirtIO transport in order to support
atomic operations
- Support for atomic clock operations based on availability of atomic
capability in the underlying SCMI transport
Other changes involves some trace and log enhancements and miscellaneous
bug fixes.
* tag 'scmi-updates-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: (28 commits)
clk: scmi: Support atomic clock enable/disable API
firmware: arm_scmi: Add support for clock_enable_latency
firmware: arm_scmi: Add atomic support to clock protocol
firmware: arm_scmi: Support optional system wide atomic-threshold-us
dt-bindings: firmware: arm,scmi: Add atomic-threshold-us optional property
firmware: arm_scmi: Add atomic mode support to virtio transport
firmware: arm_scmi: Review virtio free_list handling
firmware: arm_scmi: Add a virtio channel refcount
firmware: arm_scmi: Disable ftrace for Clang Thumb2 builds
firmware: arm_scmi: Add new parameter to mark_txdone
firmware: arm_scmi: Add atomic mode support to smc transport
firmware: arm_scmi: Add support for atomic transports
firmware: arm_scmi: Make optee support sync_cmds_completed_on_ret
firmware: arm_scmi: Make smc support sync_cmds_completed_on_ret
firmware: arm_scmi: Add sync_cmds_completed_on_ret transport flag
firmware: arm_scmi: Make smc transport use common completions
firmware: arm_scmi: Add configurable polling mode for transports
firmware: arm_scmi: Use new trace event scmi_xfer_response_wait
include: trace: Add new scmi_xfer_response_wait event
firmware: arm_scmi: Refactor message response path
...
Link: https://lore.kernel.org/r/20220222201742.3338589-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Drop LS1021A device check from soc-imx driver as it's unneeded since
commit commit 4ebd29f916 ("soc: imx: Register SoC device only on
i.MX boards").
- Add support for power domains provided by the VPU blk-ctrl on the
i.MX8MQ.
- Add resource owner management API which will be used to check whether
M4 is under control of Linux.
- Add VPU MU resources support into SCU power domain driver.
- Support DT overlay for WEIM bus driver with OF reconfiguration
notifier handler.
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmIUirsUHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM54UQf/UzYym4Y/Clur4F7xh4XodaP6Y2fF
M7DJUcE7rkI4jHCASnyh7NwSdqLCBiXOa6GVMpagELG8qoMYV/Gcwdt2Q60tn8TM
ASADkSKobjDF7hywQpGQL9808QTKglRwgVBnTgeKaUrjE1Lw0gebgM9qoisrUzjk
wwQxnUdyNxkeCOw5743z28H+lJmC8j3EecD+mjN6DiqCJYIMacQQ3+7S0pyHq2ii
TdaV0oi4ApannwlxcguqYDDgwX7VXxnguPmGVIHc8Pq+zqmbCTfcaUbRTwlYX4PK
5CCb+2sN8v0MYxKH5elYuUoMQeTZ2w7IeK99JDoCNueNbIbK6G7wndHfdQ==
=m1lO
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY/kEACgkQmmx57+YA
GNnOZQ//U4XOr+yZA5csefH0z3LDKuQBFVuM6w2pXw8sdcC84X4BFlRjJNeam8jT
LqS5t69nWJaN/1qny8MeX5lBk7rqomRs3iVizKR6AP6EsKw39F8i89U0eD7ePXiQ
dKkio4lL8w4WuOnNwoaY7eElh+jP+gYftnv8GVAmjxSJkjBTAM2HtQjFdg+G+5kn
UOCkdq6/goyvA54oq+MWfn+sSXHOyPYN4kyndb87sWnTNoLeGzklFIm4uTeG3A+e
716vS9sm1CZZrSB2FLxMffY/VDgQBLFZPU/fqgbetVQA2+cyQH+YHPSFdHs+eTje
KqtjuKIRs1zuMy2jnSDS7KIj9c9JtNJtJJG2a0bskom4z3lG/yXfnmbQEJgj82jI
T54YwM4h5MQlzznduQcyk3F3vhQssqauBjC/KIIw4TpP4qlDOpFls+v+8KNtDaDK
Znk5j3gzX4H2DvWxE3OoQePCCx7LKvM5pgRYZffrHvaVIFUlAykDhjNuGI05+Wdh
uAXeTqFmWxQ9iPy5M3zQh1i3cYIKhEE+4plO7lRFDbFny4ylQDcKR+fKtVmDzmN+
JcYHpdcy9PTzGIf/9qiDQHSEGcvalPBwlGy7kUTewT0t+yvUTqG1EJz8ndgQL7f6
4wCHShGVTD55gp2OLszeFsvHae5UoPvDornryNS9pB1KCAbzbSg=
=N5wZ
-----END PGP SIGNATURE-----
Merge tag 'imx-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers
i.MX drivers update for 5.18:
- Drop LS1021A device check from soc-imx driver as it's unneeded since
commit commit 4ebd29f916 ("soc: imx: Register SoC device only on
i.MX boards").
- Add support for power domains provided by the VPU blk-ctrl on the
i.MX8MQ.
- Add resource owner management API which will be used to check whether
M4 is under control of Linux.
- Add VPU MU resources support into SCU power domain driver.
- Support DT overlay for WEIM bus driver with OF reconfiguration
notifier handler.
* tag 'imx-drivers-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
bus: imx-weim: add DT overlay support for WEIM bus
firmware: imx: scu-pd: imx8q: add vpu mu resources
firmware: imx: add get resource owner api
soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrl
dt-bindings: power: imx8mq: add defines for VPU blk-ctrl domains
soc: imx: Remove Layerscape check
Link: https://lore.kernel.org/r/20220222075226.160187-1-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- The TEE shared memory pool based on two pools is replaced with a single
somewhat more capable pool.
- Replaces tee_shm_alloc() and tee_shm_register() with new functions
easier to use and maintain. The TEE subsystem and the TEE drivers are
updated to use the new functions instead.
- The TEE based Trusted keys routines are updated to use the new
simplified functions above.
- The OP-TEE based rng driver is updated to use the new simplified
functions above.
- The TEE_SHM-flags are refactored to better match their usage
-----BEGIN PGP SIGNATURE-----
iQJOBAABCgA4FiEEFV+gSSXZJY9ZyuB5LinzTIcAHJcFAmIP5coaHGplbnMud2lr
bGFuZGVyQGxpbmFyby5vcmcACgkQLinzTIcAHJdLQg/9F+9wtUsM3sJAitaB0DN1
tTd8Iwt0Ir8khuac56/pMcVlFF1dwBAFy5vnAKKSGF0nzToyEhOc4uRsOA0vvQ4s
EtTX7ONuHjPR18faxJbtLHPl3tSjGxkwtrBo5IvCapxaYsJK8x2XEamr9ih7r5nZ
KwSTNgiGZ+WM+IgwgZIFfOoB4pXnkQZAf2UBAdK2W1dVpIOoJzLpiS28DNgA08C5
sUduKi2GvmaieTqu6QHY2FJNRAVgYrzuyXIgfQ+Kjsa/GDMZ6CS9DB3BBt1D4xyM
OzIl4/Y2nZqJ6EFhuFtWIQIuMLlw0HiM08d/PC4vW05EwKmeJ5zTs+I9nJQEnPKN
n4SfwqKIIq5KeYeT0ByVuGwm/JET4YXvL3d9EqkDtFAwnkT0Jx7o5GgFQbj1+0Z9
RvmWWy7VFPRhvLGsPpkuJnGc9rD4XVtzFw92K1VRmarQnjQFmD2y7DvNEEXokLCv
Z4GV3bz7ntmURJsOoMpt56i9WboXkjFmsaIqg09ShPRC9EB+9RMvRNEwE72FZmlH
RIMl5Vx4SkYbY1FlaiJ9BSctcdQD9HES17D5z5l6Im3JjMbFeKvLLQCJ/Ch3vxNj
OujRhXsEO2g9uUXwh0OveK8mEh3bz+GE/uj+c7xZXb95ImswyK9fo9uLvG+Z6JVk
n9+xgsKUZlHwHkoofuXor4k=
=xOBv
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY/jcACgkQmmx57+YA
GNk94w//VHkLJADLSqwh8AZXUwpBN3nCKtsEay7HbRmC9Nh4Zm/TQyYx79QmRnnK
kDxLVAFTapFLxQVo441jPfnjp2cSW0Oomhv3zLIPNE44Gb0jF+hqfbN3sLJLk5hZ
EiiRxnMEJ6KCbvLEXaSUqRfGoYkU98HF6vNzN0nme6Zq9f11GO7RsUGL1nLNrU7R
mGj4O1hr6QVWMCY5vvEYLkGZFj54jVb64UVYzmyw8Nt5IIbY2upCQFoeQYHtiIle
h354Wn3PgE+txzSKGGH0dw9hq2JPNFSwmx3psvw+9HUjYXGC8rfaJeRNTEC9oIaC
ALXqNnnu/kkhKt6rfkVaVuJFjefn/WjTCfEFyCRblwmNdi+DZfkcCkDh0Tj/4F6X
/hoLYC4XXt+bxvdi8I6+xH8ho+Zwsh3F9WXWAU+p1fR5/kOTpvYe10k+59lK+AUK
bbPCN2WQ+IB66Mt8OXAVRycXKrbGU32QTioWF7Jv5/ZgF1aTeAnzyoRnT9OI8FMz
sxqSNd/Lasc8czP+xdTrfisOy+7vRfSOPDgZ4BUVQLAZIDmuqiJo3Rtu4J72aZx2
Pyk680b3iGKORBGVFznF8DOWxNdbUbuQFxUzIGGKHtsy9++fyZzrwtjASmT9Bzef
ec6FVInEKt+f6nuMUZrMWRaWIZw3KGqWRnkX47k86PsCAh3HDvo=
=0vIF
-----END PGP SIGNATURE-----
Merge tag 'tee-shm-for-v5.18' of git://git.linaro.org:/people/jens.wiklander/linux-tee into arm/drivers
TEE shared memory cleanup for v5.18
- The TEE shared memory pool based on two pools is replaced with a single
somewhat more capable pool.
- Replaces tee_shm_alloc() and tee_shm_register() with new functions
easier to use and maintain. The TEE subsystem and the TEE drivers are
updated to use the new functions instead.
- The TEE based Trusted keys routines are updated to use the new
simplified functions above.
- The OP-TEE based rng driver is updated to use the new simplified
functions above.
- The TEE_SHM-flags are refactored to better match their usage
* tag 'tee-shm-for-v5.18' of git://git.linaro.org:/people/jens.wiklander/linux-tee:
tee: refactor TEE_SHM_* flags
tee: replace tee_shm_register()
KEYS: trusted: tee: use tee_shm_register_kernel_buf()
tee: add tee_shm_register_{user,kernel}_buf()
optee: add optee_pool_op_free_helper()
tee: replace tee_shm_alloc()
tee: simplify shm pool handling
tee: add tee_shm_alloc_user_buf()
tee: remove unused tee_shm_pool_alloc_res_mem()
hwrng: optee-rng: use tee_shm_alloc_kernel_buf()
optee: use driver internal tee_context for some rpc
Link: https://lore.kernel.org/r/20220218184802.GA968155@jade
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Someone on IRC once asked an innocent enough sounding question: Why
with xf86-video-modesetting is es2gears limited at 120fps.
So I broke out the perfetto tracing mesa MR and took a look. It turns
out the problem was drm_atomic_helper_dirtyfb(), which would end up
waiting for vblank.. es2gears would rapidly push two frames to Xorg,
which would blit them to screen and in idle hook (I assume) call the
DIRTYFB ioctl. Which in turn would do an atomic update to flush the
dirty rects, which would stall until the next vblank. And then the
whole process would repeat.
But this is a bit silly, we only need dirtyfb for command mode DSI
panels. So track in plane state whether dirtyfb is required, and
track in the fb how many attached planes require dirtyfb so that we
can skip it when not required. (Note, mdp4 does not actually have
cmd mode support.)
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220223191118.881321-1-robdclark@gmail.com
Signed-off-by: Rob Clark <robdclark@chromium.org>
The kerneldoc for usb_get_dev() and usb_get_intf() says that drivers
should always refcount the references they hold for the usb_device or
usb_interface structure, respectively. But this is an overstatement:
In many cases drivers do not access these references after they have
been unbound, and in such cases refcounting is unnecessary.
This patch updates the kerneldoc for the two routines, explaining when
a driver does not need to increment and decrement the refcount. This
should help dispel misconceptions which might otherwise afflict
programmers new to the USB subsystem.
Signed-off-by: Alan Stern <stern@rowland.harvard.edu>
Link: https://lore.kernel.org/r/Yhjp4Rp9Alipmwtq@rowland.harvard.edu
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The list_entry_is_head() macro was added[1] after the list KUnit tests,
so wasn't tested. Add a new KUnit test to complete the set.
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e130816164e244b692921de49771eeb28205152d
Signed-off-by: David Gow <davidgow@google.com>
Acked-by: Daniel Latypov <dlatypov@google.com>
Acked-by: Brendan Higgins <brendanhiggins@google.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
list_is_head() was added recently[1], and didn't have a KUnit test. The
implementation is trivial, so it's not a particularly exciting test, but
it'd be nice to get back to full coverage of the list functions.
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/include/linux/list.h?id=0425473037db40d9e322631f2d4dc6ef51f97e88
Signed-off-by: David Gow <davidgow@google.com>
Acked-by: Daniel Latypov <dlatypov@google.com>
Acked-by: Brendan Higgins <brendanhiggins@google.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
The list_del_init_careful() function was added[1] after the list KUnit
test. Add a very basic test to cover it.
Note that this test only covers the single-threaded behaviour (which
matches list_del_init()), as is already the case with the test for
list_empty_careful().
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c6fe44d96fc1536af5b11cd859686453d1b7bfd1
Signed-off-by: David Gow <davidgow@google.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
Make sure in .probe() to set driver data before the function is left to
make it possible in .remove() to undo the actions done.
This fixes a potential memory leak and stops returning an error code in
.remove() that is ignored by the driver core anyhow.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- sama7g5: CPU idle support with CPUFreq operating points defined in DT
- polarfire: addition of the soc system controller
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ5TRCVIBiyi/S+BG4fOrpwrNPNDAUCYhjItwAKCRAfOrpwrNPN
DDLmAP9CKK9j0y3YEs69vXYO4URTc5FrpRdZ976mHZdvl5ZJpQD/SK8k/AZhVwsV
OUMN8zosXY0TiCRjsaLPq6MK9Nv09QA=
=alh4
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY9zUACgkQmmx57+YA
GNltxA/+KgPQWmNQ3sPfkGq+rbCMof3misxS41OL64VUyT7VFau9nZeyJ7m8Vc4X
CudkmTO39IgYLOcy6l51Pq8zeZ8jcMEQPntFo6fQUimo5slZQBNVuHnnCiWjpUdh
eOQe5KwQb9fHPW/vMN0zKafckkVQXELo88ol54SorHqDwK/LU/s8iYYsUXByMJoa
mxrZvg8/pXmQ+yyo1lpID0VfN+nWmOq4LVwSniF7z88M+J/H6R/A+KLqOoEyKvUN
1wawBdKHqmH/BftMnGP6oqFVFeOgH4BhMLPMSLp09rO5isx6vgPhWXvGh0PfL/+9
hUaOE+Hr7j33Yuxow97opx/Q0z+pqT0nyENq7/3cZpzB8V+WVJNFQeZ4Pm2A5jis
NLRhm+V9gnRd8usZeepa8uvywo1aZHE2T14VcFffSPqgkOONyDj0V7DEP3gfZicA
ezYIbUFHqU2hVsEmnxzXNDrvdUmI3yv77mK+1QXE3HBdd8DLDzpNOdzXED1ENf9p
j2vBUX4XCiQVxSBbhA8ILKEh+xCUHDh6ZUMnMzQwy4hxa2RPfFPscr+m/YURDb8A
EIfvG0qtBIe/CsVrD8XfhBTyewhFQKWxYUSDz0nl9OWhr3+Q/6yxJSSvAQoD40tS
rYuS6JFDIJdB+wjt2Q6adR4xpCnEkfDL8ysWiYPMnTQ/mnmu2hg=
=VBoe
-----END PGP SIGNATURE-----
Merge tag 'at91-soc-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/soc
AT91 & POLARFIRE SoC #1 for 5.18:
- sama7g5: CPU idle support with CPUFreq operating points defined in DT
- polarfire: addition of the soc system controller
* tag 'at91-soc-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
soc: add microchip polarfire soc system controller
ARM: at91: Kconfig: select PM_OPP
ARM: at91: PM: add cpu idle support for sama7g5
ARM: at91: ddr: fix typo to align with datasheet naming
ARM: at91: ddr: align macro definitions
ARM: at91: ddr: remove CONFIG_SOC_SAMA7 dependency
Link: https://lore.kernel.org/r/20220225121943.71494-1-nicolas.ferre@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
All of the SoCs that are supported so far are Cortex A7 r0p5.
So it seems like this errata is present.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Romain Perier <romain.perier@gmail.com>
Link: https://lore.kernel.org/r/20220223064807.261878-1-daniel@0x0f.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add initial support for i.MXRT10xx family which features NXP's
implementation of the Arm Cortex-M7 core and in some case the
Arm Cortex-M4 core too.
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmIUVkYUHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM7IMwf/ch9nwSrW6lLdypPqQzs80fd7JVtx
kZFeHrjxePtP2fhcPhT9PcJW5nBDmGkoxpuwbfTFjvm/UxMcBVIYfShk6Rposrcv
hhnnCA3gx1bdnGVYTTv3d/5fAXVUoIbE8UsWLM1eOrJ7KNbevpC5353cuQNytTSp
+P+wt2hHweuTDmvPRmDY6QJndM6rBwKqZ5a7Rd5pqRzGs7mMwr5cMvWMjecM50Ni
FOQYt3YmLClQXyHBBhHBog72JVkNw65NR80o/bhdDIAXwXFqReABnToWFmoS+jwd
jWif4Ibhq7DNNfxt+HRMT6mwHOViDl6VxzPZ0TvGnULb1YohMuwPmeM7cw==
=kPTp
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY9vAACgkQmmx57+YA
GNnwshAAlfT3kDGwTXSKhwDtoFB+4hD6iiQfM0bO9sRoNES/LoyJEMD/RrZmB1Yv
ZdZr3ghDPrNUHqOzhDNLnKznE+cVOPQgcE8LgoQxOspHpSN7YvCsh2nsgzWQyzQG
LkRCdHEbqiVpmGSaNPsicvVfHTIAqwBkO+ToJw1mJ/6o1Fz31Ll4Qjy3LqbcIsNW
84T2TkWZRTAGY9XKKMTJkvCZ5IVhsNtlJNM+1lMs+UvoERORpOPcYoTSjQW3ALX9
OtgOBM0u6NOeuaUX0l5MZDNurHze0D7l8QMeUSeRUnQF8KCXxnV2tS1hAh2JMD1k
8N0xmd0KB0+/OBEGF4AXTHj8anL7gQMUZxEM/geMHezlfSU8gJJ21tweRUFJRKD4
EcUCsIOrEjnhdztOznYNzpz4NrsgoZuRkRfTOpnbn+inhRmhFbp0g55wsdjtAFUg
TYzDN6amrj6FdjHHJDQ0X6NGkkpM5Wu2bS3RrZuiuaKerw2Ulyyv3bOJ/9Dv+H0t
V+yLECGAMW9qeYw2cD3ZxiRjD+3dqV7BrpUMLljKUcApVf0uGoRaHALxHwT70HSu
h3GpINmM751dcxPbNi6BJFi6TH7v+58ulsF+nZERyE+NA5UIUip0pnDeQlOQzJTZ
lt+1Cjz6zSe3OduKrbRgc61CfcAUWU7Lpwep0RC3gM3XofktWFU=
=tki8
-----END PGP SIGNATURE-----
Merge tag 'imx-soc-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/soc
i.MX SoC update for 5.18:
- Add initial support for i.MXRT10xx family which features NXP's
implementation of the Arm Cortex-M7 core and in some case the
Arm Cortex-M4 core too.
* tag 'imx-soc-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: imx: Add initial support for i.MXRT10xx family
Link: https://lore.kernel.org/r/20220222075226.160187-2-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
makes it an exclusive device tree subarchitecture without any
special weirdness in arch/arm/mach-ixp4xx.
The biggest noticeable change is the removal of the old PCI
driver and along with that the removal of the special DMA
coherency code and defines and the DMA bouncing.
I tried to convert the IXP4xx to multiplatform on top of
this but it didn't work because IXP4xx wants to be big
endian and multiplatform config creates a problem like
this:
../arch/arm/kernel/head.S: Assembler messages:
../arch/arm/kernel/head.S:94: Error: selected processor does not support `setend be' in ARM mode
I think this is because MULTI_V5 turns on CPUs that cannot
do big endian, and IXP4xx turn on big endian. (It crashes if
I try to boot in little endian mode, sorry. It really wants
to run big endian.)
But before fixing multiplatform we can fix all of this!
The networking patches are dependencies so I am requesting
ACKs from the network maintainers on these.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmIH7KsACgkQQRCzN7AZ
XXNGDQ//dfQIiKC0uE4UEbKeDG18c1NpSDHomQQ/xGjnl9nenmOzsqg9pu+hrD+y
eHNp55PmL8WKjXYV8wrbQd65BsnMGpiIh4CoT17BOM0vjQ7+l0KM9FqCuYTIXkyE
+AR8ZbOYZDSNZA6bKCy8dT1tYZakx2IK02YEphiAU2hPsvWYTE2VTDSYzskbW7pu
+aaCzPOnteQZM4cRMPDOmhq9FedaCnluom9ldTei0nEkFuDi0v947zUVs8M3o7gi
rsZBRxfXlY86G3b8WdqL0jCcrsWsnLnP6TehSH7r/TbsFlzdv+GQpfZ8craDpTTW
X5zhUQYreAYNY88Vy1UoVSci6BSJF/c8Q75lcLOcIuf/XX6ufyTO1YHDXxxSm04P
1cjunZzJs/YGx2dDgVfzSIXTBCMKovZcUVI5FfEP36wW3RA1WSa4cdWnI9alwlp4
yX7AtOtbxIZ2jiNQMV4qx9Yz8SzlVWF7E63S16XAiFWr8BQex1Lmh2u5BZLE03XW
k9yl+dhqmTf+MlHS7y70KdwxY0XvJNZiHoCEIA2A0B7ayvl9ThkXOWOkYBZLb0hq
SmlIHJkRyFLNxtVTvadq3S8fa1haS9qTONwfS7KCkCPp8XpE4QCDCEAOK9EK0tCS
p4SRGKD6SpoqEZKVItacGfLLAjJeGt6kIDBdRJ0J/nASVgcvaT8=
=DMVU
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY9nQACgkQmmx57+YA
GNkM8RAAqwYUKHl1pkAnTBU60aW9dWJpNdyIej22sdi+FcsGcF4tC/RQ+Zssl0VD
eMvAM295eGZDb02B0f8EbPQHuDEp7Y9mpC+9QjoBCLCojho15ise3cKmyloG9/7T
xo1J99lY/PW7ociVXqO4rZtWsplgy+FB3X+cCsk/UziwsF+HqjSSOi9VsEkHsBHI
sJwDE90YetuC3S2+5/G9z2JbuqNchGebT66ZE13CGGBLb1cKBNMb2L1ZjwRlbhUK
tYPBaTBnwJApLKoTQx4HlpAei5XROEB/3qxPH4e4RnW8MZyG7+ZNXnkIuZytJxVc
zt5Qols2bLakHms0QdZhpeinvqPV4c88xGCZryQRHqbU1VLfygFFuoqnDfn/l0vW
KWceaSMeL5EpvE+1sZsP7EcQn5AhCKckWoaL3TRJzeR/0JJswgBMMSBYof/eSP4u
jJX+NBid6Hjred7B12QBFYc7L3LCDcmFmQM9LYa7IciedRx3fqw9yNRXzBVgTUDC
t/cuLn06uLYTbn5fNnxxRvvDkLnXtf8OyzER0fy+Dm+terjIMATK3iQ0bGvwj46Y
sQ74A7mQ+tsosmS+SEz79VD3AuzCqm3nfFTeU8W0QUj3IK1zqWKEjmJpeeniuL8L
QBP7ZR8wlytfwq4fm2gI3wss1gFw8GYcJlkPhBAuHjMisiFWl10=
=blMU
-----END PGP SIGNATURE-----
Merge tag 'ixp4xx-cleanup-for-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/soc
This cleans out the remaining board files from IXP4xx and
makes it an exclusive device tree subarchitecture without any
special weirdness in arch/arm/mach-ixp4xx.
The biggest noticeable change is the removal of the old PCI
driver and along with that the removal of the special DMA
coherency code and defines and the DMA bouncing.
I tried to convert the IXP4xx to multiplatform on top of
this but it didn't work because IXP4xx wants to be big
endian and multiplatform config creates a problem like
this:
../arch/arm/kernel/head.S: Assembler messages:
../arch/arm/kernel/head.S:94: Error: selected processor does not support `setend be' in ARM mode
I think this is because MULTI_V5 turns on CPUs that cannot
do big endian, and IXP4xx turn on big endian. (It crashes if
I try to boot in little endian mode, sorry. It really wants
to run big endian.)
But before fixing multiplatform we can fix all of this!
The networking patches are dependencies so I am requesting
ACKs from the network maintainers on these.
* tag 'ixp4xx-cleanup-for-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: ixp4xx: Convert to SPARSE_IRQ and P2V
ARM: ixp4xx: Drop all common code
ARM: ixp4xx: Drop custom DMA coherency and bouncing
ARM: ixp4xx: Remove feature bit accessors
net: ixp4xx_hss: Check features using syscon
net: ixp4xx_eth: Drop platform data support
soc: ixp4xx-npe: Access syscon regs using regmap
soc: ixp4xx: Add features from regmap helper
ARM: ixp4xx: Drop UDC info setting function
ARM: ixp4xx: Drop stale Kconfig entry
ARM: ixp4xx: Delete old PCI driver
ARM: ixp4xx: Delete the Goramo MLR boardfile
ARM: ixp4xx: Delete Gateway 7001 boardfiles
Link: https://lore.kernel.org/r/CACRpkdahK-jaHFqLCpSqiXwAtkSKbhWQZ9jaSo6rRzHfSiECkA@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- lan966x basic DT and associated evaluation board pcb8291 (2-ports)
- documentation for an upcoming Kontron switch board featuring a LAN9668
- one fix for an old bug we have with PMECC on sama5d2 in some corner
cases
- sama7g5 and its EK: crypto, CAN and DVFS operating points
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ5TRCVIBiyi/S+BG4fOrpwrNPNDAUCYhi3WQAKCRAfOrpwrNPN
DOTGAP9y9/HV8EXrGhm8ZvH0ScfIkf3cPFyoFKtcN4EFNKb12QD/aSjSW17XEwTt
L+RYm2x2lha8eVUteyRpZXZqmK8buwg=
=3qii
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8xQACgkQmmx57+YA
GNmEyg//ej6i6g/4dVcG1TQ+Fm4zSm19HM338FduYw2esH0P6pgUKG+V6sOBaFWF
m2HaHPTsbaY90mshpym6rmC22UwEsdw64x5Z4en20NRrdLBjraVzLltz8UhLAEH2
+/pjw0CU/CxRE1z+OItfdElg3+HyJuPyF7rjXXCsM3DIMZzOR8CEXO9tt+K2EJKQ
LgO5cz4a0lS6a0FUdXivq1jzRmQW2sUzvA+7XQ/KKczxLiNzgVWD92ysua9pzoBp
a1eOrpr9BD2PpYawLlBQB995NjRCvgCf4P8QJDbjrOpfmbM13AqFi4Yk7LbKIY+d
kvqp7Ru9Zbbvg7WW276jQOMbD53/AkmJEaomKsEJeazpvOOiDnMKsY5y0PZ8Ma/f
+HSjAoXUSGw1x3+o/Ai8LlnOU6SXYo95OgmEz/KOpw08lBOkyWT2jSWEF+7bLHDg
zw0vUQESSNsGMlfH1xWit9MLqlyr/WanAhQW3CKvsFfd8IEEo7dcA/djjWsTVgiS
R5F9qJwq5/MLpxSESRJrUiVg5zBALEToHAdL+TsRD6aU0yBhsawaPQG2vWtCOdTw
GIzY4GdYMo3izMDNaxcf+/ku/AjuCzTJGO73BKGrrY/e9Rk3vTBlNTp7FGBRxpb5
tu+X2uyXu8cMqzHcO/UYX7WN9OjVSIwFhS2Hf/3joK8ETxGpyy4=
=+JfK
-----END PGP SIGNATURE-----
Merge tag 'at91-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt
AT91 & LAN966 DT #1 for 5.18:
- lan966x basic DT and associated evaluation board pcb8291 (2-ports)
- documentation for an upcoming Kontron switch board featuring a LAN9668
- one fix for an old bug we have with PMECC on sama5d2 in some corner
cases
- sama7g5 and its EK: crypto, CAN and DVFS operating points
* tag 'at91-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: dts: at91: sama7g5: add opps
ARM: dts: at91: sama7g5ek: set regulator voltages for standby state
ARM: dts: at91: fix low limit for CPU regulator
ARM: dts: at91: sama7g5: Enable can0 and can1 support in sama7g5-ek
ARM: dts: at91: sama7g5: Add can controllers of sama7g5
ARM: dts: at91: sama7g5: Add crypto nodes
ARM: dts: at91: Use the generic "crypto" node name for the crypto IPs
ARM: dts: at91: remove status = "okay" from soc specific dtsi
ARM: dts: at91: sama5d2: Fix PMERRLOC resource size
dt-bindings: arm: at91: add Kontron's new KSwitches
ARM: dts: add DT for lan966 SoC and 2-port board pcb8291
Link: https://lore.kernel.org/r/20220225110735.18080-1-nicolas.ferre@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Pin control support for the R-Car S4-8 SoC on the Spider development
board.
-----BEGIN PGP SIGNATURE-----
iHQEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYhjYwAAKCRCKwlD9ZEnx
cKSXAP0aBTnnmwZauIy0QIa2YGrGAqaiU1q++b0LV3iygbinSwD46Goz5adJeXrZ
+wta4wt82uakJRUdwouY+wBR4bPODw==
=kgbD
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8vEACgkQmmx57+YA
GNn3OQ/+IhJ3AtsNRjl2YK5jBsXggax+Af4lVyB9ihBDN1HyWa1y2QjMRFcBmviY
Q/F+OdkyXNi6bUESDC7oCeZRqrW7qcw8gjy6ItPPgQC7UfUeluBxVedxbw+y7Mvm
8zwca6UPjOw4IdJgwCMVslSvqZnoiuUjJFacYQ6k/l8JBeKiuPDytgwx9tG0BXkV
Dps71xdxScpp55KyLYqU7MR3j9f6VtnP/46rdTs+xecRoASElrsXxojt0R6NLufg
7rtKoFzLNXHDR9L4xJNNgWVoq50OCK4nsZSFk6LZVQmMgpwTzA2V4zGEeWqLZsMw
Mey/RV7rG1T1YR3BY038BIaqJ+TnCbLXgp2TaEa6vgE4P8FyswobPRDZrzaVPSIc
gY2GrpmtonuIol7Ew8NSe9Mj8EbxPva95S3zK/XFdjHvb/9nG5hRaoN6dDEiF9ln
JTD0eWL5j9cPuzUtann49lbPhljnRjwRLWu42Sz1LQvpyHbNQPr+B6jehhJj7Flp
XVvSM3kczoEXEz4dzSqAo7SRMC2QC06luv5KO8J2uxwz3QYQo/1FEDxzM9Y11mZx
8nEeh4c/bWJ9b1Ob+PkD8P63uzizEYXeaMq7MrBXhNRoZGthga6QbiSlt0bv8B7m
iYCsEnzueJTz5X/70P5uYGltiQtQ5k2HHvFwA/jf1YrNEM4JIT8=
=61Bh
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-dt-for-v5.18-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.18 (take three)
- Pin control support for the R-Car S4-8 SoC on the Spider development
board.
* tag 'renesas-arm-dt-for-v5.18-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: spider: Complete SCIF3 description
arm64: dts: renesas: r8a779f0: Add pinctrl device node
Link: https://lore.kernel.org/r/cover.1645795643.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Document the use of the renesas-soc IRC channel,
- Watchdog support for the R-Car S4-8, RZ/N1D, and RZ/G2LC SoCs on the
Spider, RZN1D-DB, and RZ/G2LC SMARC EVK development boards,
- Miscellaneous fixes and improvements.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYhiomwAKCRCKwlD9ZEnx
cHPXAQDNxh5Fr/t8POQlZRhXr/qw9vSkP/bslbLBXIxQmtTuiAD/QOwd02UBun5Q
ei27RcXBOmzpxJBD281LL2fF560h9Ak=
=gcXB
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8lYACgkQmmx57+YA
GNnvkQ/+KA3wN4WIuWG1DfkRh3wOL06EtIlbMTomH7IGvPkPVI6s5lYgPN85pWOb
Sq50/TRTX+Lo3wU7bHWm6D4uik2i7haeFLXLnMm4p020OggqZlFlIStIg2AcZ4Mb
Xu4NFHKlBEelNW4r5lgWpVwpfX37NJb5dY/ZX/oW8fNzTGufGGN/QHLKXzyIpw09
gWTL6d9EIiY6up79mX48RHQ/lLjNLs/8Ae0nnmtHRp3268vGUaUhI1ybzKdAWfsg
0pgAk2bF5oPxpkMDe4/0cilB/BDHF2TRgt8/yXXJZ34EQTXciKu/Zi3n4CmViAHr
aPm9pF9SFFuiTS0PyeY9fyj3gjb3/vj0h6Slyr/U7b4YchdVJ+wLduued3hr0tJt
3LBKtAtxgc0EqOxf772UtWcd8ZPfDH0nJnAbEotZV7y03VRWK/eKgwIQ/j5kc9go
rSZ6Gc/2YeexK5nPSxir0XDelQjVDSRo/yDQmoSPvduUJrga1N4p1MVLSGvmWimB
o/oISmNVvl868/kMTmv9RwZlmULMAgjIqQ2yrwE1kCc2x0p04aWFRoYv7e++GG3M
tK/TvodD4BvjTDVPUMrG7Az5QPjMs8QbLIIGjulGcxwPlRW6tn09Eha+qTcA4X5o
tpyk5zPZDkw+MdixdjuBCkrD8Y6yFG7foRf6Rmnhqh9oClQmplk=
=WR66
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-dt-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.18 (take two)
- Document the use of the renesas-soc IRC channel,
- Watchdog support for the R-Car S4-8, RZ/N1D, and RZ/G2LC SoCs on the
Spider, RZN1D-DB, and RZ/G2LC SMARC EVK development boards,
- Miscellaneous fixes and improvements.
* tag 'renesas-arm-dt-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
ARM: dts: renesas: Align GPIO hog names with dtschema
arm64: dts: renesas: Align GPIO hog names with dtschema
arm64: dts: renesas: rzg2lc-smarc-som: Enable watchdog
ARM: dts: r9a06g032-rzn1d400-db: Enable watchdog0 with a 60s timeout
ARM: dts: r9a06g032: Add the watchdog nodes
dt-bindings: clock: r9a06g032: Add the definition of the watchdog clock
arm64: dts: renesas: spider-cpu: Enable watchdog timer
arm64: dts: renesas: r8a779f0: Add RWDT node
MAINTAINERS: Specify IRC channel for Renesas ARM64 port
MAINTAINERS: Specify IRC channel for Renesas ARM32 port
arm64: dts: renesas: ulcb-kf: fix wrong comment
Link: https://lore.kernel.org/r/cover.1645784466.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
New peripherals for the rk356x-family (pdm-audio, gpu, another i2s, usb2)
A lot of additions to Quartz-A (connector-header, gpu, sdmmc1, io-domains,
usb2) and rk3568-evb1-v10 (rk809-audio, cpu-regulator, gpu, tsadc, led,
usb2, touchscreen).
Fixes for the pwm-regulators, that used wrong names for their supplies
as well adapting the cros-ec pwm nodes to a changed binding (going via
the pwm tree).
And as sort of misc-changes, defined the logic-regulator on rk3399-puma
as well as enabled the mali-gpu on the rk3399-firefly.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmIX+P8QHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgfZLB/9DUe9pJWRo7zg3GENlp9d3slQBJkBWHF4h
SiYheGDbQyfWmPeH4PcvwfwsVmTdNewRTgmhEbNKyl64XEIEbIVi7GXEmfCaNipQ
zEfTN/m1hMl1kn9gey+0yJT9K3oAkA4UqBUbGmgP/UuYcztZvnhjnt9Np60gwBhf
l7de3OBFcxQUatq2Tfn+HbqiGA5aur/IfJzcrzK9kFXLi6Ox2nMZGN1U2CTmJEcT
ZLFQH1tKQ0doacaAUtRSSx3IbTVSoOjr2imSzsfPKCM691OwwGC4XeJLVTn3QmVF
4WhDQsH+ufluG/dFHPA7Nqa1IVp9IX/QhOW1ZAgmODNVR37EkXGp
=cIwM
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8fUACgkQmmx57+YA
GNnjPw/+LYwi3YXP4izmG0u6y/Jfmy1J6T37FCZJEo8C9I92USUU+S6z9pEG5yrn
LhmXogJj3zB6dGUcq7nFUXIUA5YMVGxofnFRbyxbGPUmRnQSfpOB2/g4aSEYf2U8
0OwD/4ajxVOP2mSimQ7gXnwpzfeUvNrml81VJ76OHZnVtEqt81l/vIyWpd3Dro00
EQN+THTAV4G2M6XhshILt5QTLdsWHwPoCaZAg0PwmIJDU/3NeBH92rXIQiWkE33R
zmPJyOZ2ih3D2ceyVVdNp9uIvLcXeIpsXqIQv2dN0D5iXjviyBqfX787S4PFLlLO
ibsYyB+JUkciwzHyRrKHRYlOXuZmhYDYcL1M+6STSMtmZfS3Kno6V9kOdPYWpTZ8
SluJYqdkED0NMggegunGj67qbe902hX9vuL3vISaZUll3Au48YGSEoEcpghf8kuE
E2Uo4pnEkhN/1sSeZFyINUstKtqpa/XMAS2sK/CJQ09HjQfqvFnifjUxhjqYoAM6
ylhjDymjH11h3jWDmiJUpYfPxa4u/j598UI4ajvKgwPhd0ZxLug43d9IQBpFxux6
qXCWQrgUe39L5o8hfgQSXb58g72uGBXMRd8m7F3G52teGkFz+xentxHbJEZlX8oZ
UQJXCDHhkFpGkD3TNOc4YbQW/ydDZo+OCzWopP3iU6oG2X3FPQY=
=yqpJ
-----END PGP SIGNATURE-----
Merge tag 'v5.18-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
New boards: Pine64 PineNote ereader tablet and Bananapi-R2-Pro (both rk356x)
New peripherals for the rk356x-family (pdm-audio, gpu, another i2s, usb2)
A lot of additions to Quartz-A (connector-header, gpu, sdmmc1, io-domains,
usb2) and rk3568-evb1-v10 (rk809-audio, cpu-regulator, gpu, tsadc, led,
usb2, touchscreen).
Fixes for the pwm-regulators, that used wrong names for their supplies
as well adapting the cros-ec pwm nodes to a changed binding (going via
the pwm tree).
And as sort of misc-changes, defined the logic-regulator on rk3399-puma
as well as enabled the mali-gpu on the rk3399-firefly.
* tag 'v5.18-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (28 commits)
arm64: dts: rockchip: align Google CROS EC PWM node name with dtschema
arm64: dts: rockchip: enable rk809 audio codec on the rk3568 evb1-v10
arm64: dts: rockchip: set vdd_gpu regulator on rk3568-evb1-v10 to always on
arm64: dts: rockchip: add the vdd_cpu regulator to rk3568-evb1-v10
arm64: dts: rockchip: enable work led on rk3568-evb1-v10
arm64: dts: rockchip: fix supplies for pwm regulators
arm64: dts: rockchip: define vdd_log on rk3399-puma
arm64: dts: rockchip: Add Pine64 PineNote board
arm64: dts: rockchip: Add pdm node to rk356x
dt-bindings: arm: rockchip: Add Pine64 PineNote board
arm64: dts: rockchip: enable the tsadc on rk3568-evb1-v10
arm64: dts: rockchip: enable the gpu on rk3568-evb1-v10
arm64: dts: rockchip: enable the gpu on quartz64-a
arm64: dts: rockchip: add cooling map and trip points for gpu to rk356x
arm64: dts: rockchip: add gpu node to rk356x
arm64: dts: rockchip: add usb2 support to rk3568-evb1-v10
arm64: dts: rockchip: rename and sort the rk356x usb2 phy handles
arm64: dts: rockchip: add the i2s3_2ch node to rk356x
arm64: dts: rockchip: Add Bananapi R2 Pro
dt-bindings: rockchip: Add BananaPi R2 Pro Board
...
Link: https://lore.kernel.org/r/6456947.djgVdjDsCv@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
When sending a call-function IPI-many to vCPUs, yield to the
IPI target vCPU which is marked as preempted.
but when emulating HLT, an idling vCPU will be voluntarily
scheduled out and mark as preempted from the guest kernel
perspective. yielding to idle vCPU is pointless and increase
unnecessary vmexit, maybe miss the true preempted vCPU
so yield to IPI target vCPU only if vCPU is busy and preempted
Signed-off-by: Li RongQing <lirongqing@baidu.com>
Message-Id: <1644380201-29423-1-git-send-email-lirongqing@baidu.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
When Linux runs as an Isolated VM on Hyper-V, it supports AMD SEV-SNP
but it's partially enlightened, i.e. cc_platform_has(
CC_ATTR_GUEST_MEM_ENCRYPT) is true but sev_active() is false.
Commit 4d96f91091 per se is good, but with it now
kvm_setup_vsyscall_timeinfo() -> kvmclock_init_mem() calls
set_memory_decrypted(), and later gets stuck when trying to zere out
the pages pointed by 'hvclock_mem', if Linux runs as an Isolated VM on
Hyper-V. The cause is that here now the Linux VM should no longer access
the original guest physical addrss (GPA); instead the VM should do
memremap() and access the original GPA + ms_hyperv.shared_gpa_boundary:
see the example code in drivers/hv/connection.c: vmbus_connect() or
drivers/hv/ring_buffer.c: hv_ringbuffer_init(). If the VM tries to
access the original GPA, it keepts getting injected a fault by Hyper-V
and gets stuck there.
Here the issue happens only when the VM has >=65 vCPUs, because the
global static array hv_clock_boot[] can hold 64 "struct
pvclock_vsyscall_time_info" (the sizeof of the struct is 64 bytes), so
kvmclock_init_mem() only allocates memory in the case of vCPUs > 64.
Since the 'hvclock_mem' pages are only useful when the kvm clock is
supported by the underlying hypervisor, fix the issue by returning
early when Linux VM runs on Hyper-V, which doesn't support kvm clock.
Fixes: 4d96f91091 ("x86/sev: Replace occurrences of sev_active() with cc_platform_has()")
Tested-by: Andrea Parri (Microsoft) <parri.andrea@gmail.com>
Signed-off-by: Andrea Parri (Microsoft) <parri.andrea@gmail.com>
Signed-off-by: Dexuan Cui <decui@microsoft.com>
Message-Id: <20220225084600.17817-1-decui@microsoft.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Even if "no-kvmclock" is passed in cmdline parameter, the guest kernel
still allocates hvclock_mem which is scaled by the number of vCPUs,
let's check kvmclock enable in advance to avoid this memory waste.
Signed-off-by: Wanpeng Li <wanpengli@tencent.com>
Message-Id: <1645520523-30814-1-git-send-email-wanpengli@tencent.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
