MWAIT is advertised in host is not overcommitted scenario, however, PV
TLB/sched yield should be enabled in host overcommitted scenario. Let's
add the MWAIT checking when enabling PV TLB/sched yield.
Signed-off-by: Wanpeng Li <wanpengli@tencent.com>
Message-Id: <1645777780-2581-1-git-send-email-wanpengli@tencent.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Just a single update adding long waited support for SCMI firmware variant
as separate devicetrees. I wanted to deal with this differences in the
firmware interface within the bootloader for long time. But with variety
of bootloaders (u-boot, UEFI, ..etc) and need to add SCMI and SCPI
support for sake of discovery with discrepancies in shared memory layout,
it turned out difficult.
So, finally we are adding it as separate files so that we don't break
support for older SCPI firmware interface.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAmIVQ7YACgkQAEG6vDF+
4piUsg/7B/d8NBgfXQ4WSVCDw7D5ekkTVSA8I1jOu084UCUCoQjJ6h9I0sMc8ALo
ikYRgF34evJP78xl+AGsU7iQfeja4i4j+5frUt9pseiQ3XW7i+kFmp/bjX9XlYFQ
HsGJ+F7oUp70W5YxfF+Ay1I9avbA6hDWqSE6gsFNVPRnVpphBzF7MvBBsTdl9CE8
ip/gTg2WEnjzdvCHyCQ9wGV8HozTtcR2Fz1WB3LaIpqToIui7gQ2KEazqTH5cJcS
xovUdM5eMdvMHsblnLDn/ET6gvFlV1AeRxUQXQTDm8tqk/3cpRzZj0EcWJy2A6OE
0BQ63bw8bwqR+JW/vbhW01PdaA6uuKhKNINuP/RtCv++/UimDyI4QgRs8MzLFUYH
2JKptVQpaeracUElKNBkOGZGhzS9p8I9smzhFyZVHucBQA0vDzOX7e2BJpLyhTJV
tnRMc+mUH6KHr97eEJxFiEVC6aI3UiaVgTjaMnEB7ED8yWa6x0bLbgX9RRhXj9W9
hNOuCMBuDhQZD86wVwUXAi2yB0UHlCNbmhEoegxaL0h7o1G0GyNB5crLMZwck4sy
CCaLUZbUaJrsFaVpv5C6/M2xhwUtf/yKDlW65EduBc6KFKiZa4c1mrE+Ft2ZqD79
bVVLlzW/lz+2YdITrbyCCbzgNyQhwp4aNqHLwlwuDsSzhSD5uZ0=
=g/zs
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8SUACgkQmmx57+YA
GNmySg//WaF+/WTHSYleBvknbsmMQjvYz9LqpQmAXlJkxqnrbORgiBVByQ9SNgKg
Pkz6j6Ex4se8KfzZUwMmdGhuN+pOWQKi3hd2YZtt4W5koTuVw9pDberafiskC7fV
IGqdYvJtDBWZdlFfE9RZAYEvFt2cAHQJEBQQiNX3cgRl+RgqZpHC8Umm/1mLAo2a
MgLRVVRkONxQN6DPtb6KOrLqWGmVo9+wDhDXHLqBQIMyHHj/fMuNOc/c98ePPUPI
Z/0Rk/z8+Bt+6lc0FtLSjljSuSphkm//5IVle8v1KKAH3Iq0cmnjFAaXRH168naa
oR4vyRFG7i+2syFHrSt5wRmsqQab99lyqwGUgNsD7+Fl+uxt53T0z2ijIDzP3aZE
SyaQxwLUMyinPhppGNG7KoK7VEMqBpYJnhrtbDO8knrQK8SjFQY0t378lUvOFGPE
orAGkNX5P8FH22zq/qsJT/ls8qQ6nC/fe/5g8tNcLqbO88hSmLd2yacRp9U1UOST
ekVZZjQeDoWukPN11fSwSvKzrzx76xohtrN4NPzH+civuwr+J36PNz6R0nI7FDp4
ngs06jZztgNs4fItCmUhVgz2cgk96VDr8AZ2Fzt9+A4sPUcZWqy1yr5aip4/vVTE
LwTvzPIiL4zWBosx0J2XaYMIPwUGtY35bYmHxavYeNPLMEgSS00=
=D501
-----END PGP SIGNATURE-----
Merge tag 'juno-update-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt
Arm Juno update for v5.18
Just a single update adding long waited support for SCMI firmware variant
as separate devicetrees. I wanted to deal with this differences in the
firmware interface within the bootloader for long time. But with variety
of bootloaders (u-boot, UEFI, ..etc) and need to add SCMI and SCPI
support for sake of discovery with discrepancies in shared memory layout,
it turned out difficult.
So, finally we are adding it as separate files so that we don't break
support for older SCPI firmware interface.
* tag 'juno-update-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: Add separate SCMI variants
arm64: dts: juno: Remove GICv2m dma-range
Link: https://lore.kernel.org/r/20220222201812.3338619-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- New support for a number of i.MX8M Mini based boards: Protonic PRT8MM,
emCON-MX8M Mini, Toradex Verdin, Gateworks GW7903.
- A series from Adam Ford to enable GPC, USB and display support for
i.MX8M Nano.
- Enable G1 and G2 video decoder devices for i.MX8MM and i.MX8MQ.
- Enable PCIe support on imx8mm-beacon, tqma8mqml, imx8mm-evk,
imx8mq-evk and imx8mm-venice board.
- A series from Hugo Villeneuve to add PCA6416 interrupt controller
configuration, GPIO line names and i2C5 support for imx8mp-evk board.
- Correct I2C3 pad-ctrl and add internal display support for mnt-reform2
board.
- Improve fsl-ls1028a-qds overlay support by dropping syntax hard coding
and using overlay target for build.
- Add overlay support for serial modes and imx219 rpi v2 camera on
Gateworks imx8mm-venice devices.
- A set of patches from Teresa Remmet to update phyCORE-i.MX8MP SoM
device tree, including drive strength updates of different interfaces
and PMIC configuration changes.
- Device additions on various boards and some small random changes.
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmIUi64UHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM7s3Qf/TtDGP7UBFb0nnqNgNzkiQfnxsRog
iGcwwalE/Qn4Tq5ED/Sf34FOJut70fJ8chvbhqvCGkEOQPdgYOrFC8PmZw1VbKeX
5xNDihh3DAIEcGmJ89dDD5bkCepKOkyahm5c25RLzkUCOcKndoeWkzvU5bbMTs2w
8AJCrDmJ1+k5zyUXcKZlq3ySNhS4KQFD25dYGMvLy70oYhxCRtY/HLECLEStXVXs
UJ5tdwPeb4jSLi5EM9oupy4V3IGfgBSSdFCLdpXtlOTmGg5Y5rHeO1E8mFRXvigO
tCYo70SdzjLZPPxl9SUX6Ql7ShMYNZLtzmIVRn7Be2jRQ4xld9bXE4jFJw==
=iEe4
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8JAACgkQmmx57+YA
GNkUDRAAlwe2qrtugN8jUbnUIN41La5QiXOCAJYOQCosyCgAVb70ZGTIBJvOucyj
bpwU3n4hN/nppMF47jct+RRE5UcPWNF4oB7LxgEe2SdqrkUmF9/moK5XjfipCTgr
gvGln28un3mR7KS9cah3YFM/tTf749CeL5GiGx0veew39LxlYZMGA7wXIl1hJ1Tt
Vl9jzfxsrVh+lzexQBJfAbWQAE4wM5WPwDl3H/o6xZGRZPCJkuNzdmZBvnZaC5WM
ZT/R7CoeimHOV2936993MXjWkZqqZMaUBvrMGcoLYReq+0Qnht2hcETW/rHUa1+M
5nsPWSBfN8uN7jGP+qpz71eJbc8BQ/XKyximoJph9m3M1VbTNKjY1Lhq6dX2Fmyt
cutVy70TGvOEjXJOctnWf973ABBhr+NnF5m0NAJ9XGsKEGI3j3tjgYO8rpcCVnm4
AdAqSv6/HF6PQkLuT/oJu8SfHzykvZDwkh+lAP2Hfnd+Y8DEkez+c96VkvW0lqzf
TxrZIWQqrYGFPahB8rWjGzRPoLjJW6pfBEg/1iRmStMb2O+VQKzndf0DcYarrPjY
1ecrpGssvI701PP3ofwFoiOS4tGU/G955Lq8uKoT2DUVAXMOaaiGKUdxJyaMcfEr
F4BK4eLvyn/t6XDzM+7Tfj1e054bbi9GO9JZFNbGwFLCOkzHurA=
=atxP
-----END PGP SIGNATURE-----
Merge tag 'imx-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX arm64 device tree change for 5.18:
- New support for a number of i.MX8M Mini based boards: Protonic PRT8MM,
emCON-MX8M Mini, Toradex Verdin, Gateworks GW7903.
- A series from Adam Ford to enable GPC, USB and display support for
i.MX8M Nano.
- Enable G1 and G2 video decoder devices for i.MX8MM and i.MX8MQ.
- Enable PCIe support on imx8mm-beacon, tqma8mqml, imx8mm-evk,
imx8mq-evk and imx8mm-venice board.
- A series from Hugo Villeneuve to add PCA6416 interrupt controller
configuration, GPIO line names and i2C5 support for imx8mp-evk board.
- Correct I2C3 pad-ctrl and add internal display support for mnt-reform2
board.
- Improve fsl-ls1028a-qds overlay support by dropping syntax hard coding
and using overlay target for build.
- Add overlay support for serial modes and imx219 rpi v2 camera on
Gateworks imx8mm-venice devices.
- A set of patches from Teresa Remmet to update phyCORE-i.MX8MP SoM
device tree, including drive strength updates of different interfaces
and PMIC configuration changes.
- Device additions on various boards and some small random changes.
* tag 'imx-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (50 commits)
arm64: dts: imx8mp-phycore-som: Set usdhc root clock for eMMC
arm64: dts: imx8mp-phycore-som: LDO5 needs to be enabled instead of LDO4
arm64: dts: imx8mp-phycore-som: Set VDD_ARM run and standby voltage
arm64: dts: imx8mp-phycore-som: Update WDOG muxing
arm64: dts: imx8mp-phycore-som: Reduce drive strength for fec tx lines
arm64: dts: imx8mp-phycore-som: Adapt eMMC drive strength
arm64: dts: imx8mp-phycore-som: Set minimum output impedance for eth phy
arm64: dts: imx8mm-venice-gw72xx-0x: add dt overlay for imx219 rpi v2 camera
arm64: dts: imx8mm-venice-gw73xx-0x: add dt overlay for imx219 rpi v2 camera
arm64: dts: imx8mm-venice-gw72xx-0x: add dt overlays for serial modes
arm64: dts: imx8mm-venice-gw73xx-0x: add dt overlays for serial modes
arm64: dts: imx: Add i.mx8mm Gateworks gw7903 dts support
arm64: dts: ls1028a: add efuse node
arm64: dts: imx8mp-evk: add support for I2C5
arm64: dts: imx8mp-evk: add PCA6416 gpio line names
arm64: dts: imx8qm: added more serial alias to dts
arm64: dts: imx8qm: add compatible string for usdhc3
arm64: dts: imx8mq-evk: Add second PCIe port support
arm64: dts: imx8mm-beacon: Enable PCIe
arm64: dts: freescale: add initial support for verdin imx8m mini
...
Link: https://lore.kernel.org/r/20220222075226.160187-5-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- A series from Alexander Stein to update imx6qdl based TQMA6 and MBA6
devices, adding I2C bus recovery, marking GPIO buttons as wakeup
source etc.
- A set of maintenance patches from Oleksij Rempel adding display,
CAN termination and thermal support for i.MX6 based boards from
Plymovent, Protonic and from Kverneland.
- A couple of patches from Thierry Reding to correct i.MX28 RTC
compatbile, and rename RTC device nodes for i.MX SoCs.
- Update i.MX7 device tree to use audio_mclk_post_div clock instead of
audio_mclk_root_clk, and move PCIe out of AIPS3 bus.
- A couple of patches on imx6qdl-phytec to support PMIC MFD subdevices.
- Add pinctrl header support for i.MXRT1050 SoC.
- Other small and random changes.
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmIUixcUHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM7vDQf+N7EzT+AknNIBAKtW0O/Cjxlj78CA
Urbfzo75ePeS5MCnfuI1RnIgZiWtvt2fSppjvls1f67vYw4RSZqsG/T3VVF+lefw
Lnm/Z/Ak4qNwEyuX/pcAWxCpIHB1jSpSDxnr0mD0asfKF/QicEmOXH5s6lS75G45
ycItrZ8YXp1kiTqb346bqyUe5MQ7i9UWhj/WCH+0JLeW0NKdkbBPeU91eQKBhuMI
qEiTxtPLL1vH4s7qy+lT3G+j6GapLqZfDWsPqLo+lIwy6jRmfruau1sIy4vu3Euo
0ntmBbRm4palWfzVqVlAX9JEop+gi5PE+YLUPlt0mjevWXpOCvrJoCHOWQ==
=8N3I
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY8FIACgkQmmx57+YA
GNl/fw/+L7PcpisPsiso7mSNuIgxUHBA8FAXw61dhYuODM1L+/3V5ULwrDOhlK6u
KN8ISVBoosuPClL/AJgAF5XX8RjaiNignzhf4V2WKnImaBoBC2lWw1jvMsTpng2l
Z6LFBWnalV1BJU363MBvQw5nNGNZY4hMlXI2IqXwBaUn14vI8xKPA3vKo5k4gS1J
MD94T7iKyoYTwvfoBs18iD9xjpQtBUFY13BTZdVm329JMvDAc1l5gYzW4fcw7TaP
kPQindcYvBXTaPR1TakpP69wYwQgV5hAN/qKY+J4LPkGsv+GjzOiu5dlOV99jP31
CPci9tScTB5H1DFs0ZPuLyln70TICKGyRPqpjBeXWQxcrmQJoqZSnZ2eSha2mhOc
xVlbL6Yngy9qeUjfMcWNUHiJ9iuLo7ni1Qa1CjLr/OYeCrpXTqmpwKbgoXVvuF28
RsgzjCsdBEP+JB55nFtwF5KuLUXDA3u/fogT1V/aCA4iK/nbbrWgMxI8/ZcE5olh
vln2YqMWvAsEqH5kHouCdJK9FUpCW+cb2DRO8MPOvO2xw+ufqUnT4xT+Q8D5vIJL
5nUemE19t9Ww2o5iZd4AWZMXNVkXX3/6tu9WrEq3UUq0GWFYztzJbmfGzFl88N7N
sFM0/Bti7GFiICcGkkRf7sDZ8TrH7wAXObvcyia/N8u8MfABtps=
=dW+C
-----END PGP SIGNATURE-----
Merge tag 'imx-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX arm device tree change for 5.18:
- A series from Alexander Stein to update imx6qdl based TQMA6 and MBA6
devices, adding I2C bus recovery, marking GPIO buttons as wakeup
source etc.
- A set of maintenance patches from Oleksij Rempel adding display,
CAN termination and thermal support for i.MX6 based boards from
Plymovent, Protonic and from Kverneland.
- A couple of patches from Thierry Reding to correct i.MX28 RTC
compatbile, and rename RTC device nodes for i.MX SoCs.
- Update i.MX7 device tree to use audio_mclk_post_div clock instead of
audio_mclk_root_clk, and move PCIe out of AIPS3 bus.
- A couple of patches on imx6qdl-phytec to support PMIC MFD subdevices.
- Add pinctrl header support for i.MXRT1050 SoC.
- Other small and random changes.
* tag 'imx-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (22 commits)
ARM: dts: imx6qp-sabresd: Enable PCIe support
ARM: dts: imx6dl: plym2m, prtvt7, victgo: add thermal zones and hwmon
ARM: dts: imx6dl: plym2m, prtvt7, victgo: make use of new resistive-adc-touch driver
ARM: dts: imx6qdl-vicut1: add CAN termination support
ARM: dts: imx6dl-prtvt7: Add missing tvp5150 video decoder node
ARM: dts: imx6dl-prtvt7: Add display and panel nodes
ARM: dts: imx6qdl-mba6: Move pinmux to regulator node
ARM: dts: imx6qdl: tqma6: Remove obsolete comment
ARM: dts: imx6qdl: tqma6: Mark gpio-buttons as wakeup-source
ARM: dts: imx6qdl: tqma6: Add i2c bus recovery
ARM: dts: imx6qdl-mba6: Move rtc alias to common location
ARM: dts: imx7: Move PCIe out of AIPS3
ARM: dts: imx: Add missing LVDS decoder on M53Menlo
ARM: dts: imx6qdl-phytec: handle unneeded MFD-subdevices correctly
ARM: dts: imx6qdl-phytec: add missing pmic MFD subdevices
ARM: dts: imx7: Use audio_mclk_post_div instead audio_mclk_root_clk
ARM: dts: imx28: reparent gpmi clock to ref_gpmi
ARM: dts: imxrt1050-pinfunc: Add pinctrl binding header
ARM: dts: imx6sx-udoo-neo: Add HDMI support
ARM: dts: imx6qdl-dhcom-pdk2: Include missing headers
...
Link: https://lore.kernel.org/r/20220222075226.160187-4-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Additions to wpcm450 following the upstremaing of the pinctrl/gpio
driver for this platform
* Match more of the platform in MAINTAINERS
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE+nHMAt9PCBDH63wBa3ZZB4FHcJ4FAmITUqAACgkQa3ZZB4FH
cJ4LxhAAuvm8O2YQbLDMt09L5JKu0P++Oz6MMbP0IHDrasRaZFuOPp/nAwQXb+wJ
xdiXr/xfOV2PCIt4RPZ3NRagiFYNwpyq48oraKJnr8IuRyxTLo/bfa6sNKFGUU/r
fiLzLbDvUzgZD0HvS+wBoXoQAGcrx8boKhMRbqBsua7S9WXzOAd91D5hH/7dVtX9
4cUODi8ZE7rkg3psB6mmgm3/4tlVps2n2DSKG1GSqCI1+DBz25W3rYuvkVljAS0l
pIymZyw50f6BsCnCBJ0aRSB52+qCDcIikKlGQBbzHCe/6ozdyRvrHUBqtreSV2ug
iDGKQicJkhraab+HaooIDcCGPsjaC6BcPKV0VGPApxt8Z4lkiE36/KNdGImnHz6k
q8ScdKejRj5e8Gf9bsJD6Upmhq7lDFvJzdRYZLIxSlhnQ4dx4Y4djs8Tvbhy44qo
vcSijRSS6rEEBCoGX3xb/sxzZhxfsWLM2f2QWrq1K+dEl9N0+71B9UgM3o89k+Nv
Bww5v0N2sUR80uZ7Wr81/f0ByggOEuawjtJoeN+fKGGMFBTbJa9X6pw5DUHppalg
SaqwEZ/E2qkjbCQQXUVPG3fa0j9Igp+L8q15cjoc2BbhKkzjhAmpsvKcQjgsus5N
7+5Nr614rTWBjmwt7Px5FE0BvUhk9XL8vLgatETkbQOogwgyvVk=
=bfnw
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY7r4ACgkQmmx57+YA
GNkK8RAAqFn4WYyDutldEYmdpW8MUFoxeFdFh5FG2MSiz5hHsouECOHcW707He05
JZ9ziBPLffUAKOtG4tf0Zv3Sf0IuWOdJiIOqbdnQCCcA0JhMELYalfyRmxgMSc5t
2CtgMlaJCCBHVR4I1ljxt9tKuxQfjSs+/o2iBcov7FiHwWak9waI5wuaVfgfrJJ/
5ySochmdl1Y3g4QlPqSSVF2FTTvDv3GWRH2J5FkfpF43kz+M+QEvjedwMjEFuRsr
du81rz6qYiCx+rAXBRpM1ucFzqT+DRycd1GN/ukpYC9830ce9HRpC0+YZgryNJ0G
P2jEtW6Vkt6nhrg7TSl7FTmtES187ZoaG3QTQJ49e1SieoAroqXgUZW2PysrPs/Z
vR4BC3rGf5Wnye0o8d429RVekj16Adxl1Rax27qPs1tuD++4xkzuOT9ob7r53GuG
jesmFes8nqGBv1d4nfSj5h3jF0HYonsV1+VFpTQXrXzGSAzD2DNGqb5Rzqvnasq4
CpJjbhgMXxjTDF5HC3DHqJmFjfg6kuTGQIxtO0LLnfgiQdIQH0WFMbvpke2FcuG+
gHy+PFz8saSer+BQyN2FsZVWpf3/9mwnDMdIoH0hXJZDv9bBS+Ya8fwGUdAWmN4v
gZ6E0uQe/tOCxL9TJrl8es7eBppPLQgjp6vqfrKEr1R07v1zX6w=
=/MfM
-----END PGP SIGNATURE-----
Merge tag 'nuvoton-5.18-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/dt
Nuvoton device tree updates for 5.18
* Additions to wpcm450 following the upstremaing of the pinctrl/gpio
driver for this platform
* Match more of the platform in MAINTAINERS
* tag 'nuvoton-5.18-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc:
MAINTAINERS: ARM/WPCM450: Add 'W:' line with wiki
ARM: dts: wpcm450: Add pinmux information to UART0
ARM: dts: wpcm450-supermicro-x9sci-ln4f: Add GPIO LEDs and buttons
ARM: dts: wpcm450: Add pin functions
ARM: dts: wpcm450: Add pinctrl and GPIO nodes
ARM: dts: wpcm450: Add global control registers (GCR) node
MAINTAINERS: Match all of bindings/arm/npcm/ as part of NPCM architecture
dt-bindings: arm/npcm: Add binding for global control registers (GCR)
Link: https://lore.kernel.org/r/CACPK8XdjF6dG04hR+iMpUP8=LSJi5x-hRivgCGDaY7o_461eJw@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* 'mstar-dt-next' of https://github.com/linux-chenxing/linux:
ARM: mstar: Extend opp_table for infinity2m
ARM: mstar: Add OPP table for infinity3
ARM: mstar: Add OPP table for infinity
ARM: mstar: Link cpupll to second core
ARM: mstar: Link cpupll to cpu
ARM: mstar: Add cpupll to base dtsi
dt-bindings: clk: mstar msc313 cpupll binding description
ARM: dts: mstar: Add board for 100ask DongShanPiOne
dt-bindings: arm: mstar: Add compatible for 100ask DongShanPiOne
dt-bindings: vendor-prefixes: Add prefix for 100ask
ARM: dts: mstar: Add a dts for Miyoo Mini
dt-bindings: arm: mstar: Add compatible for Miyoo Mini
dt-bindings: vendor-prefixes: Add prefix for Miyoo
ARM: dts: mstar: Add the Wireless Tag IDO-SBC2D06-V1B-22W
dt-bindings: add vendor prefix for Wireless Tag
ARM: dts: mstar: Set gpio compatible for ssd20xd
Link: https://lore.kernel.org/r/20220216193131.59794-1-romain.perier@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Correctly synchronise PMR and co on PSCI CPU_SUSPEND
- Skip tests that depend on GICv3 when the HW isn't available
-----BEGIN PGP SIGNATURE-----
iQJDBAABCgAtFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAmIY1HMPHG1hekBrZXJu
ZWwub3JnAAoJECPQ0LrRPXpD4LEP/R2R5nvZwaiJIcVopzJd4ayN16bBL6qCxXWm
XsuMqdE8g/Rju3sxR/qtomDgB3GJoYpCyY28rrmVli0WBZRt9icFE1cnqUMbv5g0
Iyd+RS79LcKU6OMakAyjYX0NNwhGHr1mdD+gP8NSMny+2XWQSVcUtTVZOjSprI9L
zFNtJxPs1wfCp3WOWF668dgrBi8TsPHte2y0110+BcrY1rzJF0HXZm8YimlLakOG
Pk98dbpGMV1aKog5p9YgE3tP0oMjUcf7h+EZxuQmKF7WeFCfVg1M1xlovxRq/oEg
6KDUwUnNcDOtjUQ0pmCIPwm+rHJjlkEd+1MjZPf9L6fU0lPXmFN/DEawTh3iAsB+
xAaijEb5ImtgQgyhnDYwr5g307iXmrgSwGZKue0WOA2CTtryIXqdE02TqwZZHprm
MmAaUBUKbLGVMxd0sImsnrHUM1nNOHnD0IDEUwRLbAHOjm0u8rRK6ewV/A2O66Zz
A+AVpBZ3wd4jKkrN509d4TqomegXZQDL7hDHSgWPJDWQvOe0dFdWPJtjtamOg9Bq
+DVdXfwhQR7pHQIQbufIL+80Pgv7oBdEVSbtOJL+O+xkiSiDwHwkPdJwkB/01QMm
/f6oytJ/Kkhs+G+W6rn/bo/W1thgCBSnXntUz4qs+Cfpl4QDOIFvqMmwDdOHOzcN
9WrR6DZg
=Nyln
-----END PGP SIGNATURE-----
Merge tag 'kvmarm-fixes-5.17-4' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD
KVM/arm64 fixes for 5.17, take #4
- Correctly synchronise PMR and co on PSCI CPU_SUSPEND
- Skip tests that depend on GICv3 when the HW isn't available
The architecture provides an asymmetric mode for MTE where tag mismatches
are checked asynchronously for stores but synchronously for loads. Allow
userspace processes to select this and make it available as a default mode
via the existing per-CPU sysfs interface.
Since there PR_MTE_TCF_ values are a bitmask (allowing the kernel to choose
between the multiple modes) and there are no free bits adjacent to the
existing PR_MTE_TCF_ bits the set of bits used to specify the mode becomes
disjoint. Programs using the new interface should be aware of this and
programs that do not use it will not see any change in behaviour.
When userspace requests two possible modes but the system default for the
CPU is the third mode (eg, default is synchronous but userspace requests
either asynchronous or asymmetric) the preference order is:
ASYMM > ASYNC > SYNC
This situation is not currently possible since there are only two modes and
it is mandatory to have a system default so there could be no ambiguity and
there is no ABI change. The chosen order is basically arbitrary as we do not
have a clear metric for what is better here.
If userspace requests specifically asymmetric mode via the prctl() and the
system does not support it then we will return an error, this mirrors
how we handle the case where userspace enables MTE on a system that does
not support MTE at all and the behaviour that will be seen if running on
an older kernel that does not support userspace use of asymmetric mode.
Attempts to set asymmetric mode as the default mode will result in an error
if the system does not support it.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Vincenzo Frascino <Vincenzo.Frascino@arm.com>
Tested-by: Branislav Rankov <branislav.rankov@arm.com>
Link: https://lore.kernel.org/r/20220216173224.2342152-5-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Allow userspace to detect support for asymmetric mode by providing a hwcap
for it, using the official feature name FEAT_MTE3.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Vincenzo Frascino <Vincenzo.Frascino@arm.com>
Tested-by: Branislav Rankov <branislav.rankov@arm.com>
Link: https://lore.kernel.org/r/20220216173224.2342152-4-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
The code isn't that obscure but it probably won't hurt to have a little
bit more documentation for anyone trying to find out where everything
actually takes effect.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Vincenzo Frascino <Vincenzo.Frascino@arm.com>
Tested-by: Branislav Rankov <branislav.rankov@arm.com>
Link: https://lore.kernel.org/r/20220216173224.2342152-3-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
MTE3 adds a new mode which is synchronous for reads but asynchronous for
writes. Document the userspace ABI for this feature, we call the new
mode ASYMM and add a new prctl flag and mte_tcf_preferred value for it.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220216173224.2342152-2-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Some features may invalidate some tests, for example by supporting an
operation which would trap otherwise. Allow tests to list features that
they are incompatible with so we can cover the case where a signal will
be generated without disruption on systems where that won't happen.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Shuah Khan <skhan@linuxfoundation.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220207152109.197566-6-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
- Fix up the WG302 to support the v1 version (also tested)
- Fix up the syscon size
- Drop the alias for UART1 in GW7001
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmIIHtgACgkQQRCzN7AZ
XXMZoRAAtILhm1zZP0IAYpeXNEg6Mj51YVKuQamyo6zZG7MrEqy/9wjSnHGY5+P0
DBBkYBPjJmMoF3Jn3IK68tNVoJadE8dg2eklKharU1nYcOLAbNkrxZSmFv79dasO
rEDwR3FihNW1uu/USGfHL5ckWVpU3ld6iGtejyehXkMJI6AwHRDA+UGLP6fbi0nI
+/lgGqVRtHmlYiR5HKE3plQYSDVKFuTs8VxRZS3NS1cHR3ERuA3gXPA7t4ls0e2j
PBKkgJJov7SqnHqWGdhZwoIyZpxyn/t6Rt/nM+Mvk2jTImMvkGREOp8X/vkrXAGo
B7f9mgw//36H0PN+2Hdbw56JYq7VU7lgAUp1wk+DQgwp5+xrTP4jwTVHL3nwjHlJ
TVs3CVOTHjQedeQoSPNT5OiwLUiG88x6uXepZVOEGRfObM0AXvwayreAO6iAKShR
IS+xhioJx5JRDxA3Wqfsy8OE+WiDWzgFI7zvdSluxEiiIlK67QS+oGpU77C8SkeU
XtY5fjSYd5x7RVTUtsMpfWHqRDUeF4q9NuIXFfTZJunJhxLYJF57NswkoG3j0ijJ
zM+yhoqY55Wc5yj2Tor+nMGSAC9h1CxgAswFXN50cktReZ2fULC88L3zFGPZs+8u
KAWVswMwdLS6fTYHYHv+JHAR7PONQkZjjlvpEm524IgwMVXlDrE=
=ydjH
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY6RsACgkQmmx57+YA
GNm1FBAAi6TykQDRm1L++QYIFsXmkKHBgZ39g6OBG4I6mi/2bXq8CpjR75WDj4vU
sx1J/x6iDce5ReSDiQuCoyXq6hqKPKV168gVgb6pHVDcH5gJyUshGOsJx1dHnMF3
f3a/tV8YkzWbyq8cN2EaTCzGMPfaDrpiJamV2czezoKAMivOoQ4hFg/Gzx3eNt7B
kdQMTwNUfNusXcwFXsDDhOcDagWq82iZjKLIFbIe7xkuBhLkKQ5o+qF+2Zymjhni
0twjazrZmgSYLFvMiz+MmKARXGAtLc4DF+WJ2UV8yXlHdSrQF6MgxxiIJEJCeySM
ZdReMW7cqaAtIgTsDOIcURPB4rMZOlvJ7ar50L+KN4nPH6xIeGRiyqzLOqdYBrj+
FskPO+YfPTYygZzFvjYV1TBbKCdqUtvNN4MymC8vsW5TkixXVnKxkn834UQSgRVN
u9YN/fREh4m8B+QM2DnQWPAIHQvfYn/XuPDLaZx9brnFoh4Kg2tUNNl8SqNiAcLv
pFjgaAO3xnorMsEpbZMjJM3lIL0lSWkRgMfcJEBP6aeNpTKK0qfqwYH5Vw55Gkl/
hCsPx74QCdUxGVn2587OOG5OUJ/jdcmRmWFjRjP+fQ1qH2EbcS7NOogjB2X+X8yf
nIaPlPjgwr/sAqwISc7wa8ztaDGl8OWI+smTO8SX5dHjYVBCh6Y=
=Vc2E
-----END PGP SIGNATURE-----
Merge tag 'ixp4xx-dts-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/dt
IXP4xx patches for the v5.18 kernel cycle:
- Fix up the WG302 to support the v1 version (also tested)
- Fix up the syscon size
- Drop the alias for UART1 in GW7001
* tag 'ixp4xx-dts-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: dts: Drop serial 1 alias on GW7001
ARM: dts: ixp42x: Expand syscon register range
ARM: dts: ixp4xx: Fix up the Netgear WG302 device tree
Link: https://lore.kernel.org/r/CACRpkdaMk+XECwhXJYeiF8SMU6cQsj_dk8gGMoPE3zAURAPqTw@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add battery thermal zones so we can monitor the battery temperature
- Enable charging options on AB8505
- Fix up all the AB8500 and AB8505 nodes in accordance with the new
schema.
- Fix the mounting matrix for the Janice phone.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmIG2fwACgkQQRCzN7AZ
XXOBsg//YA3N12II2lxCRHriTdz6L5jAUdArHMMgLNTLbNJAHLIgcGDDH2WwUTDH
/Q+TNUEeQVSXbm5bflp4+SxX5OCkAWDNZVt1/MegoIotfDv7fjN0JwwPNJeQX61Y
c/DH9sgVEXv/iS1kt8GGzlpnyg60G7w8mCQeEOQ0YIjJwkxk38zqMK9qzTrTgcFB
XS9OPjCbBp4HEGOltVnQjbtiCEVU1N4yrwLYmkP+MF1Bs+/WDcfukj9gZGgJ9zGu
ljivN6smB0BJ7b5D9Wf6CvYOPVYfe2gxhwOCb4Y8xIiPUXN6KrbdetsbwMdqz0AV
Qwy8TiV6XFDL383mVcISLaRN64kEyfpMWeJPSTLNeNRJiKTrn/FiLb5k1+98lSZi
HWjp5tnmLsQ7o56VPbx6vdxlimnJ/abyWwek3tlQDPUkHmj+4IxPBCSpLhAoQ59I
z86af1wQ2Ggkn9CeXusoX8RDZZhK1C20nqi/4fWPv6G+r2z7YaVse2FcJhAlc8pE
Vos/6pSKy8n+gqtBr6uCLbh8xXQo/0/HBddRpYZBTTWPyc+hejBdviXv+HBeJ0An
ShuyX50yCbpCZknyBzQeNdDW7H9RSDTPQ8SSVUeM+YJxy67tmNVyK7D09EpHf5nd
5SaLQEkWK4joSawOLsb8VjGRTaHazbm0SsBAYZPZFCVhk5JmOLM=
=h414
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY6K4ACgkQmmx57+YA
GNl9ug/+Jm5Ms73+GTKcS6/oF2z7ASbF8mGk5H11qk1RTAZUrJfSgdnsCWmDNmuV
fG8vHqtPVTtlYuaBMTc85bkdSdQFLuQJ9naK+SA1R7eHDjeMVgnkVyiHDOmGNrb6
ubELnMiXfTAQhqy0VpYaKlHYcMtgAmMsNWhXToHVyYuAppYGZuqcsvsy86TDVKYs
yLLFHAVU/U+3725y/yqExfb3inhlrXQ4dl9qz5umKhsnONiW4f1gzOSPNATAtElV
MN2cQb+RYPlb2Baxt/9U/nZLyK5qYZMsY3mMJmgsblC9NQ3bPsCzfEejI286oKOG
tyJ+z5LQ8q5aCCWZRw3Joz03dzSLmW7WjFDukawoKKzK2+n4iMmzr1VFoaZ6QmKo
IJkneaY6mK8gC44RKwr1ADQZT92X8V28VGMXrHYMV23+lYt2eM0fkGfruO2lf5Ox
62q7SZGa/bmQFVA2it2gDt2WQZzDpyok9aSVUSudzaiAb5j6wYBM5OjcVb8oHe8o
68vsHgtN5bv6Tehyy6WFo65Jf7sOuz9xyTESWuxLcT8jMnsL1FL+x4jhV7TxvZRH
qC+lt3Vo1Y4YOIaM+of8dIpxp39grpnqslJ7auCSlhlM+knllslp/1NbZh+XpHjN
x9SxkWiTCSrrgDETAPOg1E0bNl3ZOVgG2OXROySwcwpiSMmJFD4=
=PAPT
-----END PGP SIGNATURE-----
Merge tag 'ux500-dts-v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/dt
Ux500 DTS updates for the v5.18 kernel cycle:
- Add battery thermal zones so we can monitor the battery temperature
- Enable charging options on AB8505
- Fix up all the AB8500 and AB8505 nodes in accordance with the new
schema.
- Fix the mounting matrix for the Janice phone.
* tag 'ux500-dts-v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: dts: ux500: Correct Janice accel mount matrix
ARM: dts: ux500: Update AB850[05] nodes
ARM: dts: AB8505: Enable charging options
ARM: dts: ux500: Add battery thermal zones and NTCs
Link: https://lore.kernel.org/r/CACRpkdaDcEqtSnWzRBnBHVweh2n=Dj3meHG9LND+K0Czb9ORGg@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Since all the fields in the main ID registers are 4 bits wide we have up
until now not bothered specifying the width in the code. Since we now
wish to use this mechanism to enumerate features from the floating point
feature registers which do not follow this pattern add a width to the
table. This means updating all the existing table entries but makes it
less likely that we run into issues in future due to implicitly assuming
a 4 bit width.
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220207152109.197566-4-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
CPACR_EL1 has several bitfields for controlling traps for floating point
features to EL1, each of which has a separate bits for EL0 and EL1. Marc
Zyngier noted that we are not consistent in our use of defines to
manipulate these, sometimes using a define covering the whole field and
sometimes using defines for the individual bits. Make this consistent by
expanding the whole field defines where they are used (currently only in
the KVM code) and deleting them so that no further uses can be
introduced.
Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220207152109.197566-3-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
The base floating point, SVE and SME all have enable controls for EL0 and
EL1 in CPACR_EL1 which have a similar layout and function. Currently the
basic floating point enable FPEN is defined differently to the SVE control,
specified as a single define in kvm_arm.h rather than in sysreg.h. Move the
define to sysreg.h and provide separate EL0 and EL1 control bits so code
managing the different floating point enables can look consistent.
Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220207152109.197566-2-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
- External interrupt (INTC-EX) support for the R-Car V3U SoC,
- Initial support for the RZ/G2LC and RZ/V2L SoCs, and the RZ/G2LC and
RZ/V2L SMARC EVK development boards,
- Support for MAX9286 GMSL deserializers and GSML cameras on the Eagle
and Condor development boards,
- NAND support for the RZ/N1D SoC,
- DMA engine (SYS-DMAC) support for the R-Car S4-8 SoC,
- LVDS support for the R-Car M3-W+ SoC,
- HDMI output and 9-axis sensor support for the Kingfisher (ULCB
extension) board,
- MAX96712 GMSL serializer support for the Falcon development board,
- MOST network support for the R-Car H3, M3-W, M3-W+, M3-N, E3, and D3
SoCs,
- Miscellaneous fixes and improvements.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYgZjowAKCRCKwlD9ZEnx
cIq5AP4gwBDY8UmVVcKj9CWl+feTrHYxjFCrs/ALVcjS1EphmQEAwpK4TaqElJwb
pO2PuhfgYlCl0QwkkzYygxKFAlutjQg=
=24DK
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY5lAACgkQmmx57+YA
GNnYOg/7BXiOalLktvKGNDMKREiJ9zJXMc55NNeQzw3ne2AN6M4nuOcBiGkQiHHP
NkvQwGruOXctTJtCnk4fCTd4cu1EhSIWBUyyk4t9sBLTLm+rG9a+tGyeFKj+opjF
MvdK+EqCAeZfF/zrwvIFBSz0rbhNKje6OT8iDU1Xha2YmabXJy5T0QXerDguF1P0
jJxrENPlhEVGFyh+9ObqgGCsMdRAnNeHyIgrg+nqdys7k4+PKtwopdyC6sb8cH6t
ok2zPAJuStGsW8USA5afhLU4qrL9kCEMH0tDWq2RdN27EYVJGAnp0O2Yxa20cxLh
pMNZ70KfvkbQkv2nf+ZyMEB5z27JR6hk9GJcKit3y4VCa6gIQfBxlVFBHqJD1q4f
ugQDV/pRH/KSktd/9XHcPf6yD8njpfqpZtBLFY5AlG6xns6oImHmwM+3Dp4Glsh5
5oAh8fp6BOKiqZt7lc24h1HJZB6G8FyWhhuRaTNYfLdX66GTrAkq5BvclKvLzbsj
SbW7o8zKNLeYPbNyC4jYt6/e5MWGhg2SFHv3Aa8N919n1MjfRumn1KbjrAeMU1zu
fYh3EzMclBKKL+cOwVfb14tbE0OnpB8XJ6ipPWiCIQ9E8WeGhEsyDoFUivNt0IPN
t3dGAuTUqKC0PRF2kJ1ct5pni03G2B0iiQopTQxB8Ca5dMUQ0S8=
=YRMA
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm-dt-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.18
- External interrupt (INTC-EX) support for the R-Car V3U SoC,
- Initial support for the RZ/G2LC and RZ/V2L SoCs, and the RZ/G2LC and
RZ/V2L SMARC EVK development boards,
- Support for MAX9286 GMSL deserializers and GSML cameras on the Eagle
and Condor development boards,
- NAND support for the RZ/N1D SoC,
- DMA engine (SYS-DMAC) support for the R-Car S4-8 SoC,
- LVDS support for the R-Car M3-W+ SoC,
- HDMI output and 9-axis sensor support for the Kingfisher (ULCB
extension) board,
- MAX96712 GMSL serializer support for the Falcon development board,
- MOST network support for the R-Car H3, M3-W, M3-W+, M3-N, E3, and D3
SoCs,
- Miscellaneous fixes and improvements.
* tag 'renesas-arm-dt-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (27 commits)
arm64: dts: renesas: rzg2lc-smarc: Use SW_SD0_DEV_SEL macro for eMMC/SDHI device selection
arm64: dts: renesas: rzg2lc-smarc: Enable CANFD channel 1
arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board
arm64: dts: renesas: rzg2lc-smarc: Add macros for DIP-Switch settings
arm64: dts: renesas: rzg2l-smarc: Add common dtsi file
arm64: dts: renesas: rzg2lc-smarc: Enable microSD on SMARC platform
arm64: dts: renesas: rzg2lc-smarc-som: Enable eMMC on SMARC platform
arm64: dts: renesas: Add initial device tree for RZ/V2L SMARC EVK
arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC
dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions
arm64: dts: renesas: ulcb/ulcb-kf: switch to use audio-graph-card2 for sound
arm64: dts: renesas: rcar-gen3: Add MOST devices
arm64: dts: renesas: Miscellaneous whitespace fixes
arm64: dts: renesas: falcon-csi-dsi: Add and connect MAX96712
arm64: dts: renesas: ulcb-kf: Add 9-asix sensor device
arm64: dts: renesas: ulcb-kf: Add KF HDMI output
arm64: dts: renesas: r8a77961: Add lvds0 device node
arm64: dts: renesas: r8a779f0: Add sys-dmac nodes
ARM: dts: r9a06g032: Describe the NAND controller
arm64: dts: renesas: Add GMSL cameras .dtsi
...
Link: https://lore.kernel.org/r/cover.1644587200.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Conversion of Samsung pinctrl bindings to dtschema followed up with
alignment of DTS files to the dtschema.
The entire work consists of three parts but everything should be merged
at once to avoid dtschema check errors:
1. Samsung pinctrl driver change necessary to accept new DTS (driver
depends on node names and this has to be adjusted because of dtschema).
2. Conversion to dtschema which brings requirement of different naming
of the GPIO nodes.
3. DTS commits depending on driver (1) above, which convert all GPIO pin
bank names to new naming, required by dtschema.
This also includes few cleanups around DTS which are here to avoid
any merge conflicts.
The Samsung pinctrl driver changes are backwards compatible. However
the DTS changes (renaming nodes) could cause problems in out-of-tree or
other project implementations of the driver.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmH1KTEQHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD11PfD/4tFiY40inEHZIjWSrIB/D3RZhVzslSeT2d
bABVtync3w0gTQZpT/E06XtSGrxLFh0hEa9ZJp94whiSFQ8xO8ziJONdp7T0zkzM
cJNufT5bsROGIhlnqX7FjZVyuqTKla1Uch5BwLbC1+0jeNFeic6tUXyWgk+ds0Dh
mmyKNNNpPW0kU5PTmk2rHxK171JCS7id4mpGCujqvMaBPB4RXHQJ/qjV/3e0QvmY
eReX+QVeMyeGg0UcFvxaVVT1Nw5TgFRzA9cOaIJ/JXbi/Jp7PagkvB6ZHk7smR7V
dxnPyQoASx41NPNRifVLUFmsGfrBzMO22JYHEzu0P7effbMLxDZoTU1lsBXWLDad
q7zWf9OpEK3hEwVM7vSwPZpLH14P7MqKvaDYEW1OdbC2zW3wT5McodUhCAdHsCxx
0iCmWxoOV8JyP8MbmW2I5o5Nw7lUW8hKg5KGYnUK6DLFDCkn8OP1XA+pnwr50H4t
FqGjKdLAjddId8KIEI+FO5O59kpPm082B71rpR/97D4nOaPOWfvv9NDRcwXbmkOv
nUPM/By6XwXo8NfdU/rcwJDGwDv1fe+nNVDU0aKXNLVhpGO3dkR6l14VQsQrsH2E
Dd4Hmio3HBClLGREkCbl0+5H9+a+ACOQ11XJlXmmHJkwb5SzmM2CYQRNxE6NxArd
3s63FKVA1w==
=aFcq
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY5fwACgkQmmx57+YA
GNn37xAAiwrsEdyqDFerNB/JVUJRLlw93TY6PojPnsj60x98UfeJbcgPeEUjYNPk
hl3HIOtpyrHom1UmqJXFROKSNq+S/rwfOJS67uwtYBgM7YwU3KCHVIeJbT1Pzwzm
dE80TSX1nolTFctCsI90mQzN72tRJbQZhvz8vP7FlkOLDe7YFIjy1j5gGify+d4J
M1YnMRVSCEA4Ba7bggQL7RWfhLzwkT4lEYLRkSGpH0kGmnW/2s+4iCxDMTqfjufF
NYP+3ctDmXfReDInkvdVHHT/F5f04C0r6JO+S7+Hvo0SJAE1zPAsNcST/dkE9hsQ
0W8VP3+EviU/k9Gmd3fPBfzX0zWzeEIaQwn3i9XVkIE4QGgXcwNOTksWgBAqyRj7
Bc6qNLmFK79dLIavRp1jmZzdDpK8yLHrVhcQjppmBBHcjW6BdBf7LN6ZYjr65qlo
ecITWLzkVLOL7iTGlLvgU1NYKUKpOJ98w2a86DbX3iAg1m1o0i0pABGCQurpUdKJ
od1y8o+xMT3+zEyK+K/Rx+ugXny1nm08qbkaApJu0yKaS5c0UhTQWPqrqvZfe+Jp
Am2KPG4EM+dDaUOj5MSItt4DeyBWQqmdLGiPJbxrVK9rmYW7CO3CotwOJU2E3St7
0dv7wRkfmuwbEt9BF9ITuNjLUXM60eR94IJV345QVxi6lVYg6ho=
=CjdH
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt-pinctrl-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Samsung pinctrl DTS and driver changes for v5.18
Conversion of Samsung pinctrl bindings to dtschema followed up with
alignment of DTS files to the dtschema.
The entire work consists of three parts but everything should be merged
at once to avoid dtschema check errors:
1. Samsung pinctrl driver change necessary to accept new DTS (driver
depends on node names and this has to be adjusted because of dtschema).
2. Conversion to dtschema which brings requirement of different naming
of the GPIO nodes.
3. DTS commits depending on driver (1) above, which convert all GPIO pin
bank names to new naming, required by dtschema.
This also includes few cleanups around DTS which are here to avoid
any merge conflicts.
The Samsung pinctrl driver changes are backwards compatible. However
the DTS changes (renaming nodes) could cause problems in out-of-tree or
other project implementations of the driver.
* tag 'samsung-dt-pinctrl-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (28 commits)
arm64: dts: exynos: use dedicated wake-up pinctrl compatible in ExynosAutov9
ARM: dts: s5pv210: align pinctrl with dtschema
ARM: dts: s3c64xx: align pinctrl with dtschema
ARM: dts: s3c24xx: align pinctrl with dtschema
arm64: dts: exynos: align pinctrl with dtschema in ExynosAutov9
arm64: dts: exynos: align pinctrl with dtschema in Exynos7
arm64: dts: exynos: align pinctrl with dtschema in Exynos5433
ARM: dts: exynos: align pinctrl with dtschema in Exynos542x/5800
ARM: dts: exynos: align pinctrl with dtschema in Exynos5410
ARM: dts: exynos: align pinctrl with dtschema in Exynos5260
ARM: dts: exynos: align pinctrl with dtschema in Exynos5250
ARM: dts: exynos: align pinctrl with dtschema in Exynos4412
ARM: dts: exynos: align pinctrl with dtschema in Exynos4210
ARM: dts: exynos: align pinctrl with dtschema in Exynos3250
ARM: dts: s3c64xx: drop unneeded pinctrl wake-up interrupt mapping
ARM: dts: exynos: simplify PMIC DVS pin configuration in Peach Pi
ARM: dts: exynos: override pins by label in Peach Pi
ARM: dts: exynos: simplify PMIC DVS pin configuration in Peach Pit
ARM: dts: exynos: override pins by label in Peach Pit
ARM: dts: exynos: simplify PMIC DVS pin configuration in Odroid XU
...
Link: https://lore.kernel.org/r/20220129115352.13274-1-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
1. Minor improvements and dtschema fixes (node names, properties).
2. Fix issues pointed out by DT schema checks:
- Add necessary clock controller inputs on Exynos5260.
- Drop unsupported regulators on Odroid XU.
- Add USB DWC3 supplies.
- Drop old thermal properties from Exynos4210.
3. Add support for Samsung Chagall WiFi (Exynos5420, Samsung Galaxy Tab
S 10.5", SM-T800 ) and a similar Samsung Klimt WiFi (Samsung Galaxy
Tab S 8.4").
4. Add battery to Samsung P4Nnote (Exynos4412, Samsung Galaxy Note
10.1).
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmID09wQHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD1+WKD/wLP4YW8lKuGiZmt3Jxc/Vo4mcWha8iV4aN
v0cMPu0C6RQxHqHop4ZeJ5UOa6/2MAEadz3urWymhQNugXr3tfd+NNcBF5zVJlYa
JZfgTHtgAKnUgJzItsvOmWvUeVwKYtDGMSKlyZ5140Z8HFTaQZZwCwRj+VK8BvTn
d9F53l++xiF3w8H70qkJLGdDyMZu181f011XjFqIAYPIPPvxr3J//L4nnClVEtoq
vJROI3dMg5UKuJZcjiyYIRlFwdFWc+Q1ZE8mW5d2MUDvkQWBHaMCpzVJrZpNtfo4
1omH+dGtULF46kluhOE9CEf/yU0dAaoIjCD8Jq6vXkdICHqd78/u9dP5wb2xokcy
KZ3SxYXxQbyrWtkj9/PALIujD3GIN/t/PgncGfKXFPej8W3g6TCEw8rW9q0Ds9oo
Ws4HYcfPIaiSXxRjfEumPmQC8VIlkL8E4DTpZT6O/O84G9Ri3km0mFX/q9vA9uHq
WIanSCkIAVfIngQDO3cn5Lb06D4sA4e7TAph2sOl/xRMwhDdxBhrE8D5egBoJKX0
llwcxBnxQao/Au8/3/rdsaj0owaskD4PHEKHDaFSDIbHOJc1RC97zRRZR3eaPHW7
FC7KEq8g82VLGvOKkSG0mKQI8qokv2niWt3rYtnS38sk7QBsOwzTE90SrJPvTI20
GFTqWrqLCg==
=N8hw
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY5B8ACgkQmmx57+YA
GNnORxAAwpLqzk7pu1boMKntDoIO5FI06f5rSN9XpfgsclUUpL3GnPO3fH+N8DEY
C9gtVkUFVVz2r/C/8U/Y6/n076lFaY+pIBYMWZaWhmP5npKvuLMSTtDNJnsg5imb
SbL2B3sK4cNg7dnWHYngRgNDSa82I5LFLP/lNyRYbpmfjtusJb3bF4/bpyDKwDOt
4Psk8Nn+Sqv3wxjyqij4FNV0nfD/TRMAZLcqyTrtunU4Oqt4+E6l2Dl/NSfE+WVL
cmn1eDf8Y8fCg/ufUC0lm2jza2GXFe7Hy1lC53qxCHyulO5F74wNu//oYvTrVuLW
Jyqs1/HRCcymoVe/g3oox4BK61yRX+h8m2HX3OQq2MDTid/YU/DsUuY0dy6Q/TGy
3BtTSAkyCdbVwaJWuv1LSIJpnO9cHtfvKkhZSK2YsriNPTStHEs6CnAMigiMSDF8
I+HkcTwJrfRBhBgfckXtk0xc6E5hJXyarAsqcp1m475ChVnWqrtzXBOw32jLaSkR
HOuqSbMBcx/MQ6BVVbeB/AM4FUurn+0uS8HyyYq6TrNxqkywwC6MxjfSVsl/jL69
JLiP4PkoWAjWZN+wXOEwK2fk/5pusWQl93XZne/xKCdveoIC+s6BKo0mhm6kr3MG
XyLJmvO0dQPgnFy+gYEHnByFQDHirlJ6k4QTa8ap6nU1xmZ14P0=
=DfMW
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Samsung DTS ARM changes for v5.18
1. Minor improvements and dtschema fixes (node names, properties).
2. Fix issues pointed out by DT schema checks:
- Add necessary clock controller inputs on Exynos5260.
- Drop unsupported regulators on Odroid XU.
- Add USB DWC3 supplies.
- Drop old thermal properties from Exynos4210.
3. Add support for Samsung Chagall WiFi (Exynos5420, Samsung Galaxy Tab
S 10.5", SM-T800 ) and a similar Samsung Klimt WiFi (Samsung Galaxy
Tab S 8.4").
4. Add battery to Samsung P4Nnote (Exynos4412, Samsung Galaxy Note
10.1).
* tag 'samsung-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (22 commits)
ARM: dts: exynos: use generic node name for LPDDR3 timings in Odroid
ARM: dts: exynos: add charger and battery to p4note
ARM: dts: exynos: update dma node name with dtschema
ARM: dts: exynos: use define for TMU clock on Exynos4412
ARM: dts: exynos: drop old thermal properties from Exynos4210
ARM: dts: exynos: add fake USB DWC3 supplies to SMDK5410
ARM: dts: exynos: add USB DWC3 supplies to SMDK5420
ARM: dts: exynos: add USB DWC3 supplies to Chromebook Peach Pi
ARM: dts: exynos: add USB DWC3 supplies to Chromebook Peach Pit
ARM: dts: exynos: add USB DWC3 supplies to ArndaleOcta
ARM: dts: exynos: add USB DWC3 supplies to Chromebook Spring
ARM: dts: exynos: add USB DWC3 supplies to Chromebook Snow
ARM: dts: exynos: add USB DWC3 supplies to SMDK5250
ARM: dts: exynos: add USB DWC3 supplies to Arndale
ARM: dts: exynos: Add support for Samsung Klimt WiFi
dt-bindings: arm: samsung: document Klimt WiFi board binding
ARM: dts: exynos: Add support for Samsung Chagall WiFi
dt-bindings: arm: samsung: document Chagall WiFi board binding
ARM: dts: exynos: drop unsupported MAX77802 regulators on Odroid XU
ARM: dts: exynos: add necessary clock controller inputs in Exynos5260
...
Link: https://lore.kernel.org/r/20220209145226.184375-1-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add Tesla FSD SoC ARM64 platform: bindings, DTSI+DTS, maintainer's entry
and defconfig change. This brings and enables this new platform.
This includes clock controller bindings (header files with clock IDs)
which are shared also with Tesla FSD SoC clock controller pull request.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmH9SB0QHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD1zpnD/9xV+X85LiKRWWuYeDtLBOzwuqCKAEVBX+U
ZVGEuS675Ha4RrskEOWHBqxBePV7dposFaBWv59wGlnTESrz4N5jtdQu8WJYatp0
WzTTpgdmQBldKHjS1xtEBK7aZ3UOfvGEEGh+dkIX8U+DxdSzfil10XpnLeplOLUs
pzpb8YdwSKX4VwRTRNuZpthN/VKTcIykANvm+DbKEl8F5kFjHWrlPFgU11XmLzZp
ngzB2AeNHWqSjDJR/JZjbjlF7SsFCbfVTYBVLVoiiHKDVgpds6rM1LiR9OjY9skp
W8egM8q2tO7mVNdFnNEK1k/CaioJUgBhEFUdxycR8Q0YoJP2dRnvQ3kEEI30suGY
EoNULUyLLa61yMIgzQ8RF8RBo/Pb9lJDvr4DyG8InDANr9Y9bLHqi4Rmm4h6BJYb
Y5cEhorY8qCmxBvllj9PdjCO0e1FanxO+RsVBgzDw3iBo6mrGXdFy1CppZ3BUSI1
NcNc5D5TRIkSo8JU9gFe+bVCjI2h1QQkZFERraH2f801wKQi7kD7/c8TE2KQR6Ej
uz7BRA9cIlE2tDqzWVtmSM+ida5c8CsTGknk1aWKM6cwGB5wM6JhHnJfg4mBUGZj
BCdUmRfqRYX4+2E01YyUjbqjbSGxYkvyPPw9LBr2ii3di4G7FInwfyrvD4O7IBBL
UUn0MFjD3w==
=tXfh
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY47wACgkQmmx57+YA
GNnklg/8CNnZyxSIOo258Bixbpf7ArNIVXuwd2mDUQO5w/dt6/y1HPErk1x/FJO5
u4x3ugyCOJOPXnZy/We38M1NXJI7+RWfkvnHObGGLqsHf6YPICEUZqAlVuAT0fJn
eWGTD1XOmf3m7r6xpSn8W6dxZ31tU/ST3WcecSBEcX4URJULdtF5Umqyh7RXTjYL
HX3QvJwKxeNCnIUbsPJK7Iq0Y77AFgzPpn7iSO4qiP5lAK+YWRuT8jQKaIOGKJxz
lw5rkYhq8pQD0Amlm/DYxrvfJJZEU83FEzMxx9ZmeeU3LoixVvWgA2H0phjZP03k
0sbshjOhUSLFIfduk1oZSbkYxQAsDsF8r1Jvrbr5LrVI+2C7vQoqTwG+neaqksnp
CmNYDvAhugdVGHBGZTeQzeVMq8swV5o+3DJtlnKPp6gXlrJjFOECE63F4f1Pc+Fi
CE9KRBLqFSrdHyAfi3bwAcS8tTnhRYx6I6NYjCp+qa4wEREw8X8HBLDRemWsoqB2
T19W864mkGPPbkmxaf5/F9LcJNU8tSd86E3hSIn1fgusEKTkv50KaEZ0GrLV45ou
GYTAYfIVRG+9RZpQOlmHPMAJ2DIoHB1EXrvPmD73Tyrgo3sZhftClNkikZKbDGDp
XplUjSnClvsUBe4cbO4zVw/s7wQwIe8x+CEl/3Ry2L6MV/fysMY=
=l8Oq
-----END PGP SIGNATURE-----
Merge tag 'tesla-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Tesla FSD ARM64 changes for v5.18
Add Tesla FSD SoC ARM64 platform: bindings, DTSI+DTS, maintainer's entry
and defconfig change. This brings and enables this new platform.
This includes clock controller bindings (header files with clock IDs)
which are shared also with Tesla FSD SoC clock controller pull request.
* tag 'tesla-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: fsd: Add SPI device nodes
arm64: defconfig: Enable Tesla FSD SoC
arm64: dts: fsd: Add initial pinctrl support
arm64: dts: fsd: Add initial device tree support
dt-bindings: clock: Document FSD CMU bindings
dt-bindings: clock: Add bindings definitions for FSD CMU blocks
dt-bindings: arm: add Tesla FSD ARM SoC
dt-bindings: add vendor prefix for Tesla
Link: https://lore.kernel.org/r/20220204154112.133723-2-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
On ELF, (NOLOAD) sets the section type to SHT_NOBITS[1]. It is conceptually
inappropriate for .plt and .text.* sections which are always
SHT_PROGBITS.
In GNU ld, if PLT entries are needed, .plt will be SHT_PROGBITS anyway
and (NOLOAD) will be essentially ignored. In ld.lld, since
https://reviews.llvm.org/D118840 ("[ELF] Support (TYPE=<value>) to
customize the output section type"), ld.lld will report a `section type
mismatch` error. Just remove (NOLOAD) to fix the error.
[1] https://lld.llvm.org/ELF/linker_script.html As of today, "The
section should be marked as not loadable" on
https://sourceware.org/binutils/docs/ld/Output-Section-Type.html is
outdated for ELF.
Tested-by: Nathan Chancellor <nathan@kernel.org>
Reported-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Fangrui Song <maskray@google.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20220218081209.354383-1-maskray@google.com
Signed-off-by: Will Deacon <will@kernel.org>
cpu_has_fwb() is supposed to warn user is following architectural
requirement is not valid:
LoUU, bits [29:27] - Level of Unification Uniprocessor for the cache
hierarchy.
Note
When FEAT_S2FWB is implemented, the architecture requires that
this field is zero so that no levels of data cache need to be
cleaned in order to manage coherency with instruction fetches.
LoUIS, bits [23:21] - Level of Unification Inner Shareable for the
cache hierarchy.
Note
When FEAT_S2FWB is implemented, the architecture requires that
this field is zero so that no levels of data cache need to be
cleaned in order to manage coherency with instruction fetches.
It is not really clear what user have to do if assertion fires. Having
assertions about the CPU design like this inspire even more assertions
to be added and the kernel definitely is not the right place for that,
so let's remove cpu_has_fwb() altogether.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Link: https://lore.kernel.org/r/20220224164739.119168-1-vladimir.murzin@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
under low power state a SoundWire Wake IRQ could trigger MBHC interrupts
so make sure that codec is not in suspended state when this happens.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220224111718.6264-17-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
For SoundWire Frame sync to be generated correctly we need both MCLK
and MCLKx2 (npl). Without pm runtime enabled these two clocks will remain on,
however after adding pm runtime support its possible that NPl clock could be
turned off even when SoundWire controller is active.
Fix this by enabling mclk and npl clk when SoundWire clks are enabled.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220224111718.6264-10-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
For SoundWire Frame sync to be generated correctly we need both MCLK
and MCLKx2 (npl). Without pm runtime enabled these two clocks will remain on,
however after adding pm runtime support its possible that NPl clock could be
turned off even when SoundWire controller is active.
Fix this by enabling mclk and npl clk when SoundWire clks are enabled.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220224111718.6264-9-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
For SoundWire Frame sync to be generated correctly we need both MCLK
and MCLKx2 (npl). Without pm runtime enabled these two clocks will remain on,
however after adding pm runtime support its possible that NPl clock could be
turned off even when SoundWire controller is active.
Fix this by enabling mclk and npl clk when SoundWire clks are enabled.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220224111718.6264-8-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Using bulk clocks and referencing them individually using array index is
not great for readers.
So move them to individual clocks handling and also remove some unnecessary
error handling in the code.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220224111718.6264-7-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Using bulk clocks and referencing them individually using array index is
not great for readers.
So move them to individual clocks handling and also remove some unnecessary
error handling in the code.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220224111718.6264-6-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Using bulk clocks and referencing them individually using array index is
not great for readers.
So move them to individual clocks handling and also remove some unnecessary
error handling in the code.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220224111718.6264-5-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Using bulk clocks and referencing them individually using array index is
not great for readers.
So move them to individual clocks handling and also remove some unnecessary
error handling in the code.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220224111718.6264-2-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
* kvm-arm64/psci-1.1:
: .
: Limited PSCI-1.1 support from Will Deacon:
:
: This small series exposes the PSCI SYSTEM_RESET2 call to guests, which
: allows the propagation of a "reset_type" and a "cookie" back to the VMM.
: Although Linux guests only ever pass 0 for the type ("SYSTEM_WARM_RESET"),
: the vendor-defined range can be used by a bootloader to provide additional
: information about the reset, such as an error code.
: .
KVM: arm64: Remove unneeded semicolons
KVM: arm64: Indicate SYSTEM_RESET2 in kvm_run::system_event flags field
KVM: arm64: Expose PSCI SYSTEM_RESET2 call to the guest
KVM: arm64: Bump guest PSCI version to 1.1
Signed-off-by: Marc Zyngier <maz@kernel.org>
fix issue
/builds/robherring/linux-dt/Documentation/devicetree/bindings/spi/spi-sunplus-sp7021.example.dt.yaml:
spi@9C002D80: 'clocks-names' is a required property
From schema: /builds/robherring/linux-dt/Documentation/devicetree/bindings/spi/spi-sunplus-sp7021.yaml
delete unused required(clock-name)
Fixes: 3b8ab4da34 ("spi: Fix test error for sp7021")
Reported-by: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Li-hao Kuo <lhjeff911@gmail.com>
Link: https://lore.kernel.org/r/097bbc8b703b17e8fb3e3f6f6d2f97fe668bd5c5.1645770648.git.lhjeff911@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This patch fixes the tristate configuration for i2c3 function assigned
to the dtf pins on the Tamonten Tegra20 SoM.
Signed-off-by: Richard Leitner <richard.leitner@skidata.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
