The code to set the shifter STe palette registers has a long
standing operator precedence bug, manifesting as colors set
on a 2 bits per pixel frame buffer coming up with a distinctive
blue tint.
Add parentheses around the calculation of the per-color palette
data before shifting those into their respective bit field position.
This bug goes back a long way (2.4 days at the very least) so there
won't be a Fixes: tag.
Tested on ARAnyM as well on Falcon030 hardware.
Cc: stable@vger.kernel.org
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Link: https://lore.kernel.org/all/CAMuHMdU3ievhXxKR_xi_v3aumnYW7UNUO6qMdhgfyWTyVSsCkQ@mail.gmail.com
Tested-by: Michael Schmitz <schmitzmic@gmail.com>
Tested-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Michael Schmitz <schmitzmic@gmail.com>
Signed-off-by: Helge Deller <deller@gmx.de>
Tag all the coded formats where the s5p_mfc decoder supports dynamic
resolution switching or has a bytestream parser.
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Removes the redundant TEE_SHM_DMA_BUF, TEE_SHM_EXT_DMA_BUF,
TEE_SHM_MAPPED and TEE_SHM_KERNEL_MAPPED flags.
TEE_SHM_REGISTER is renamed to TEE_SHM_DYNAMIC in order to better
match its usage.
Assigns new values to the remaining flags to void gaps.
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
tee_shm_register() is replaced by the previously introduced functions
tee_shm_register_user_buf() and tee_shm_register_kernel_buf().
Since there are not external callers left we can remove tee_shm_register()
and refactor the remains.
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Uses the new simplified tee_shm_register_kernel_buf() function instead
of the old tee_shm_alloc() function which required specific
TEE_SHM-flags
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Adds the two new functions tee_shm_register_user_buf() and
tee_shm_register_kernel_buf() which should be used instead of the old
tee_shm_register().
This avoids having the caller supplying the flags parameter which
exposes a bit more than desired of the internals of the TEE subsystem.
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Adds a common helper function to free a tee_shm allocated using the
helper function optee_pool_op_alloc_helper().
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
tee_shm_alloc() is replaced by three new functions,
tee_shm_alloc_user_buf() - for user mode allocations, replacing passing
the flags TEE_SHM_MAPPED | TEE_SHM_DMA_BUF
tee_shm_alloc_kernel_buf() - for kernel mode allocations, slightly
optimized compared to using the flags TEE_SHM_MAPPED | TEE_SHM_DMA_BUF.
tee_shm_alloc_priv_buf() - primarily for TEE driver internal use.
This also makes the interface easier to use as we can get rid of the
somewhat hard to use flags parameter.
The TEE subsystem and the TEE drivers are updated to use the new
functions instead.
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Replaces the shared memory pool based on two pools with a single pool.
The alloc() function pointer in struct tee_shm_pool_ops gets another
parameter, align. This makes it possible to make less than page aligned
allocations from the optional reserved shared memory pool while still
making user space allocations page aligned. With in practice unchanged
behaviour using only a single pool for bookkeeping.
The allocation algorithm in the static OP-TEE shared memory pool is
changed from best-fit to first-fit since only the latter supports an
alignment parameter. The best-fit algorithm was previously the default
choice and not a conscious one.
The optee and amdtee drivers are updated as needed to work with this
changed pool handling.
This also removes OPTEE_SHM_NUM_PRIV_PAGES which becomes obsolete with
this change as the private pages can be mixed with the payload pages.
The OP-TEE driver changes minimum alignment for argument struct from 8
bytes to 512 bytes. A typical OP-TEE private shm allocation is 224 bytes
(argument struct with 6 parameters, needed for open session). So with an
alignment of 512 well waste a bit more than 50%. Before this we had a
single page reserved for this so worst case usage compared to that would
be 3 pages instead of 1 page. However, this worst case only occurs if
there is a high pressure from multiple threads on secure world. All in
all this should scale up and down better than fixed boundaries.
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Adds a new function tee_shm_alloc_user_buf() for user mode allocations,
replacing passing the flags TEE_SHM_MAPPED | TEE_SHM_DMA_BUF to
tee_shm_alloc().
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
None of the drivers in the TEE subsystem uses
tee_shm_pool_alloc_res_mem() so remove the function.
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Uses the new simplified tee_shm_alloc_kernel_buf() function instead of
the old deprecated tee_shm_alloc() function which required specific
TEE_SHM-flags.
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Since Commit ed7c9870c9 ("Input: of_touchscreen - add support for
inverted / swapped axes"), the of_touchscreen interface supports axis
inverting and swapping through device tree properties. Make use of this
feature.
Signed-off-by: Yunus Bas <y.bas@phytec.de>
Link: https://lore.kernel.org/r/20220209223933.1672782-1-y.bas@phytec.de
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cleanup following nodes:
1. Remove redundant i2c1 node.
2. Disable in-chip rtc, use battery-backed external rtc (pcf85263)
instead.
Signed-off-by: Potin Lai <potin.lai@quantatw.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Link: https://lore.kernel.org/r/20220215163151.32252-11-potin.lai@quantatw.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Enable mdio3 bus based on EVT HW.
So far lack of c45 support in mdio-aspeed, at least can access mdio bus
by read/write register.
TODO: Add Marvell PHY 88X3310 and mdio-aspeed driver c45 support
Signed-off-by: Potin Lai <potin.lai@quantatw.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Link: https://lore.kernel.org/r/20220215163151.32252-10-potin.lai@quantatw.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Add INA230 node on each sled based on EVT HW.
Signed-off-by: Potin Lai <potin.lai@quantatw.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Link: https://lore.kernel.org/r/20220215163151.32252-9-potin.lai@quantatw.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Fix with correct shunt-resistor value base on EVT HW.
Signed-off-by: Potin Lai <potin.lai@quantatw.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Link: https://lore.kernel.org/r/20220215163151.32252-8-potin.lai@quantatw.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Enable interrupt support for all sledx_ioexp, so userspace can monitor
gpio from io expander by interrupt.
Signed-off-by: Potin Lai <potin.lai@quantatw.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Link: https://lore.kernel.org/r/20220215163151.32252-7-potin.lai@quantatw.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Switch spi2 to spi-gpio driver to avoid unstable signal issue with EVT
HW.
Remove spi2 node and create a new spi2_gpio node.
Signed-off-by: Potin Lai <potin.lai@quantatw.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Link: https://lore.kernel.org/r/20220215163151.32252-6-potin.lai@quantatw.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Add flash1 in fmc to support dual flash module.
Signed-off-by: Potin Lai <potin.lai@quantatw.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Link: https://lore.kernel.org/r/20220215163151.32252-5-potin.lai@quantatw.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Separate gpio-leds by each io expander chip.
To avoid entire gpio-leds bind failed due to single chip not available
Signed-off-by: Potin Lai <potin.lai@quantatw.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Link: https://lore.kernel.org/r/20220215163151.32252-3-potin.lai@quantatw.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
Switch sled to 1-based to meet OpenBMC multi-host numbering rule
Signed-off-by: Potin Lai <potin.lai@quantatw.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Patrick Williams <patrick@stwcx.xyz>
Link: https://lore.kernel.org/r/20220215163151.32252-2-potin.lai@quantatw.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
The commit
a5886ef4f4 ("gve: Introduce per netdev `enum gve_queue_format`")
introduces three queue format type, only GVE_GQI_QPL_FORMAT queue has
page list. So it should use the queue page list number to detect the
zero size queue page list. Correct the design logic.
Using the 'queue_format == GVE_GQI_RDA_FORMAT' may lead to request zero
sized memory allocation, like if the queue format is GVE_DQO_RDA_FORMAT.
The kernel memory subsystem will return ZERO_SIZE_PTR, which is not NULL
address, so the driver can run successfully. Also the code still checks
the queue page list number firstly, then accesses the allocated memory,
so zero number queue page list allocation will not lead to access fault.
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Reviewed-by: Bailey Forrest <bcf@google.com>
Link: https://lore.kernel.org/r/20220215051751.260866-1-haiyue.wang@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
The PS/2 bus defines the data and clock line be open drain, therefore
for both enforce the particular GPIO flags in the driver.
Without enforcing to flag at least the clock gpio as open drain we run
into the following warning:
WARNING: CPU: 1 PID: 40 at drivers/gpio/gpiolib.c:3175 gpiochip_enable_irq+0x54/0x90
gpiochip_enable_irq() warns on a GPIO being configured as output while
serving as IRQ source without being flagged as open drain.
Signed-off-by: Danilo Krummrich <danilokrummrich@dk-develop.de>
Link: https://lore.kernel.org/r/20220215180829.63543-4-danilokrummrich@dk-develop.de
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Sending the data before processing the stop bit from the device already
saves the data of the current xfer in case the stop bit is missed.
However, when TX xfers are enabled this introduces a race condition when
a peripheral driver using the bus immediately requests a TX xfer from IRQ
context.
Therefore the data must be send after receiving the stop bit, although
it is possible the data is lost when missing the stop bit.
Signed-off-by: Danilo Krummrich <danilokrummrich@dk-develop.de>
Link: https://lore.kernel.org/r/20220215160208.34826-5-danilokrummrich@dk-develop.de
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Actually, there's no extra clock pulse to wait for.
The assumption of an extra clock pulse was mistakenly derived from the
fact that by the time this driver was introduced the GPIO controller of
the test machine (bcm2835) generated spurious interrupts.
Since now spurious interrupts are handled properly this can and must be
removed in order to make TX xfers work properly.
While at it, remove duplicate gpiod_direction_input(). The data gpio
must already be configured to act as input when receiving the ACK bit.
This patch is tested with the original hardware (peripherals and board)
the driver was developed on.
Signed-off-by: Danilo Krummrich <danilokrummrich@dk-develop.de>
Link: https://lore.kernel.org/r/20220215160208.34826-4-danilokrummrich@dk-develop.de
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Using jiffies for the IRQ timekeeping is not sufficient for two reasons:
(1) Usually jiffies have a resolution of 1ms to 10ms. The IRQ intervals
based on the clock frequency of PS2 protocol specification (10kHz -
16.7kHz) are between ~60us and 100us only. Therefore only those IRQ
intervals can be detected which are either at the end of a transfer
or are overly delayed. While this is sufficient in most cases, since
we have quite a lot of ways to detect faulty transfers, it can
produce false positives in rare cases: When the jiffies value
changes right between two interrupt that are in time, we wrongly
assume that we missed one or more clock cycles.
(2) Some gpio controllers (e.g. the one in the bcm283x chips) may generate
spurious IRQs when processing interrupts in the frequency given by PS2
devices.
Both issues can be fixed by using ktime resolution for IRQ timekeeping.
However, it is still possible to miss clock cycles without detecting
them. When the PS2 device generates the falling edge of the clock signal
we have between ~30us and 50us to sample the data line, because after
this time we reach the next rising edge at which the device changes the
data signal already. But, the only thing we can detect is whether the
IRQ interval is within the given period. Therefore it is possible to
have an IRQ latency greater than ~30us to 50us, sample the wrong bit on
the data line and still be on time with the next IRQ. However, this can
only happen when within a given transfer the IRQ latency increases
slowly.
___ ______ ______ ______ ___
\ / \ / \ / \ /
\ / \ / \ / \ /
\______/ \______/ \______/ \______/
|-----------------| |--------|
60us/100us 30us/50us
Signed-off-by: Danilo Krummrich <danilokrummrich@dk-develop.de>
Link: https://lore.kernel.org/r/20220215160208.34826-3-danilokrummrich@dk-develop.de
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Refactor struct ps2_gpio_data in order to clearly separate RX and TX
state data.
This change intends to increase code readability and does not bring any
functional change.
Signed-off-by: Danilo Krummrich <danilokrummrich@dk-develop.de>
Link: https://lore.kernel.org/r/20220215160208.34826-2-danilokrummrich@dk-develop.de
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
This driver works just fine with the BT404 version of the touchscreen
as well. Tested on the Samsung GT-I8160 (Codina) mobile phone.
Add all the new variants from the binding document so people can
easily test them, we believe most of them work more or less.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20220214234033.1052681-1-linus.walleij@linaro.org
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
As LaTeX macros for CJK font settings can have Latin-script font
settings as well, settings under Documentation/translations/ can
be moved to the main conf.py.
By this change, translations.pdf built by top-level "make pdfdocs"
can have properly aligned ascii-art diagrams except for Korean
ones.
For the reason of remaining misalignment in Korean diagrams, see
changelog of commit a90dad8f61 ("docs: pdfdocs: Add conf.py
local to translations for ascii-art alignment").
Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
Cc: Jonathan Corbet <corbet@lwn.net>
Link: https://lore.kernel.org/r/eb87790a-03f4-9f29-c8a3-ef2c3e78ca18@gmail.com
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
On systems without "Noto Sans CJK" fonts, CJK chapters in
translations.pdf are full of "TOFU" boxes, with a long build time and
a large log file containing lots of missing-font warnings.
Avoid such waste of time and resources by skipping CJK chapters when
CJK fonts are not available.
To skip whole chapters, change the definition of
\kerneldocBegin{SC|TC|KR|JP} commands so that they can have an argument
to be ignored.
This works as far as the argument (#1) is not used in the command.
In place of skipped contents, put a note on skipped contents at the
beginning of the PDF.
Change the call sites in index.rst of CJK translations accordingly.
When CJK fonts are available, existing command definitions with
no argument just work. LaTeX engine will see additional pairs of
"{" and "}", which add a level of grouping without having any effect
on typesetting.
Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
Cc: Jonathan Corbet <corbet@lwn.net>
Link: https://lore.kernel.org/r/3359ca41-b81d-b2c7-e437-7618efbe241d@gmail.com
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Korean (Hangul) titles in Table of Contents of translations.pdf
don't have inter-phrase spaces.
This is because the CJKspace option of xeCJK is disabled by
default.
Restore the spaces by enabling the option at the beginning of every
document and disable it in the \kerneldocBegin{SC|TC|JP} commands.
Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
Cc: Jonathan Corbet <corbet@lwn.net>
Link: https://lore.kernel.org/r/19141b3e-01d9-1f6d-5020-42fbda784831@gmail.com
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
xeCJK is enabled in Table of Contents (TOC) so that translations.pdf
built by top-level "make pdfdocs" can have its TOC typeset properly.
This causes quotation marks and apostrophe symbols appear too wide in
Latin-script docs.
This is because (1) Sphinx converts ASCII symbols into multi-byte
UTF-8 ones in LaTeX and (2) in the SC variant of "Noto CJK" font
families, those UTF-8 symbols have full-width glyph.
The KR variant of the font families has half-width glyph for those
symbols and TOC pages should look nicer when it is used instead.
Switch the default CJK font families to the KR variant and teach
xeCJK of those symbols' widths.
To compensate the switch, teach xeCJK of the width in the SC and
TC variants.
Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
Cc: Jonathan Corbet <corbet@lwn.net>
Link: https://lore.kernel.org/r/0c8ea878-0a6f-ea01-ab45-4e66c5facee9@gmail.com
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Sphinx has its own set of width parameters of Table of Contents (TOC)
for LaTeX defined in its class definition of sphinxmanual.cls.
It also inherits parameters for chapter entries from report.cls of
original LaTeX base.
However, they are optimized assuming small documents with tens of
pages and chapters/sections of less than 10.
To cope with some of kernel-doc documents with more than 1000
pages and several tens of chapters/sections, definitions of those
parameters need to be adjusted.
Unfortunately, those parameters are hard coded in the class
definitions and need low-level LaTeX coding tricks to redefine.
As Sphinx 1.7.9 does not have \sphinxtableofcontentshook,
which defines those parameters in later Sphinx versions,
for compatibility with both pre-1.8 and later Sphinx versions,
empty the hook altogether and redefine \@pnumwidth, \l@chapter,
\l@section, and \@subsection commands originally defined in
report.cls.
Summary of parameter changes:
Width of page number (\@pnumwidth): 1.55em -> 2.7em
Width of chapter number: 1.5em -> 1.8em
Indent of section number: 1.5em -> 1.8em
Width of section number: 2.6em -> 3.2em
Indent of subsection number: 4.1em -> 5em
Width of subsection number: 3.5em -> 4.3em
Notes:
1. Parameters for subsection become relevant only when
":maxdepth: 3" is specified under "toctree::" (e.g., RCU/index.rst).
They can hold subsection numbers up to 5 digits such as "18.7.13"
(in RCU.pdf).
2. Number of chapters in driver-api.pdf is getting closer to 100.
When it reaches 100, another set of tweaks will be necessary.
3. The low-level LaTeX trick is mentioned in "Unofficial LaTeX2e
reference manual" at:
http://latexref.xyz/Table-of-contents-etc_002e.html
Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
Cc: Jonathan Corbet <corbet@lwn.net>
Link: https://lore.kernel.org/r/e52b4718-7909-25be-fbc1-76800aa62ae3@gmail.com
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
This fixes some simple grammar errors in the documentation for zram,
specifically errors in the optional feature section of the zram
documentation.
Signed-off-by: Ethan Dye <mrtops03@gmail.com>
Link: https://lore.kernel.org/r/20220207235442.95090-1-mrtops03@gmail.com
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Translate scheduler/sched-energy.rst into Chinese.
Signed-off-by: Tang Yizhou <tangyizhou@huawei.com>
Reviewed-by: Alex Shi <alexs@kernel.org>
Reviewed-by: Yanteng Si <siyanteng@loongson.cn>
Link: https://lore.kernel.org/r/20220208020105.14117-1-tangyizhou@huawei.com
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Recently we added generic "edp-panel"s probed by EDID. To support
panels in this way we look at the panel ID in the EDID and look up the
panel in a table that has power sequence timings. If we find a panel
that's not in the table we will still attempt to use it but we'll use
conservative timings. While it's likely that these conservative
timings will work for most nearly all panels, the performance of
turning the panel off and on suffers.
We'd like to be able to reliably detect the case that we're using the
hardcoded timings without relying on parsing dmesg. This allows us to
implement tests that ensure that no devices get shipped that are
relying on the conservative timings.
Let's add a new debugfs entry to panel devices. It will have one of:
* UNKNOWN - We tried to detect a panel but it wasn't in our table.
* HARDCODED - We're not using generic "edp-panel" probed by EDID.
* A panel name - This is the name of the panel from our table.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220204161245.v2.3.I209d72bcc571e1d7d6b793db71bf15c9c0fc9292@changeid
We'd like panels to be able to add things to debugfs underneath the
connector's directory. Let's plumb it through. A panel will be able to
put things in a "panel" directory under the connector's
directory. Note that debugfs is not ABI and so it's always possible
that the location that the panel gets for its debugfs could change in
the future.
NOTE: this currently only works if you're using a modern
architecture. Specifically the plumbing relies on _both_
drm_bridge_connector and drm_panel_bridge. If you're not using one or
both of these things then things won't be plumbed through.
As a side effect of this change, drm_bridges can also get callbacks to
put stuff underneath the connector's debugfs directory. At the moment
all bridges in the chain have their debugfs_init() called with the
connector's root directory.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220204161245.v2.2.Ib0bd5346135cbb0b63006b69b61d4c8af6484740@changeid
The ti-sn65dsi86 driver shouldn't hand-roll its own bridge
connector. It should use the normal drm_bridge_connector. Let's switch
to do that, removing all of the custom code.
NOTE: this still _doesn't_ implement DRM_BRIDGE_ATTACH_NO_CONNECTOR
support for ti-sn65dsi86 and that would still be a useful thing to do
in the future. It was attempted in the past [1] but put on the back
burner. However, unless we instantly change ti-sn65dsi86 fully from
not supporting DRM_BRIDGE_ATTACH_NO_CONNECTOR at all to _only_
supporting DRM_BRIDGE_ATTACH_NO_CONNECTOR then we'll still need a bit
of time when we support both. This is a better way to support the old
way where the driver hand rolls things itself.
A new notes about the implementation here:
* When using the drm_bridge_connector the connector should be created
after all the bridges, so we change the ordering a bit.
* I'm reasonably certain that we don't need to do anything to "free"
the new drm_bridge_connector. If drm_bridge_connector_init() returns
success then we know drm_connector_init() was called with the
`drm_bridge_connector_funcs`. The `drm_bridge_connector_funcs` has a
.destroy() that does all the cleanup. drm_connector_init() calls
__drm_mode_object_add() with a drm_connector_free() that will call
the .destroy().
* I'm also reasonably certain that I don't need to "undo" the
drm_bridge_attach() if drm_bridge_connector_init() fails. The
"detach" function is private and other similar code doesn't try to
undo the drm_bridge_attach() in error cases. There's also a comment
indicating the lack of balance at the top of drm_bridge_attach().
[1] https://lore.kernel.org/r/20210920225801.227211-4-robdclark@gmail.com
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220204161245.v2.1.I3ab26b7f197cc56c874246a43e57913e9c2c1028@changeid
Add the spec version to the title line.
Explain likely source of "Unknown lines".
"Unknown lines" in nested tests are optionally indented.
Add "Unknown lines" items to differences between TAP & KTAP list
Convert "Major differences between TAP and KTAP" from a bullet list
to a table. The bullet list was being formatted as a single
paragraph.
Reviewed-by: Tim Bird <Tim.Bird@sony.com>
Reviewed-by: David Gow <davidgow@google.com>
Reviewed-by: Shuah Khan <skhan@linuxfoundation.org>
Signed-off-by: Frank Rowand <frank.rowand@sony.com>
Reviewed-by: Brendan Higgins <brendanhiggins@google.com>
Link: https://lore.kernel.org/r/20220210233630.3304495-1-frowand.list@gmail.com
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Add the program header definition and data layout for the
PT_ARM_MEMTAG_MTE segments.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Luis Machado <luis.machado@linaro.org>
Link: https://lore.kernel.org/r/20220131165456.2160675-6-catalin.marinas@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
For each vma mapped with PROT_MTE (the VM_MTE flag set), generate a
PT_ARM_MEMTAG_MTE segment in the core file and dump the corresponding
tags. The in-file size for such segments is 128 bytes per page.
For pages in a VM_MTE vma which are not present in the user page tables
or don't have the PG_mte_tagged flag set (e.g. execute-only), just write
zeros in the core file.
An example of program headers for two vmas, one 2-page, the other 4-page
long:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
...
LOAD 0x030000 0x0000ffff80034000 0x0000000000000000 0x000000 0x002000 RW 0x1000
LOAD 0x030000 0x0000ffff80036000 0x0000000000000000 0x004000 0x004000 RW 0x1000
...
LOPROC+0x1 0x05b000 0x0000ffff80034000 0x0000000000000000 0x000100 0x002000 0
LOPROC+0x1 0x05b100 0x0000ffff80036000 0x0000000000000000 0x000200 0x004000 0
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Luis Machado <luis.machado@linaro.org>
Reviewed-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220131165456.2160675-5-catalin.marinas@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Rather than explicitly calculating the number of bytes for a compact tag
storage format corresponding to a page, just add a MTE_PAGE_TAG_STORAGE
macro. With the current MTE implementation of 4 bits per tag, we store
2 tags in a byte.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Luis Machado <luis.machado@linaro.org>
Link: https://lore.kernel.org/r/20220131165456.2160675-4-catalin.marinas@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Memory tags will be dumped in the core file as segments with their own
type. Discussions with the binutils and the generic ABI community
settled on using new definitions in the PT_*PROC space (and to be
documented in the processor-specific ABIs).
Introduce PT_ARM_MEMTAG_MTE as (PT_LOPROC + 0x1). Not included in this
patch since there is no upstream support but the CHERI/BSD community
will also reserve:
#define PT_ARM_MEMTAG_CHERI (PT_LOPROC + 0x2)
#define PT_RISCV_MEMTAG_CHERI (PT_LOPROC + 0x3)
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Luis Machado <luis.machado@linaro.org>
Link: https://lore.kernel.org/r/20220131165456.2160675-3-catalin.marinas@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
As arm64 is about to introduce MTE-specific phdrs in the core dump, add
a common CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS option currently selectable
by UML_X86 and IA64.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Eric Biederman <ebiederm@xmission.com>
Link: https://lore.kernel.org/r/20220131165456.2160675-2-catalin.marinas@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
