Support for requesting the next power_off operation for a genpd to be
synchronous is introduced, and implemented in the GDSC driver. To allow
the GPU driver to request power_off to wait for the GDSC to actually
collapse.
Support for QDU1000/QRU1000 Global clock controller, SA8775P Global
clock controller, SM8550 TCSR and display clock controller, SM6350 clock
controller, nd MSM8996 CBF and APCS clock controllers is introduced..
Parent references are updated across a large number of clock drivers, to
align with the design changes since those drivers where introduced.
Similarly, test clocks has been dropped from a range of drivers.
A range of fixes for the MSM8996 CPU clock controller is introduced.
MSM8974 GCC is transitioned off the externally defined sleep_clk.
GDSC in the global clock controller for QCS404 is added, and various
parent definitions are cleaned up.
The SDCC core clocks on SM6115 are moved for floor_ops.
Programming of clk_dis_wait for GPU CX GDSC on SC7180 and SDM845 are
moved to use the recently introduced properties in the GDSC struct.
The RPMh clock driver gains SM8550 and SA8775P clocks, and the IPA clock
is added on a variety of platforms.
The SMD RPM driver receives a big cleanup, in particular a move away
from duplicating declaration of identical clocks between multiple
platforms.
A few missing clocks across msm8998, msm8992, msm8916, qcs404 are added
as well.
Using devm_pm_runtime_enable() to clean up some duplication is done
across SM8250 display and video clock controllers, SM8450 display clock
controller and SC7280 LPASS clock controller.
Devicetree binding changes for above mentioned additions and changes are
introduced.
Support for postponing clk_disable_unused() until sync_state was
introduced, but later reverted again, awaiting an agreement on the
solution.
Lastly, a change to pad a few registers in the SM8250 DTS to 8 digits
was picked up in the wrong tree and kept here, to avoid rebasing.
-----BEGIN PGP SIGNATURE-----
iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmP2NUoVHGFuZGVyc3Nv
bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FKx8P/3MbazA6/X63Q6YjaOWIFlB7ekRl
UVumgbvFB6Ul0hErLluGBlAckjf5gyEb/SQDeQ6yMG6EO6UFTA74ZT4mqDh3jr6P
VAVjxW6BGgiPLBSLAFGhq1YQwmbCiiOKWleApZpgWH8gQU3NbdUV1c3WueGRGSWK
HXmNgE5Up4NqBPcupKadDQO4L/32hrnH3gy21MY7f0okFuCWENdUjVkYLupWOdc+
yWHJot0esSMZUy6I8p/PHAsuOLfvELzgS2WFAv/Kv38G6Dx81MvVh6wdlWu2WT+Q
y8Ooje6C9YzV8MS3YgwI59ajX5+5pmYGvPz8QhyhTGGX3KzPrgZus31d5/zDqHe6
gVTXM75luDxjq80QIb0onm1FGC2qK3B1590x+x6XB4Cpe1k98qvEAGgUTrrjCznc
dSzo+nsQVANzwSUQiW3mpR79QttHFAh/OeS2xk4phg8kGrNZOZOJEiybXwJhAPzH
dFvFRLEQkxIvwKl27ewv1b3grJuHDg7SP4cPAVFz8cGHoOe7EIYAMT066UkHT4+G
5QobmKYkDBCJFIPZpjRjvXU7JXXsuYLWfV7qSq6AI4fyGx1UrR6D+vzERvk/bupy
PLrOJVbwmR7P8WW5H8qwh+5daUHKshxMjvuVKTVRTZizbodXEM3d0/mTeK9ZXuN4
qJ+cHoeV9A4c0rnG
=uOcH
-----END PGP SIGNATURE-----
Merge tag 'qcom-clk-for-6.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom
Pull Qualcomm clk driver updates from Bjorn Andersson:
Support for requesting the next power_off operation for a genpd to be
synchronous is introduced, and implemented in the GDSC driver. To allow
the GPU driver to request power_off to wait for the GDSC to actually
collapse.
Support for QDU1000/QRU1000 Global clock controller, SA8775P Global
clock controller, SM8550 TCSR and display clock controller, SM6350 clock
controller, nd MSM8996 CBF and APCS clock controllers is introduced.
Parent references are updated across a large number of clock drivers, to
align with the design changes since those drivers where introduced.
Similarly, test clocks has been dropped from a range of drivers.
A range of fixes for the MSM8996 CPU clock controller is introduced.
MSM8974 GCC is transitioned off the externally defined sleep_clk.
GDSC in the global clock controller for QCS404 is added, and various
parent definitions are cleaned up.
The SDCC core clocks on SM6115 are moved for floor_ops.
Programming of clk_dis_wait for GPU CX GDSC on SC7180 and SDM845 are
moved to use the recently introduced properties in the GDSC struct.
The RPMh clock driver gains SM8550 and SA8775P clocks, and the IPA clock
is added on a variety of platforms.
The SMD RPM driver receives a big cleanup, in particular a move away
from duplicating declaration of identical clocks between multiple
platforms.
A few missing clocks across msm8998, msm8992, msm8916, qcs404 are added
as well.
Using devm_pm_runtime_enable() to clean up some duplication is done
across SM8250 display and video clock controllers, SM8450 display clock
controller and SC7280 LPASS clock controller.
Devicetree binding changes for above mentioned additions and changes are
introduced.
Support for postponing clk_disable_unused() until sync_state was
introduced, but later reverted again, awaiting an agreement on the
solution.
Lastly, a change to pad a few registers in the SM8250 DTS to 8 digits
was picked up in the wrong tree and kept here, to avoid rebasing.
* tag 'qcom-clk-for-6.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (142 commits)
clk: qcom: Revert sync_state based clk_disable_unused
dt-bindings: clock: Merge qcom,gpucc-sm8350 into qcom,gpucc.yaml
clk: qcom: gpucc-sdm845: fix clk_dis_wait being programmed for CX GDSC
clk: qcom: gpucc-sc7180: fix clk_dis_wait being programmed for CX GDSC
dt-bindings: clock: qcom,sa8775p-gcc: add the power-domains property
clk: qcom: cpu-8996: add missing cputype include
clk: qcom: gcc-sa8775p: remove unused variables
clk: qcom: smd-rpm: provide RPM_SMD_XO_CLK_SRC on MSM8996 platform
clk: qcom: add msm8996 Core Bus Framework (CBF) support
dt-bindings: clock: qcom,msm8996-cbf: Describe the MSM8996 CBF clock controller
clk: qcom: add the driver for the MSM8996 APCS clocks
clk: qcom: gcc-qcs404: fix duplicate initializer warning
clk: qcom: cpu-8996: change setup sequence to follow vendor kernel
clk: qcom: cpu-8996: fix PLL clock ops
clk: qcom: cpu-8996: fix ACD initialization
clk: qcom: cpu-8996: fix PLL configuration sequence
clk: qcom: cpu-8996: move qcom_cpu_clk_msm8996_acd_init call
clk: qcom: cpu-8996: setup PLLs before registering clocks
clk: qcom: cpu-8996: simplify the cpu_clk_notifier_cb
clk: qcom: cpu-8996: skip ACD init if the setup is valid
...
Revert the postponement of clk_disable_unused() for clock providers that
implement sync_state, and the change to drivers implementing this, until
agreement on the implementation has been reached.
This reverts:
29e31415e1 ("clk: qcom: Remove need for clk_ignore_unused on sc8280xp")
99c0f7d35c ("clk: qcom: sdm845: Use generic clk_sync_state_disable_unused callback")
26b36df751 ("clk: Add generic sync_state callback for disabling unused clocks")
Requested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The GPU clock controller bindings for the Qualcomm sm8350 platform are
not correct. The driver uses .fw_name instead of using indices to bind
parent clocks, thus demanding the clock-names usage. With the proper
clock-names in place, the bindings becomes equal to the bindings defined
by qcom,gpucc.yaml, so it is impractical to keep them in a separate
file.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230206145707.122937-2-dmitry.baryshkov@linaro.org
The gdsc_init() function will rewrite the CLK_DIS_WAIT field while
registering the GDSC (writing the value 0x2 by default). This will
override the setting done in the driver's probe function.
Set cx_gdsc.clk_dis_wait_val to 8 to follow the intention of the probe
function.
Fixes: 453361cdd7 ("clk: qcom: Add graphics clock controller driver for SDM845")
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230201172305.993146-2-dmitry.baryshkov@linaro.org
The gdsc_init() function will rewrite the CLK_DIS_WAIT field while
registering the GDSC (writing the value 0x2 by default). This will
override the setting done in the driver's probe function.
Set cx_gdsc.clk_dis_wait_val to 8 to follow the intention of the probe
function.
Fixes: 745ff069a4 ("clk: qcom: Add graphics clock controller driver for SC7180")
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230201172305.993146-1-dmitry.baryshkov@linaro.org
Include asm/cputype.h to fix ARMv7 compile test error:
drivers/clk/qcom/clk-cpu-8996.c: In function ‘qcom_cpu_clk_msm8996_acd_init’:
drivers/clk/qcom/clk-cpu-8996.c:468:16: error: implicit declaration of function ‘read_cpuid_mpidr’ [-Werror=implicit-function-declaration]
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[bjorn: Moved asm-include after linux/, per Stephen's request]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230123201812.1230039-1-krzysztof.kozlowski@linaro.org
There are four struct definitions in the driver that aren't used so
remove them.
Reported-by: kernel test robot <lkp@intel.com>
Fixes: ed432b1ed00a ("clk: qcom: add the GCC driver for sa8775p")
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230123103338.230320-1-brgl@bgdev.pl
Extend the list of RPM clocks provided on MSM8996 platform to also
include RPM_SMD_XO_CLK_SRC and RPM_SMD_XO_A_CLK_SRC.
Fixes: 7066fdd0d7 ("clk: qcom: clk-smd-rpm: add msm8996 rpmclks")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230120061417.2623751-6-dmitry.baryshkov@linaro.org
Add CBF clock driver as a part of MSM8996 CPU clocks. Significantly
based on AngeloGioacchino del Regno's work at [1].
The CBF is an interconnect between two CPU clusters, setting it up
properly is required for booting the MSM8996 with all four cores
enabled.
[1] https://github.com/sonyxperiadev/kernel/blob/aosp/LE.UM.2.3.2.r1.4/drivers/clk/qcom/clk-cpu-8996.c
Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
[bjorn: Dropped partially uninitialized variable "ret" from cbf_clk_notifier_cb()]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230120061417.2623751-4-dmitry.baryshkov@linaro.org
MSM8996 Core Bus Fabric (CBF) clock controller clocks an interconnect
between two CPU clusters. The CBF clock should follow the CPU
frequencies to provide enough bandwidth between clusters. Thus a single
driver implements both a clock and an interconnect to set the clock
rate.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230120061417.2623751-2-dmitry.baryshkov@linaro.org
Add a simple driver handling the APCS clocks on MSM8996. For now it
supports just a single aux clock, linking GPLL0 to CPU and CBF clocks.
Note, there is little sense in registering sys_apcs_aux as a child of
gpll0. The PLL is always-on. And listing the gpll0 as a property of the
apcs would delay its probing until the GCC has been probed (while we
would like for the apcs to be probed as early as possible).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[bjorn: Fixed spelling of register, per Stephen's feedback]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230126230319.3977109-8-dmitry.baryshkov@linaro.org
In one of the clocks, a redundant initialization for .num_parents
got left behind by a recent patch:
drivers/clk/qcom/gcc-qcs404.c:63:32: error: initialized field overwritten [-Werror=override-init]
63 | .num_parents = 1,
| ^
Fixes: 2ce81afa0c ("clk: qcom: gcc-qcs404: sort out the cxo clock")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230130135555.3268172-1-arnd@kernel.org
Add missing register writes to CPU clocks setup procedure. This makes it
follow the setup procedure used in msm-3.18 kernel.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113120544.59320-14-dmitry.baryshkov@linaro.org
Switch CPU PLLs to use clk_alpha_pll_hwfsm_ops, it seems to suit
better.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113120544.59320-13-dmitry.baryshkov@linaro.org
The vendor kernel applies different order while programming SSSCTL and
L2ACDCR registers on power and performance clusters. However it was
demonstrated that doing this upstream results in the board reset. Make
both clusters use the same sequence, which fixes the reset.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113120544.59320-12-dmitry.baryshkov@linaro.org
Switch both power and performance clocks to the GPLL0/2 (sys_apcs_aux)
before PLL configuration. Switch them to the ACD afterwards.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113120544.59320-11-dmitry.baryshkov@linaro.org
Initialize ACD configuration from qcom_cpu_clk_msm8996_register_clks(),
before registering all clocks. This way we can be sure that the clock is
fully configured before letting CCF touch it.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113120544.59320-10-dmitry.baryshkov@linaro.org
Setup all PLLs before registering clocks in the common clock framework.
This ensures that the clocks are not accessed before being setup in the
known way and that the CCF is in sync with the actual HW programming.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113120544.59320-9-dmitry.baryshkov@linaro.org
- Do not use the Alt PLL completely. Switch to smux when necessary to
prevent overvolting
- Restore the parent in case the rate change aborts for some reason
- Do not duplicate resetting the parent in set_parent operation.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113120544.59320-8-dmitry.baryshkov@linaro.org
Check whether L2 registers contain correct values and skip programming
if they are valid. This follows the code present downstream.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113120544.59320-7-dmitry.baryshkov@linaro.org
In some cases the driver might need using GPLL0 to drive CPU clocks.
Bring it in through the sys_apcs_aux clock.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113120544.59320-6-dmitry.baryshkov@linaro.org
Current multiplier (60) results in CPU getting the rate which is
unlisted in the CPU frequency tables (60 * 19.2 = 1152 MHz). This
results in warnings from the cpufreq during startup.
Change PLL programming (l = 54) to init CPU clocks to start with the
frequency of 54 * 19.2 = 1036.8 MHz which is supported by both power and
performance clusters from all speed bins.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113120544.59320-5-dmitry.baryshkov@linaro.org
Program PLL_TEST and PLL_TEST_U registers if required by the pll
configuration.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113120544.59320-3-dmitry.baryshkov@linaro.org
The MSM8996 CPU clock controller can make use of the sys_apcs_aux clock.
Add it to the bindings.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230113120544.59320-2-dmitry.baryshkov@linaro.org
Add Global Clock Controller (GCC) support for QDU1000 and QRU1000 SoCs.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
[bjorn: Made gcc_pcie_0_pipe_clk_src use clk_regmap_phy_mux_ops]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230112204446.30236-3-quic_molvera@quicinc.com
Add device tree bindings for global clock controller on QDU1000 and
QRU1000 SoCs.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230112204446.30236-2-quic_molvera@quicinc.com
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.
Note, the system names for xo clocks were changed from "xo" to
"xo_board" to follow the example of other platforms. This switches the
clocks to use DT-provided "xo_board" clock instead of manually
registered "xo" clock and allows us to drop qcom_cc_register_board_clk()
call from the driver at some point.
In the same way change the looked up system "sleep_clk_src" clock to
"sleep_clk", which is registered from DT.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230111060402.1168726-12-dmitry.baryshkov@linaro.org
SPDM is used for debug/profiling and does not have any other
functionality. These clocks can safely be removed.
Suggested-by: Stephen Boyd <sboyd@kernel.org>
Suggested-by: Georgi Djakov <djakov@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230111060402.1168726-11-dmitry.baryshkov@linaro.org
Move clock parent tables down, after the PLL declrataions, so that we
can use pll hw clock fields in the next commit.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230111060402.1168726-10-dmitry.baryshkov@linaro.org
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230111060402.1168726-9-dmitry.baryshkov@linaro.org
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.
Note, the system names for xo clocks were changed from "xo" to
"xo_board" to follow the example of other platforms. This switches the
clocks to use DT-provided "xo_board" clock instead of manually
registered "xo" clock and allows us to drop qcom_cc_register_board_clk()
call from the driver at some point.
In the same way change the looked up system "sleep_clk_src" clock to
"sleep_clk", which is registered from DT.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230111060402.1168726-7-dmitry.baryshkov@linaro.org
Move PLL clock declarations up, before clock parent tables, so that we
can use pll hw clock fields in the next commit.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230111060402.1168726-6-dmitry.baryshkov@linaro.org
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230111060402.1168726-5-dmitry.baryshkov@linaro.org
Define clock/clock-names properties of the MMCC device node to be used
on APQ8084 platform.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230111060402.1168726-4-dmitry.baryshkov@linaro.org
Define clock/clock-names properties of the GCC device node to be used
on APQ8084 platform.
Note: the driver uses a single pcie_pipe clock, however most probably
there are two pipe clocks, one from each of PCIe QMP PHYs.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230111060402.1168726-2-dmitry.baryshkov@linaro.org
Having only .name populated in parent_data for clocks which are only
globally searchable currently will not work as the clk core won't copy
that name if there is no .fw_name present as well.
So, populate .fw_name for usb3phy clocks in parent_data as they were
missed by me in ("clk: qcom: ipq8074: populate fw_name for all parents").
Fixes: ae55ad32e2 ("clk: qcom: ipq8074: convert to parent data")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230108130440.670181-1-robimarko@gmail.com
Add support for the Global Clock Controller found in the QTI SA8775P
platforms.
Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
[Bartosz: made the driver ready for upstream]
Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[bjorn: Moved to core_initcall(), per request of Konrad]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230117180429.305266-3-brgl@bgdev.pl
The XO crystal input is buffered through the PMIC and controlled by RPM.
Create the relevant clock gate representation in the RPM clock definitions.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230117024846.1367794-5-bryan.odonoghue@linaro.org
Add clocks and properties (power-domains, required-opps) already used in
SM8250 DTS:
sm8250-hdk.dtb: clock-controller@ad00000: clocks: [[46, 10], [44, 0], [44, 1], [45]] is too long
sm8250-hdk.dtb: clock-controller@ad00000: clock-names:0: 'bi_tcxo' was expected
sm8250-hdk.dtb: clock-controller@ad00000: 'power-domains', 'required-opps' do not match any of the regexes: 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221224214404.18280-1-krzysztof.kozlowski@linaro.org
Different SoCs come with a bit different clock inputs:
sm8250-mtp.dtb: clock-controller@abf0000: clock-names:0: 'bi_tcxo' was expected
sm8250-mtp.dtb: clock-controller@abf0000: clock-names: ['iface', 'bi_tcxo', 'bi_tcxo_ao'] is too long
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221224154152.43272-1-krzysztof.kozlowski@linaro.org
