The bus-width property was moved to k3-am64-main.dtsi.
See commit 0ae3113a46 ("arm64: dts: ti: k3-am6*: Fix bus-width property
in MMC nodes")
Signed-off-by: John Ma <jma@phytec.com>
Link: https://lore.kernel.org/r/20240926184918.3342719-2-jma@phytec.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The bus-width property was moved to k3-am64-main.dtsi.
See commit 0ae3113a46 ("arm64: dts: ti: k3-am6*: Fix bus-width property
in MMC nodes")
Signed-off-by: John Ma <jma@phytec.com>
Link: https://lore.kernel.org/r/20240926184918.3342719-1-jma@phytec.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add overlay to enable the PCIe0 instance of PCIe on AM642-EVM in
Endpoint mode of operation.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20240930103413.3085689-1-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add overlay to enable the PCIE1 instance of PCIe on J7200-EVM in
Endpoint mode of operation.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20241001093426.3401765-1-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The power switch used to power the SD card interface might have
more than 2ms turn-on time, increase the startup delay to 20ms to
prevent failures.
Fixes: 316b80246b ("arm64: dts: ti: add verdin am62")
Cc: stable@vger.kernel.org
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Link: https://lore.kernel.org/r/20241024130628.49650-1-francesco@dolcini.it
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Fix Verdin AM62 on-SOM ADC compatible. Currently the hardware is not
correctly described in the DT, use the correct TI TLA2024 compatible that
matches what is assembled on the board.
The "ti,tla2024" compatible was introduced in Linux v5.19 and Verdin AM62
support was introduced in Linux v6.5.
The new DTB will not work on kernel older than v5.19, but this seems
unlikely to happen. U-Boot does not use the ADC node and a known Android 14
out-of-tree port uses a Linux Kernel 6.1.
With that said, despite this being a breaking change, it seems fair to
to not expect any regression because of it.
Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com>
Link: https://lore.kernel.org/r/20241015113334.246110-1-jpaulo.silvagoncalves@gmail.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The clock IDs for multiple MCSPI instances across wakeup as
well as main domain in J7200 are incorrect when compared with
documentation [1]. This results in kernel crashes when the said
instances are enabled. Fix the clock ids to their appropriate
values.
[1]https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j7200/clocks.html
Fixes: 8f6c475f4c ("arm64: dts: ti: k3-j7200: Add MCSPI nodes")
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Reviewed-by: Aniket Limaye <a-limaye@ti.com>
Link: https://lore.kernel.org/r/20241023104532.3438851-2-a-dutta@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Commit 0d0a0b4413 ("arm64: dts: ti: k3-j7200: fix main pinmux
range") split the main_pmx0 into two nodes: main_pmx0 and main_pmx1
due to a non-addressable region, but incorrectly represented the
ranges. As a result, the memory map for the pinctrl is incorrect. Fix
this by introducing the correct ranges.
The ranges are taken from the J7200 TRM [1] (Table 5-695. CTRL_MMR0
Registers).
Padconfig starting addresses and ranges:
- 0 to 66: 0x11c000, 0x10c
- 68: 0x11c110, 0x004
- 71 to 73: 0x11c11c, 0x00c
- 89 to 90: 0x11c164, 0x008
The datasheet [2] doesn't contain PADCONFIG63 (Table 6-106. Pin
Multiplexing), but the pin is necessary for enabling the MMC1 CLKLP
pad loopback and should be included in the pinmux register map.
Due to the change in pinmux node addresses, change the pinmux node for
the USB0_DRVVBUS pin to main_pmx2. The offset has not changed since the
new main_pmx2 node has the same base address and range as the original
main_pmx1 node. All other pinmuxing done within J7200 dts or dtso files
only uses main_pmx0 which has not changed.
[1] https://www.ti.com/lit/pdf/spruiu1
[2] https://www.ti.com/lit/gpn/dra821u
Fixes: 0d0a0b4413 ("arm64: dts: ti: k3-j7200: fix main pinmux range")
Signed-off-by: Aniket Limaye <a-limaye@ti.com>
Signed-off-by: Jared McArthur <j-mcarthur@ti.com>
Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20240926102533.398139-1-a-limaye@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Adds bootph-* properties to the leaf nodes to enable bootloaders to
utilise them.
Following adds bootph-* to:
- pmic regulator for enabling AVS Support
- main_uart0, mcu_uart0(DM), wkup_uart0(TIFS) for Traces
- mmc0, mmc1, usb0, ospi0, hbmc for enabling various bootmodes.
Reviewed-by: Aniket Limaye <a-limaye@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-12-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Adds bootph-* properties to the leaf nodes to enable bootloaders to
utilise them.
Following adds bootph-* to:
- main_uart0, mcu_uart0(DM), wkup_uart0(TIFS) for Traces
- mmc1, usb0, usb1, ospi0 for enabling various bootmodes.
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-11-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Adds bootph-* properties to the leaf nodes to enable bootloaders to
utilise them.
Following adds bootph-* to:
- main_uart0, mcu_uart0(DM), wkup_uart0(TIFS) for Traces
- mmc0, mmc1, usb0, ospi0, ospi1, hbmc for enabling various bootmodes.
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-10-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Adds bootph-* properties to the leaf nodes to enable bootloaders to
utilise them.
Following adds bootph-* to:
- main_uart8, mcu_uart0(DM), wkup_uart0(TIFS) for Traces
- mmc1, ospi0 for enabling various bootmodes.
- eeprom for board detection
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-9-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Adds bootph-* properties to the leaf nodes to enable bootloaders to
utilise them.
Following adds bootph-* to:
- pmic regulator for enabling AVS Support
- main_uart8, mcu_uart0(DM), wkup_uart0(TIFS) for Traces
- mmc0, mmc1, usb0, ospi0, ospi1 for enabling various bootmodes.
Reviewed-by: Andrew Davis <afd@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-8-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Adding bootph properties on leaf nodes imply that they are applicable to
the parent nodes as well. Bootloaders can derive the parent nodes when
bootph is available in the leaf nodes.
Remove the bootph-* properties from parent nodes as they are redundant.
Reviewed-by: Aniket Limaye <a-limaye@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-7-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Adds bootph-* properties to the leaf nodes to enable bootloaders to
utilise them.
Following adds bootph-* to
- System controller nodes that allow controlling power domain, clocks, etc.
- secure_proxy_sa3/secure_proxy_main mboxes for communication with
System Controller
- mcu_ringacc/mcu_udmap for DMA to SMS
- chipid for detection soc information.
- mcu_timer0 for bootloader tick-timer.
- hbmc_mux for enabling Hyperflash support
- ESM nodes for enabling ESM support.
- wkup_vtm for enabling Adaptive voltage scaling(AVS) support
Reviewed-by: Aniket Limaye <a-limaye@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-6-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Adds bootph-* properties to the leaf nodes to enable bootloaders to
utilise them.
Following adds bootph-* to
- System controller nodes that allow controlling power domain, clocks, etc.
- secure_proxy_sa3/secure_proxy_main mboxes for communication with
System Controller
- mcu_ringacc/mcu_udmap for DMA to SMS
- chipid for detection soc information.
- mcu_timer0 for bootloader tick-timer.
- hbmc_mux for enabling Hyperflash support
- ESM nodes for enabling ESM support.
- wkup_vtm for enabling Adaptive voltage scaling(AVS) support
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-5-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Adds bootph-* properties to the leaf nodes to enable bootloaders to
utilise them.
Following adds bootph-* to
- System controller nodes that allow controlling power domain, clocks, etc.
- secure_proxy_sa3/secure_proxy_main mboxes for communication with
System Controller
- mcu_ringacc/mcu_udmap for DMA to SMS
- chipid for detection soc information.
- mcu_timer0 for bootloader tick-timer.
- wkup_vtm for enabling Adaptive voltage scaling(AVS) support
Reviewed-by: Andrew Davis <afd@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-4-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The following nodes are being used in the bootloaders. Adds bootph-*
properties to the leaf nodes to enable bootloaders to utilise them.
Following adds bootph-* to
- secure_proxy_sa3/secure_proxy_main mboxes for communication with
System Controller
- wkup_vtm for enabling Adaptive voltage scaling(AVS) support
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-3-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Adding bootph properties on leaf nodes imply that they are applicable to
the parent nodes as well. Bootloaders can derive the parent nodes when
bootph is available in the leaf nodes.
Remove the bootph-* properties from parent nodes as they are redundant.
Reviewed-by: Aniket Limaye <a-limaye@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20241024-b4-upstream-bootph-all-v6-2-2af90e3a4fe7@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add ti,pa-stats phandles to k3-am64x-evm.dts. This is a phandle to
PA_STATS syscon regmap and will be used to dump IET related statistics
for ICSSG Driver
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20241014074527.1121613-5-danishanwar@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add pa-stats nodes to k3-am64-main.dtsi for all ICSSG instances.
This is needed to dump IET related statistics for ICSSG Driver.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20241014074527.1121613-4-danishanwar@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add ti,pa-stats phandles to AM65x device trees. This is a phandle to
PA_STATS syscon regmap and will be used to dump IET related statistics
for ICSSG Driver
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Link: https://lore.kernel.org/r/20241014074527.1121613-3-danishanwar@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Add pa-stats nodes to k3-am65-main.dtsi for all ICSSG instances.
This is needed to dump IET related statistics for ICSSG Driver.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20241014074527.1121613-2-danishanwar@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Update the RGMII delay to 2.5ns to improve performance. We use an
additional mapper board for the am62a7 phyBOARD Lyra which makes this
delay necessary.
Signed-off-by: Nathan Morrisson <nmorrisson@phytec.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20241004221049.1155022-1-nmorrisson@phytec.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Drop the McASP AFIFOs for better audio latency. This adds back a
change that was lost while refactoring the device tree.
Fixes: 554dd562a5 ("arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Drop McASP AFIFOs")
Signed-off-by: Nathan Morrisson <nmorrisson@phytec.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20241002224754.2917895-1-nmorrisson@phytec.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
There are 3 instances of eQEP on AM64x. Only EQEP0 signals
can be routed to the user expansion so enable only EQEP0
in k3-am642-sk.dts.
Signed-off-by: Judith Mendez <jm@ti.com>
Link: https://lore.kernel.org/r/20240924220700.886313-6-jm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The AM64x SoCs of the TI K3 family have a Cortex M4F core in the MCU
domain. This core can be used by non safety applications as a remote
processor. When used as a remote processor with virtio/rpmessage IPC,
two carveout reserved memory nodes are needed. The first region is used
as a DMA pool for the rproc device, and the second region will furnish
the static carveout regions for the firmware memory.
The current carveout addresses and sizes are defined statically for
each rproc device. The M4F processor does not have an MMU, and as such
requires the exact memory used by the firmware to be set-aside.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Andrew Davis <afd@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20241003170118.24932-6-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The AM64x SoCs of the TI K3 family have a Cortex M4F core in the MCU
domain. This core can be used by non safety applications as a remote
processor. When used as a remote processor with virtio/rpmessage IPC,
two carveout reserved memory nodes are needed. The first region is used
as a DMA pool for the rproc device, and the second region will furnish
the static carveout regions for the firmware memory.
The current carveout addresses and sizes are defined statically for
each rproc device. The M4F processor does not have an MMU, and as such
requires the exact memory used by the firmware to be set-aside.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Andrew Davis <afd@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20241003170118.24932-5-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The AM64x SoCs of the TI K3 family have a Cortex M4F core in the MCU
domain. This core can be used by non safety applications as a remote
processor. When used as a remote processor with virtio/rpmessage IPC,
two carveout reserved memory nodes are needed.
Disable by default as this node is not complete until mailbox data
is provided in the board level DT.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Andrew Davis <afd@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20241003170118.24932-4-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The AM62x SoCs of the TI K3 family have a Cortex M4F core in the MCU
domain. This core can be used by non safety applications as a remote
processor. When used as a remote processor with virtio/rpmessage IPC,
two carveout reserved memory nodes are needed. The first region is used
as a DMA pool for the rproc device, and the second region will furnish
the static carveout regions for the firmware memory.
The current carveout addresses and sizes are defined statically for
each rproc device. The M4F processor does not have an MMU, and as such
requires the exact memory used by the firmware to be set-aside.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Andrew Davis <afd@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20241003170118.24932-3-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The AM62x SoCs of the TI K3 family have a Cortex M4F core in the MCU
domain. This core can be used by non safety applications as a remote
processor. When used as a remote processor with virtio/rpmessage IPC,
two carveout reserved memory nodes are needed.
Disable by default as this node is not complete until mailbox data
is provided in the board level DT.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Andrew Davis <afd@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20241003170118.24932-2-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
We now configure the a53_opp_table to include a 1.4 GHz node and set our
VDD_CORE to 0.85v in the k3-am62-phycore-som.dtsi. This change is to
match our PMIC which is now set to output 0.85v by default.
This reverts commit 7a5775a3da.
Signed-off-by: Garrett Giordano <ggiordano@phytec.com>
Link: https://lore.kernel.org/r/20241001071916.1362213-3-ggiordano@phytec.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
The am625 is capable of running at 1.4 GHz when VDD_CORE is increased
from 0.75V to 0.85V. Here we add a 1.4 GHz node to the a53_opp_table and
increase the VDD_CORE voltage accordingly.
Signed-off-by: Garrett Giordano <ggiordano@phytec.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20241001071916.1362213-2-ggiordano@phytec.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This device is a subset of J784S4 and shares the same memory map and
thus the nodes are being reused from J784S4 to avoid duplication.
Here are some of the salient features of the J742S2 automotive grade
application processor:
The J742S2 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration in automotive, ADAS and industrial
applications requiring AI at the network edge. This SoC extends the K3
Jacinto 7 family of SoCs with focus on raising performance and
integration while providing interfaces, memory architecture and compute
performance for multi-sensor, high concurrency applications.
Some changes that this devices has from J784S4 are:
* 4x Cortex-A72 vs 8x Cortex-A72
* 3x C7x DSP vs 4x C7x DSP
* 4 port ethernet switch vs 8 port ethernet switch
( Refer Table 2-1 for Device comparison with J7AHP )
Link: https://www.ti.com/lit/pdf/spruje3 (TRM)
Reviewed-by: Beleswar Padhi <b-padhi@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Link: https://lore.kernel.org/r/20240902-b4-upstream-j742s2-v6-4-6a7aa2736797@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Refactor J784s4-evm to a common file which uses the
superset device to allow reuse in j742s2-evm which uses the subset part.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Beleswar Padhi <b-padhi@ti.com>
Link: https://lore.kernel.org/r/20240902-b4-upstream-j742s2-v6-2-6a7aa2736797@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Refactor J784s4 SoC files to a common file which uses the
superset device to allow reuse in j742s2-evm which uses the subset part.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Beleswar Padhi <b-padhi@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20240902-b4-upstream-j742s2-v6-1-6a7aa2736797@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
