Add support for 1-2-2 read ops by separately calculating the switch from
single-bit to multi-bit, and then switching within the prepend data.
This allows us to support single-bit write followed by multi-bit write
followed by multi-bit read, and we do not need to reject 1-2-2 read
operations anymore.
Tested on BCM963268BU_P300 with custom fixup to allow 1-2-2 on the
non-SDFP capable s25fl129p1 attached (which it actually supports):
root@OpenWrt:~# cat /sys/kernel/debug/spi-nor/spi1.0/params
name s25fl129p1
id 01 20 18 4d 01 01
size 16.0 MiB
write size 1
page size 256
address nbytes 3
flags HAS_16BIT_SR | NO_READ_CR
opcodes
read 0xbb
dummy cycles 4
erase 0xd8
program 0x02
8D extension none
protocols
read 1S-2S-2S
write 1S-1S-1S
register 1S-1S-1S
Reading from flash is still working as expected:
[ 1.070000] parser_imagetag: rootfs: CFE image tag found at 0x0 with version 6, board type 963168VX
[ 1.080000] parser_imagetag: Partition 0 is rootfs offset 100 and length 665000
[ 1.090000] parser_imagetag: Partition 1 is kernel offset 665100 and length 136fa1
[ 1.100000] parser_imagetag: Spare partition is offset 7b0000 and length 30000
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Acked-by: William Zhang <william.zhang@broadcom.com>
Tested-by: David Regan <dregan@broadcom.com>
Link: https://patch.msgid.link/20251217211026.173946-1-jonas.gorski@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Merge series from Alain Volmat <alain.volmat@foss.st.com>:
The series fixes a stability issue when dealing with <8bpw
transfers, as well as enforce an error if the DMA information
provided within the DT are incorrect.
Performance enhancement is also provided by allowing a polling
mode which is triggered when the transfer is so short that
polling mode transfer would lead to faster transfer than
if it was done in a interrupt driven manner.
In case of interrupt based transfer, when the transfer is very
small, relying on interrupts leads to lower performances than if
the transfer were done using polling on the registers.
Add a module parameter "polling_limit_us" to indicate the threshold
in us from which a transfer would be done polling the registers rather
than relying on interrupts.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Link: https://patch.msgid.link/20251218-stm32-spi-enhancements-v2-3-3b69901ca9fe@foss.st.com
Signed-off-by: Mark Brown <broonie@kernel.org>
When SPI communication is suspended by hardware automatically, it could
happen that few bits of next frame are already clocked out due to
internal synchronization delay.
To achieve a safe suspension, we need to ensure that each word must be
at least 8 SPI clock cycles long. That's why, if bpw is less than 8
bits, we need to use midi to reach 8 SPI clock cycles at least.
This will ensure that each word achieve safe suspension and prevent
overrun condition.
Signed-off-by: Deepak Kumar <deepak.kumar01@st.com>
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Link: https://patch.msgid.link/20251218-stm32-spi-enhancements-v2-2-3b69901ca9fe@foss.st.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Correct handling of the dma_request_chan call in order to avoid
misleading warn message if no DMA is provided within the device-tree
and moreover fail if dma_request_chan has returned a valid error.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Link: https://patch.msgid.link/20251218-stm32-spi-enhancements-v2-1-3b69901ca9fe@foss.st.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Merge series from Haibo Chen <haibo.chen@nxp.com>:
XSPI is a flexible SPI host controller which supports up to
2 external devices (2 CS). It support Single/Dual/Quad/Octal
mode data transfer.
The difference between XSPI and Flexspi is XSPI support
multiple independent execution environments (EENVs) for HW
virtualization with some limitations. Each EENV has its own
interrupt and its own set of programming registers that exists
in a specific offset range in the XSPI memory map.
The main environment (EENV0) address space contains all of the
registers for controlling EENV0 plus all of the general XSPI
control and programming registers. The register mnemonics for
the user environments (EENV1 to EENV4) have "_SUB_n" appended
to the mnemonic for the corresponding main-environment register.
Current driver based on EENV0, which means system already give
EENV0 right to linux.
This driver use SPI memory interface of the SPI framework to issue
flash memory operations. Tested this driver with mtd_debug and
UBIFS on NXP i.MX943 EVK board which has one MT35XU512ABA spi nor
flash. NOw this driver has the following key features:
- Support up to OCT DDR mode
- Support AHB read
- Support IP read and IP write
- Support two CS
Remove unnecessary semicolons reported by Coccinelle/coccicheck and the
semantic patch at scripts/coccinelle/misc/semicolon.cocci.
Signed-off-by: Chen Ni <nichen@iscas.ac.cn>
Link: https://patch.msgid.link/20251217023721.1684244-1-nichen@iscas.ac.cn
Signed-off-by: Mark Brown <broonie@kernel.org>
Remove unnecessary semicolons reported by Coccinelle/coccicheck and the
semantic patch at scripts/coccinelle/misc/semicolon.cocci.
Signed-off-by: Chen Ni <nichen@iscas.ac.cn>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://patch.msgid.link/20251216043210.1521722-1-nichen@iscas.ac.cn
Signed-off-by: Mark Brown <broonie@kernel.org>
Document devicetree bindings for the Andes ATCSPI200 SPI controller.
Signed-off-by: CL Wang <cl634@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20251215132349.513843-2-cl634@andestech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Add driver support for NXP XSPI controller.
XSPI is a flexible SPI host controller which supports up to
2 external devices (2 CS). It support Single/Dual/Quad/Octal
mode data transfer.
The difference between XSPI and Flexspi:
1.the register layout is total different.
2.XSPI support multiple independent execution environments
(EENVs) for HW virtualization with some limitations. Each EENV
has its own interrupt and its own set of programming registers
that exists in a specific offset range in the XSPI memory map.
The main environment (EENV0) address space contains all of the
registers for controlling EENV0 plus all of the general XSPI
control and programming registers. The register mnemonics for
the user environments (EENV1 to EENV4) have "_SUB_n" appended
to the mnemonic for the corresponding main-environment register.
Current driver based on EENV0, which means system already give
EENV0 right to linux.
This driver use SPI memory interface of the SPI framework to
issue flash memory operations. Tested this driver with UBIFS
and mtd_debug on NXP i.MX943 EVK board which has one spi nor
MT35XU512ABA flash. Now this driver has the following key
features:
- Support up to OCT DDR mode
- Support AHB read
- Support IP read and IP write
- Support two CS
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Link: https://patch.msgid.link/20251216-xspi-v7-2-282525220979@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Document imx94 xspi that supports interface to serial flash
supporting following features:
- Single-bit SPI, Dual SPI, Quad SPI and Octal SPI.
- Single Data Rate or Double Data Rate modes.
- Direct memory mapping of all AHB memory accesses to the
chip system memory space.
- Multi-master AHB accesses with priority.
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Link: https://patch.msgid.link/20251216-xspi-v7-1-282525220979@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Merge series from Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>:
The DMA controller can be used to transfer data to and from the SPI
controller without involving the CPU for each word of a SPI transfer.
Add support for DMA mode, and do some other cleanups while touching the
same code.
Merge series from Carlos Song <carlos.song@nxp.com>:
ECSPI has a low throughput because of no dynamic burst support, it
transfers only one word per frame in DMA mode, causing SCLK stalls
between words due to BURST_LENGTH updates.
This patch set is to support ECSPI dynamic burst feature to help improve
the ECSPI DMA mode performance.
Performance test (spidev_test @10MHz, 4KB):
Before: tx/rx ~6651.9 kbps
After: tx/rx ~9922.2 kbps (~50% improvement)
For compatibility with slow SPI devices, add configurable word delay in
DMA mode. When word delay is set, dynamic burst is disabled and
BURST_LENGTH equals word length.
Also support target DMA mode with enabled dynamic burst.
---
Changes since v2:
* Patch1~4: no change
* Patch5: remove __counted_by from *dma_data, because spi_imx struct
is allocated with a fixed memory in probe, flexible array is not
suitable, so just remove it to avoid the build error. Also add
review-by tag
* Patch6: add review-by tag
Changes since v1:
* Patch1~3:
* Add review-by tag
* Patch4:
* Add review-by tag
* Improve patch commit log
* Patch5:
* Clean up tab instead of space for dma_tx_addr and dma_rx_addr
* Add __counted_by(dma_package_num) for dma_data_package *dma_data
* Move temp and bytes_per_word to if()
* Add comment for spi_imx_dma_rx_data_handle() and
spi_imx_dma_tx_data_handle()
* Use kzalloc instead of kmalloc(x, x | __GFP_ZERO)
* Use sizeof(*temp) instead of BYTES_PER_32BITS_WORD in suitable place
* Add comments and fix comments according to discussion
* Propagate the error value of dma_mapping_error()
* Use round_down() to replace DIV_ROUND_DOWN_ULL()
* Improve transfer->error |= SPI_TRANS_FAIL_NO_START judgment for
better readability
* Patch6:
* Improve patch commit log
* Add READ_ONCE for spi_imx->target_aborted
* Add comments for data length limit
* Move data length limit to spi_imx_can_dma()
Carlos Song (6):
spi: imx: group spi_imx_dma_configure() with spi_imx_dma_transfer()
spi: imx: introduce helper to clear DMA mode logic
spi: imx: avoid dmaengine_terminate_all() on TX prep failure
spi: imx: handle DMA submission errors with dma_submit_error()
spi: imx: support dynamic burst length for ECSPI DMA mode
spi: imx: enable DMA mode for target operation
drivers/spi/spi-imx.c | 625 +++++++++++++++++++++++++++++++++++-------
1 file changed, 519 insertions(+), 106 deletions(-)
--
2.34.1
Merge series from Patrice Chotard <patrice.chotard@foss.st.com>:
This serie applies the following updates on the spi-stm32-ospi and
spi-stm32-qspi dirvers :
_ Update FIFO accesses using u16 and u32 when possible instead of u8
only to optimize throughput.
_ Replace Transmit Complete and Transmit Error interrupt management by
usage of read_poll_timeout_atomic() to optimize throughtput.
_ Simplify Status Match interrupt check.
_ Set DMA burst configuration dynamically.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
Changes in v2:
- Fix compilation error in stm32_ospi_wait_cmd()
- Link to v1: https://lore.kernel.org/r/20251205-upstream_qspi_ospi_updates-v1-0-7e6c8b9f5141@foss.st.com
---
Patrice Chotard (8):
spi: stm32-ospi: Set DMA maxburst dynamically
spi: stm32-ospi: Optimize FIFO accesses using u16 or u32
spi: stm32-ospi: Remove CR_TCIE and CR_TEIE irq usage
spi: stm32-ospi: Simplify SMIE interrupt test
spi: stm32-qspi: Set DMA maxburst dynamically
spi: stm32-qspi: Optimize FIFO accesses using u16 or u32
spi: stm32-qspi: Remove CR_TCIE and CR_TEIE irq usage
spi: stm32-qspi: Simplify SMIE interrupt test
drivers/spi/spi-stm32-ospi.c | 107 +++++++++++++++++++++++++----------------
drivers/spi/spi-stm32-qspi.c | 111 +++++++++++++++++++++++++------------------
2 files changed, 132 insertions(+), 86 deletions(-)
---
base-commit: 7d0a66e4bb
change-id: 20251205-upstream_qspi_ospi_updates-4faf7a3b098c
Best regards,
--
Patrice Chotard <patrice.chotard@foss.st.com>
Current min() has supported comparison by normal integer promotion rules,
so explicit type casts or min_t() are not needed.
Signed-off-by: Carlos Song <carlos.song@nxp.com>
Reviewed-by: David Laight <david.laight.linux@gmail.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20251210105001.3891776-1-carlos.song@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Initializing automatic __free variables to NULL without need (e.g.
branches with different allocations), followed by actual allocation is
in contrary to explicit coding rules guiding cleanup.h:
"Given that the "__free(...) = NULL" pattern for variables defined at
the top of the function poses this potential interdependency problem the
recommendation is to always define and assign variables in one statement
and not group variable definitions at the top of the function when
__free() is used."
Code does not have a bug, but is less readable and uses discouraged
coding practice, so fix that by moving declaration to the place of
assignment.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20251208020830.5225-2-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Mark Brown <broonie@kernel.org>
The recent refactoring of where runtime PM is enabled done in commit
f1eb4e792b ("spi: spi-cadence-quadspi: Enable pm runtime earlier to
avoid imbalance") made the fact that when we do a pm_runtime_disable()
in the error paths of probe() we can trigger a runtime disable which in
turn results in duplicate clock disables. This is particularly likely
to happen when there is missing or broken DT description for the flashes
attached to the controller.
Early on in the probe function we do a pm_runtime_get_noresume() since
the probe function leaves the device in a powered up state but in the
error path we can't assume that PM is enabled so we also manually
disable everything, including clocks. This means that when runtime PM is
active both it and the probe function release the same reference to the
main clock for the IP, triggering warnings from the clock subsystem:
[ 8.693719] clk:75:7 already disabled
[ 8.693791] WARNING: CPU: 1 PID: 185 at /usr/src/kernel/drivers/clk/clk.c:1188 clk_core_disable+0xa0/0xb
...
[ 8.694261] clk_core_disable+0xa0/0xb4 (P)
[ 8.694272] clk_disable+0x38/0x60
[ 8.694283] cqspi_probe+0x7c8/0xc5c [spi_cadence_quadspi]
[ 8.694309] platform_probe+0x5c/0xa4
Dealing with this issue properly is complicated by the fact that we
don't know if runtime PM is active so can't tell if it will disable the
clocks or not. We can, however, sidestep the issue for the flash
descriptions by moving their parsing to when we parse the controller
properties which also save us doing a bunch of setup which can never be
used so let's do that.
Reported-by: Francesco Dolcini <francesco@dolcini.it>
Closes: https://lore.kernel.org/r/20251201072844.GA6785@francesco-nb
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://patch.msgid.link/20251204-spi-cadence-qspi-runtime-pm-imbalance-v2-1-10af9115d531@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Before configuring the registers related to page read, both the
qcom_spi_read_page_ecc() and the qcom_spi_read_page_oob() functions
are calling qcom_spi_set_read_loc() to set the read location for the
first codeword.
However the qcom_spi_set_read_loc() function puts the passed value
into the register write cache only, from where those gets written
to the corresponding register later via DMA.
Yet, the qcom_spi_set_read_loc() is also gets called within the
internal loops, and during the first iteration the read location
register values written by the initial call gets overwritten in
the register cache.
This means that the values written by the first calls are never
getting used in practice, so remove the calls as those are
superfluous.
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://patch.msgid.link/20251129-qpic-snand-superfluous-readloc-v1-1-b84ca17095d9@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Update each register only if it changes.
This also fixes the chipselect related registers not being changed when
chipselect changes but not the mode.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://patch.msgid.link/20251120211204.24078-5-jonathan@marek.ca
Signed-off-by: Mark Brown <broonie@kernel.org>
setup_fifo_params assumes these will be zero, it won't write these
registers if the initial mode is zero.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://patch.msgid.link/20251120211204.24078-4-jonathan@marek.ca
Signed-off-by: Mark Brown <broonie@kernel.org>
mas->cur_bits_per_word may not reflect the value of xfer->bits_per_word
when can_dma() is called. Use the right value instead.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://patch.msgid.link/20251120211204.24078-3-jonathan@marek.ca
Signed-off-by: Mark Brown <broonie@kernel.org>
setup_se_xfer() already sets the correct clock (xfer->speed_hz). Setting
the clock to max_speed_hz here makes the driver change the clock rate
between speed_hz and max_speed_hz for every message (if not equal),
slowing it down significantly.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://patch.msgid.link/20251120211204.24078-2-jonathan@marek.ca
Signed-off-by: Mark Brown <broonie@kernel.org>
The GPI_DMA mode already uses automatic CS control, to use automatic CS
control for non-GPI case all that's needed is to set the FRAGMENTATION flag
using the same logic as setup_gsi_xfer(). (note clearing SPI_TRANS_CFG's
CS_TOGGLE bit enables automatic CS control, the comment was wrong)
spi_geni_set_cs() is slow, so this is a big performance improvement.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://patch.msgid.link/20251120211204.24078-1-jonathan@marek.ca
Signed-off-by: Mark Brown <broonie@kernel.org>
The pm_runtime_mark_last_busy() call is redundant in probe function
as pm_runtime_put_autosuspend() already calls pm_runtime_mark_last_busy()
internally to update the last access time of the device before queuing
autosuspend.
Remove the pm_runtime_mark_last_busy() call from the probe function.
Tested on StarFive VisionFive 2 v1.2A board.
Fixes: e1f2e77624 ("spi: cadence-qspi: Fix runtime PM imbalance in probe")
Signed-off-by: Akif Ejaz <akifejaz40@gmail.com>
Link: https://patch.msgid.link/20251203181921.97171-1-akifejaz40@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Replace OF/ACPI specific call to get matched driver data with
the agnostic one. This doesn't change functionality. While at
it, add missing property.h include, and drop now unneeded of.h.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://patch.msgid.link/20251129150704.3998301-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Replace ACPI specific calls to get device property with the agnostic one.
The code looses the direct dependency to the ACPI APIs and get cleaner.
This doesn't change functionality.
While at it, drop now unneeded acpi.h.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://patch.msgid.link/20251129151739.3998668-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Replace CR_TCIE and CR_TEIE irq usage by a read_poll_timeout_atomic() in
stm32_qspi_wait_cmd(). It will reduce the time waiting for TCF or TEF flags
to optimize throughput.
before after
average time spent in stm32_qspi_wait_cmd: 2615 ns 712 ns
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://patch.msgid.link/20251208-upstream_qspi_ospi_updates-v2-7-62526c9467dc@foss.st.com
Signed-off-by: Mark Brown <broonie@kernel.org>
FIFO accesses uses u8 only for read/write.
In order to optimize throughput, add u16 or u32 read/write
accesses when possible.
Running mtd_speedtest on a 4MB sNOR partition using a
stm32mp257f-ev1 board gives the following results:
before after gain
Read : 5773 KiB/s 22170 KiB/s 384%
Write: 796 KiB/s 890 KiB/s 12%
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://patch.msgid.link/20251208-upstream_qspi_ospi_updates-v2-6-62526c9467dc@foss.st.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Replace CR_TCIE and CR_TEIE irq usage by a read_poll_timeout_atomic() in
stm32_ospi_wait_cmd(). It will reduce the time waiting for TCF or TEF flags
to optimize throughput.
before after
average time spent in stm32_omi_wait_cmd: 5685 ns 923 ns
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://patch.msgid.link/20251208-upstream_qspi_ospi_updates-v2-3-62526c9467dc@foss.st.com
Signed-off-by: Mark Brown <broonie@kernel.org>
FIFO accesses uses u8 only for read/write.
In order to optimize throughput, add u16 or u32 read/write
accesses when possible.
Running mtd_speedtest on a 4MB sNOR partition using a
stm32mp257f-ev1 board gives the following results:
before after gain
Read : 5693 KiB/s 21139 KiB/s 371%
Write: 765 KiB/s 910 KiB/s 19%
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://patch.msgid.link/20251208-upstream_qspi_ospi_updates-v2-2-62526c9467dc@foss.st.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Enable DMA mode for SPI IMX in target mode. Disable the word delay feature
for target mode, because target mode should always keep high performance
to make sure it can follow the master. Target mode continues to operate in
dynamic burst mode.
Signed-off-by: Carlos Song <carlos.song@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20251203085949.2922166-7-carlos.song@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
ECSPI transfers only one word per frame in DMA mode, causing SCLK stalls
between words due to BURST_LENGTH updates, which significantly impacts
performance.
To improve throughput, configure BURST_LENGTH as large as possible (up to
512 bytes per frame) instead of word length. This avoids delays between
words. When transfer length is not 4-byte aligned, use bounce buffers to
align data for DMA. TX uses aligned words for TXFIFO, while RX trims DMA
buffer data after transfer completion.
Introduce a new dma_package structure to store:
1. BURST_LENGTH values for each DMA request
2. Variables for DMA submission
3. DMA transmission length and actual data length
Handle three cases:
- len <= 512 bytes: one package, BURST_LENGTH = len * 8 - 1
- len > 512 and aligned: one package, BURST_LENGTH = max (512 bytes)
- len > 512 and unaligned: two packages, second for tail data
Performance test (spidev_test @10MHz, 4KB):
Before: tx/rx ~6651.9 kbps
After: tx/rx ~9922.2 kbps (~50% improvement)
For compatibility with slow SPI devices, add configurable word delay in
DMA mode. When word delay is set, dynamic burst is disabled and
BURST_LENGTH equals word length.
Signed-off-by: Carlos Song <carlos.song@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20251203085949.2922166-6-carlos.song@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Add error handling for DMA request submission by checking the return
cookie with dma_submit_error(). This prevents propagating submission
failures through the DMA transfer process, which could lead to
unexpected behavior.
Signed-off-by: Carlos Song <carlos.song@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20251203085949.2922166-5-carlos.song@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
If dmaengine_prep_slave_sg() fails, no descriptor is submitted to the TX
channel and DMA is never started. Therefore, calling
dmaengine_terminate_all() for the TX DMA channel is unnecessary.
Signed-off-by: Carlos Song <carlos.song@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20251203085949.2922166-4-carlos.song@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Add a helper function to handle clearing DMA mode, including getting the
maximum watermark length and submitting the DMA request. This refactoring
makes the code more concise and improves readability.
No functional changes.
Signed-off-by: Carlos Song <carlos.song@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20251203085949.2922166-3-carlos.song@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Relocate spi_imx_dma_configure() next to spi_imx_dma_transfer() so that
all DMA-related functions are grouped together for better readability.
No functional changes.
Signed-off-by: Carlos Song <carlos.song@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20251203085949.2922166-2-carlos.song@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
The DMA controller can be used to transfer data to and from the SPI
controller without involving the CPU for each word of a SPI transfer.
Add support for DMA mode.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Link: https://patch.msgid.link/20251201134229.600817-12-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
In preparation for implementing DMA support, enable the transmit buffer
empty interrupt, which is necessary for DMA to write more data to the
FIFO.
This does not affect the PIO mode as we do not even request the TX
interrupt line.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Link: https://patch.msgid.link/20251201134229.600817-9-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
In PIO mode we send data word-by-word, and wait for the received data
to be available after each sent word, making no use of the TX interrupt.
In DMA mode, we need to set the RX and TX FIFO thresholds to 0, as
described in the User Manual.
In preparation for implementing DMA support, set TX FIFO threshold to 0,
as RX FIFO threshold is already 0.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Link: https://patch.msgid.link/20251201134229.600817-8-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
