The device node for the FIFO-buffered Serial Interface sound node lacks
the "clocks" property, as the DTS file didn't describe any clocks yet at
its introduction.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200519075525.24742-1-geert+renesas@glider.be
Add the I2C[0-6] and IIC Bus Interface for DVFS (IIC for DVFS)
devices nodes to the r8a774e1 device tree.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1594811350-14066-14-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add the device nodes for RZ/G2H SCIF and HSCIF serial ports,
including clocks, power domains and DMAs.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1594811350-14066-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This patch adds the CMT[0123] device tree nodes to the
r8a774e1 SoC specific DT.
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/1594811350-14066-7-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add thermal support for R8A774E1 (RZ/G2H) SoC.
Based on the work done for r8a774a1 SoC.
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/1594811350-14066-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The RZ/G2H (r8a774e1) comes with two clusters of processors, similarly to
the r8a774a1. The first cluster is made of A57s, the second cluster is made
of A53s.
The operating points for the cluster with the A57s are:
Frequency | Voltage
----------|---------
500 MHz | 0.82V
1.0 GHz | 0.82V
1.5 GHz | 0.82V
The operating points for the cluster with the A53s are:
Frequency | Voltage
----------|---------
800 MHz | 0.82V
1.0 GHz | 0.82V
1.2 GHz | 0.82V
This patch adds the definitions for the operating points to the SoC
specific DT.
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/1594811350-14066-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Beacon EmebeddedWorks, formerly Logic PD is introducing a new
SOM and development kit based on the RZ/G2M SoC from Renesas.
The SOM supports eMMC, WiFi and Bluetooth, along with a Cat-M1
cellular radio.
The Baseboard has Ethernet, USB, HDMI, stereo audio in and out,
along with a variety of push buttons and LED's, and support for
a parallel RGB and an LVDS display.
Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20200715140622.1295370-1-aford173@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The HiHope RZ/G2H sub board sits below the HiHope RZ/G2H main board.
These boards are identical with the ones for RZ/G2M[N].
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/1594230511-24790-9-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Clock and Power Domain definitions for the Renesas RZ/G2H (R8A774E1)
SoC, shared by driver and DT source files.
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Merge tag 'renesas-r8a774e1-dt-binding-defs-tag' into renesas-arm-dt-for-v5.9
Renesas RZ/G2H DT Binding Definitions
Clock and Power Domain definitions for the Renesas RZ/G2H (R8A774E1)
SoC, shared by driver and DT source files.
A series of changes to configure IPU and DSP remoteproc for omap4 & 5.
And a change to configure the default mux for am335x-pocketbeagle, and
a change to use https for external links.
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Merge tag 'omap-for-v5.9/dt-pt2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt
More dts changes for omaps for v5.9
A series of changes to configure IPU and DSP remoteproc for omap4 & 5.
And a change to configure the default mux for am335x-pocketbeagle, and
a change to use https for external links.
* tag 'omap-for-v5.9/dt-pt2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
Replace HTTP links with HTTPS ones: OMAP DEVICE TREE SUPPORT
ARM: dts: omap5-uevm: Add watchdog timers for IPU and DSP
ARM: dts: omap4-panda-common: Add watchdog timers for IPU and DSP
ARM: dts: omap5-uevm: Add system timers to DSP and IPU
ARM: dts: omap5-uevm: Add CMA pools and enable IPU & DSP
ARM: dts: omap5: Add aliases for rproc nodes
ARM: dts: omap5: Add DSP and IPU nodes
ARM: dts: omap4-panda-common:: Add system timers to DSP and IPU
ARM: dts: omap4-panda-common: Add CMA pools and enable IPU & DSP
ARM: dts: omap4: Add aliases for rproc nodes
ARM: dts: omap4: Add IPU DT node
ARM: dts: omap4: Update the DSP node
ARM: dts: omap5: Add timer_sys_ck clocks for timers
ARM: dts: omap4: Add timer_sys_ck clocks for timers
ARM: dts: am335x-pocketbeagle: set default mux for gpio pins
Link: https://lore.kernel.org/r/pull-1594838111-649880@atomide.com-3
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
A series of changes to drop remaining USB platform data for omap4/5,
and am4, and dra7.
And a patch to drop AES platform data for omap3.
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Merge tag 'omap-for-v5.9/ti-sysc-drop-pdata-take2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt
Drop more legacy platform data for omaps for v5.9
A series of changes to drop remaining USB platform data for omap4/5,
and am4, and dra7.
And a patch to drop AES platform data for omap3.
* tag 'omap-for-v5.9/ti-sysc-drop-pdata-take2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Drop legacy platform data for omap5 usb host
ARM: OMAP2+: Drop legacy platform data for omap4 usb
ARM: OMAP2+: Drop legacy platform data for dra7 dwc3
ARM: OMAP2+: Drop legacy platform data for omap5 dwc3
ARM: OMAP2+: Drop legacy platform data for am4 dwc3
bus: ti-sysc: Add missing quirk flags for usb_host_hs
ARM: dts: omap3: Migrate AES from hwmods to sysc-omap2
Link: https://lore.kernel.org/r/pull-1594838111-649880@atomide.com-2
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Beacon EmbeddedWorks is introducing a development kit based on the
Renesas RZ/G2M platform. This patch adds the entry to the bindings
list.
Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20200714123419.3390-2-aford173@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Make the Makefile for building Renesas DTB files easier to read and
maintain:
- Get rid of line continuations,
- Use a single entry per line,
- Sort SoCs and boards alphabetically,
- Separate SoCs by blank lines.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20200706154015.29257-1-geert+renesas@glider.be
The PHY mode already defaults to RGMII in the RZ/G2E base SoC DTS file,
so there is no need to specify the same value in board files.
Fixes: 6b170cd3ed ("arm64: dts: renesas: cat875: Add ethernet support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20200706151400.23105-1-geert+renesas@glider.be
We can now probe devices with ti-sysc interconnect driver and dts
data. Let's drop the related platform data and custom ti,hwmods
dts property.
As we're just dropping data, and the early platform data init
is based on the custom ti,hwmods property, we want to drop both
the platform data and ti,hwmods property in a single patch.
Signed-off-by: Tony Lindgren <tony@atomide.com>
We can now probe devices with ti-sysc interconnect driver and dts
data. Let's drop the related platform data and custom ti,hwmods
dts property.
As we're just dropping data, and the early platform data init
is based on the custom ti,hwmods property, we want to drop both
the platform data and ti,hwmods property in a single patch.
Signed-off-by: Tony Lindgren <tony@atomide.com>
We can now probe devices with ti-sysc interconnect driver and dts
data. Let's drop the related platform data and custom ti,hwmods
dts property.
As we're just dropping data, and the early platform data init
is based on the custom ti,hwmods property, we want to drop both
the platform data and ti,hwmods property in a single patch.
Signed-off-by: Tony Lindgren <tony@atomide.com>
We can now probe devices with ti-sysc interconnect driver and dts
data. Let's drop the related platform data and custom ti,hwmods
dts property.
As we're just dropping data, and the early platform data init
is based on the custom ti,hwmods property, we want to drop both
the platform data and ti,hwmods property in a single patch.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Odroid-C1 has an eMMC connector where users can optionally install an
eMMC module. The eMMC modules run off a 1.8V VQMMC supply which means
that HS-200 mode can be used (this is the highest mode that the SDHC
controller supports). Enable the SDHC controller so eMMC modules can be
accessed.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200620163654.37207-4-martin.blumenstingl@googlemail.com
EC-100 has built-in eMMC flash which is hard-wired to 3.3V VCC (which
means it's limited to high-speed MMC modes). Enable the SDHC controller
to access the contents of the eMMC flash.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200620163654.37207-3-martin.blumenstingl@googlemail.com
Meson6, Meson8, Meson8b and Meson8m2 are using a similar SDHC controller
IP which typically connects to an eMMC chip (because unlike the SDIO
controller the SDHC controller has an 8-bit bus interface).
On Meson8, Meson8b and Meson8m2 the clock inputs are all the same.
However, Meson8m2 seems to have an improved version of the SHDC
controller IP which doesn't require the driver to wait manually for a
flush of a DMA transfer. Thus every SoC has it's own compatible string
so if more difference are discovered they can be implemented.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200620163654.37207-2-martin.blumenstingl@googlemail.com
The Meson8b SoCs have a power domain controller which can turn on/off
various register areas (such as: Ethernet, VPU, etc.).
Add the main "pwrc" controller and configure the Ethernet power domain.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20200620161010.23171-4-martin.blumenstingl@googlemail.com
The Meson8m2 SoCs has introduced additional reset lines for the VPU
compared to Meson8. Also it uses a slightly different VPU clock
frequency compared to Meson8 since it can now achieve 364MHz thanks to
the addition of the GP_PLL.
Add the reset lines, VPU clock configuration and update the compatible
string so the implementation differences can be managed.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20200620161010.23171-3-martin.blumenstingl@googlemail.com
The Meson8 SoCs have a power domain controller which can turn on/off
various register areas (such as: Ethernet, VPU, etc.).
Add the main "pwrc" controller and configure the Ethernet power domain.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20200620161010.23171-2-martin.blumenstingl@googlemail.com
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The watchdog timers have been added for the IPU and DSP remoteproc
devices for the OMAP5 uEVM board. The following timers (same as the
timers on OMAP4 Panda boards) are used as the watchdog timers,
DSP : GPT6
IPU : GPT9 & GPT11 (one for each Cortex-M4 core)
The MPU-side drivers will use this data to initialize the watchdog
timers, and listen for any watchdog triggers. The BIOS-side code
needs to configure and refresh these timers properly to not throw
a watchdog error.
These timers can be changed or removed as per the system integration
needs, alongside appropriate equivalent changes on the firmware side.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The watchdog timers have been added for the IPU and DSP remoteproc
devices on all the OMAP4-based Panda boards. The following timers
are used as the watchdog timers,
DSP : GPT6
IPU : GPT9 & GPT11 (one for each Cortex-M3 core)
The MPU-side drivers will use this data to initialize the watchdog
timers, and listen for any watchdog triggers. The BIOS-side code
needs to configure and refresh these timers properly to not throw
a watchdog error.
These timers can be changed or removed as per the system integration
needs, alongside appropriate equivalent changes on the firmware side.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The BIOS System Tick timers have been added for the IPU and DSP
remoteproc devices for the OMAP5 uEVM boards. The following timers
(same as the timers on OMAP4 Panda boards) are chosen:
IPU : GPT3 (SMP-mode)
DSP : GPT5
IPU has two Cortex-M4 processors, and is currently expected to be
running in SMP-mode, so only a single timer suffices to provide
the BIOS tick timer. An additional timer should be added for the
second processor in IPU if it were to be run in non-SMP mode. The
timer value also needs to be unique from the ones used by other
processors so that they can be run simultaneously.
The timers are optional, but are mandatory to support device
management features such as power management and watchdog support.
The above are added to successfully boot and execute firmware images
configured with the respective timers, images that use internal
processor subsystem timers are not affected. The timers can be
changed or removed as per the system integration needs, alongside
equivalent changes on the firmware side.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
