Fix a couple of instances of incorrectly sorted nodes in the MSM8916
boards. They should be ordered alphabetically for consistency.
No functional change.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20230921-msm8916-rmem-fixups-v1-3-34d2b6e721cf@gerhold.net
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Enable &wcnss_mem for msm8939-longcheer-l9100. This is needed now to
have WCNSS working. It was missed when &wcnss_mem was disabled by
default because the patch with the msm8939-longcheer-l9100 device tree
was not applied yet.
Fixes: 0ece6438a8 ("arm64: dts: qcom: msm8916/39: Disable unneeded firmware reservations")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: André Apitzsch <git@apitzsch.eu>
Tested-by: André Apitzsch <git@apitzsch.eu>
Link: https://lore.kernel.org/r/20230921-msm8916-rmem-fixups-v1-2-34d2b6e721cf@gerhold.net
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Enable the GPU for the msm8916-samsung-gt58 and gt510 tablets now that
they have display panels enabled in the device tree. This was missed
when the GPU was disabled by default because the change was not applied
yet.
Fixes: 0ce5bb825d ("arm64: dts: qcom: msm8916/39: Disable GPU by default")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20230921-msm8916-rmem-fixups-v1-1-34d2b6e721cf@gerhold.net
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
While the kernel is booting up, APSS clock / CPU clock will be running
at 800MHz with GPLL0 as source. Once the cpufreq driver is available,
APSS PLL will be configured to the rate based on the opp table and the
source also will be changed to APSS_PLL_EARLY. So allow the mailbox to
consume the GPLL0, with this inclusion, CPU Freq correctly reports that
CPU is running at 800MHz rather than 24MHz.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-11-c8ceb1a37680@quicinc.com
[bjorn: Updated commit message, as requested by Kathiravan]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
While the kernel is booting up, APSS clock / CPU clock will be running
at 800MHz with GPLL0 as source. Once the cpufreq driver is available,
APSS PLL will be configured to the rate based on the opp table and the
source also will be changed to APSS_PLL_EARLY. So allow the mailbox to
consume the GPLL0, with this inclusion, CPU Freq correctly reports that
CPU is running at 800MHz rather than 24MHz.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-10-c8ceb1a37680@quicinc.com
[bjorn: Updated commit message, as requested by Kathiravan]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
While the kernel is booting up, APSS clock / CPU clock will be running
at 800MHz with GPLL0 as source. Once the cpufreq driver is available,
APSS PLL will be configured to the rate based on the opp table and the
source also will be changed to APSS_PLL_EARLY. So allow the mailbox to
consume the GPLL0, with this inclusion, CPU Freq correctly reports that
CPU is running at 800MHz rather than 24MHz.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-9-c8ceb1a37680@quicinc.com
[bjorn: Updated commit message, as requested by Kathiravan]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
While the kernel is booting up, APSS clock / CPU clock will be running
at 800MHz with GPLL0 as source. Once the cpufreq driver is available,
APSS PLL will be configured to the rate based on the opp table and the
source also will be changed to APSS_PLL_EARLY. So allow the mailbox to
consume the GPLL0, with this inclusion, CPU Freq correctly reports that
CPU is running at 800MHz rather than 24MHz.
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-8-c8ceb1a37680@quicinc.com
[bjorn: Updated commit message, as requested by Kathiravan]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
IPQ95xx SoCs have different OPPs available for the CPU based on
SoC variant. This can be determined from an eFuse register
present in the silicon.
Add support to read the eFuse and populate the OPPs based on it.
Frequency 1.2GHz 1.8GHz 1.5GHz No opp-supported-hw
Limit
------------------------------------------------------------
936000000 1 1 1 1 0xf
1104000000 1 1 1 1 0xf
1200000000 1 1 1 1 0xf
1416000000 0 1 1 1 0x7
1488000000 0 1 1 1 0x7
1800000000 0 1 0 1 0x5
2208000000 0 0 0 1 0x1
-----------------------------------------------------------
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/14ab08b7cfd904433ca6065fac798d4f221c9d95.1697781921.git.quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
IPQ53xx have different OPPs available for the CPU based on
SoC variant. This can be determined through use of an eFuse
register present in the silicon.
Add support to read the eFuse and populate the OPPs based on it.
------------------------------------------------
Frequency BIT2 BIT1 opp-supported-hw
1.1GHz 1.5GHz
------------------------------------------------
1100000000 1 1 0x7
1500000000 0 1 0x3
------------------------------------------------
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/463f01759cedef3121767d2432aa415794036ce1.1697781921.git.quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The bindings for the CPU frequency scaling driver require a specific
compatible for the SoC. Add the compatible.
Fixes: 0c665213d1 ("arm64: dts: qcom: sdm670: add cpu frequency scaling")
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230816230412.76862-9-mailingradian@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Follow the example of other platforms and extend the PDC resource region
to 0x30000, so that the PDC driver can read the PDC_VERSION register.
Fixes: 397ad94668 ("arm64: dts: qcom: sm8150: Add pdc interrupt controller node")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230929-topic-sm8x50-upstream-pdc-ver-v5-2-800111572104@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add the required BAM and QUP nodes for the QUP1 SPI controller on IPQ5018.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Link: https://lore.kernel.org/r/20231004191303.331055-1-robimarko@gmail.com
[bjorn: Padded address to 8 digits, fixed node sort order]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The rb2 only has a single USB controller, it can be switched between a
type-c port and an internal USB hub via a DIP switch. Until dynamic
role switching is available it's preferable to put the USB controller
in host mode so that the type-A ports and ethernet are available.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Fixes: eaa53a8574 ("arm64: dts: qcom: qrb4210-rb2: Enable USB node")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20231010-caleb-rb2-host-mode-v1-1-b057d443cd62@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add the USB3+DP Combo QMP PHY port subnodes to facilitate the
description of the connection between the hardware blocks.
Put it in the SoC DTSI to avoid duplication in the device DTs.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20230929-sc7280-qmpphy-ports-v2-1-aae7e9c286b0@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
To make dtbs_check happy and the software more aware of what's going
on, describe the HSUSB PHY's regulators and tighten up VDDA_PLL to match.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20230927-topic-6375_stuff-v1-4-12243e36b45c@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add a dtsi file to include interfaces that are common
across RDPs.
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Link: https://lore.kernel.org/r/20230927-common-rdp-v3-1-3d07b3ff6d42@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The sc7280 SoC has a True Random Number Generator, add the node with
the correct compatible set.
Signed-off-by: Om Prakash Singh <quic_omprsing@quicinc.com>
Link: https://lore.kernel.org/r/20231015193901.2344590-5-quic_omprsing@quicinc.com
[bjorn: Padded address to 8 digits, moved hunk to maintain sort order]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The sa8775p SoC has a True Random Number Generator, add the node with
the correct compatible set.
Signed-off-by: Om Prakash Singh <quic_omprsing@quicinc.com>
Link: https://lore.kernel.org/r/20231015193901.2344590-4-quic_omprsing@quicinc.com
[bjorn: Padded address to 8 digits, moved hunk to maintain sort order]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The SM8450 SoC has a True Random Number Generator, add the node with
the correct compatible set.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20231003-topic-sm8550-rng-v4-5-255e4d0ba08e@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add the missing regulator supplies to the ADV7533 HDMI bridge to fix
the following dtbs_check warnings. They are all also supplied by
pm8916_l6 so there is no functional difference.
apq8016-sbc.dtb: bridge@39: 'dvdd-supply' is a required property
apq8016-sbc.dtb: bridge@39: 'pvdd-supply' is a required property
apq8016-sbc.dtb: bridge@39: 'a2vdd-supply' is a required property
from schema display/bridge/adi,adv7533.yaml
Fixes: 28546b0955 ("arm64: dts: apq8016-sbc: Add HDMI display support")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230922-db410c-adv7533-regulators-v1-1-68aba71e529b@gerhold.net
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Now that the pm7250b.dtsi can be configured to be on a different SID, we
also need to specify it for this dts file. Set it to the SID 2/3 like it
was before commit 8e2d56f645 ("arm64: dts: qcom: pm7250b: make SID
configurable").
Fixes: 8e2d56f645 ("arm64: dts: qcom: pm7250b: make SID configurable")
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20230921-pm7250b-sid-fixup-v1-1-231c1a65471f@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Due to the presence of the fastboot micro cable in the CI farm,
it causes the hardware to remain in gadget mode instead of host mode.
So it doesn't find the network, which results in failure to mount root
fs via NFS.
Add an overlay dtso file that sets the dr_mode to host, allowing the
USB controllers to work in host mode. With commit 15d16d6dad
("kbuild: Add generic rule to apply fdtoverlay"), overlay target can
be used to simplify the build of DTB overlays. It uses fdtoverlay to
merge base device tree with the overlay dtso. apq8016-sbc-usb-host.dtb
file can be used by drm-ci, mesa-ci.
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Suggested-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Helen Koike <helen.koike@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Helen Koike <helen.koike@collabora.com>
Link: https://lore.kernel.org/r/20230911161518.650726-1-vignesh.raman@collabora.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add device tree for the Fairphone 5 smartphone which is based on
the QCM6490 SoC.
Supported features are, as of now:
* Bluetooth
* Debug UART
* Display via simplefb
* Flash/torch LED
* Flip cover sensor
* Power & volume buttons
* RTC
* SD card
* USB
* Various plumbing like regulators, i2c, spi, etc
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230919-fp5-initial-v2-7-14bb7cedadf5@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Like other Qualcomm PMICs the PM7250B can be used on different addresses
on the SPMI bus. Use similar defines like the PMK8350 to make this
possible but skip the ifndef based on maintainer feedback.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230919-fp5-initial-v2-3-14bb7cedadf5@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
With the standard Qualcomm TrustZone setup, components such as lpasscc,
pdc_reset and watchdog shouldn't be touched by Linux. Mark them with
the status 'reserved' and reenable them in the chrome-common dtsi.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20230919-fp5-initial-v2-1-14bb7cedadf5@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Fix the apps iommu local address space range as per data sheet.
Fixes: 61550c6c15 ("arm64: dts: qcom: Add msm8939 SoC")
Signed-off-by: Gaurav Kohli <quic_gkohli@quicinc.com>
Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20230917140039.25283-1-quic_gkohli@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Now that SCM has support for indicating that SDI has been enabled by
default, lets set the property so SCM disables it during probing.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Link: https://lore.kernel.org/r/20230816164641.3371878-4-robimarko@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
MSM8976 downstream dts define reloc region which is used by pil-tz
to load both wcnss and lpass, on mainline however we might not be
able to do it and we need separate regions(also validating dts might get
problematic if we had to put memory-region(rproc node) per device).
Luckily it seems size and entry points in firmware headers appears
to be static across multiple devices including Sony Loire platform
and Xiaomi Redmi Note 3 Pro this should let us fit in first ~17MB
Split lpass region(reloc on downstream) into two separate regions.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Link: https://lore.kernel.org/r/20230812112534.8610-7-a39.skl@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add an ICE node to sa8775p SoC description and enable it by adding a
phandle to the UFS node.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230913153529.32777-2-bartosz.golaszewski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The modem firmware size is typically highly device-specific.
The current size of the mpss_mem region in msm8916.dtsi (0x2b00000)
only works for some APQ8016 devices without full-featured modem,
such as the DragonBoard 410c.
The full modem firmware is typically about twice as large (~45 MiB
-> ~90 MiB) but also varies by a few MiB from device to device. Since
these devices are quite memory-constrained nowadays it's important to
minimize the unnecessary memory reservations.
Make it clear that each board needs to specify the necessary mpss_mem
size by replacing the DB410c-specific size in msm8916.dtsi with a
simple comment. &mpss_mem is disabled by default so it's fine to leave
some properties up to the boards if they want to enable it.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20230911-msm8916-rmem-v1-8-b7089ec3e3a1@gerhold.net
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Now that we no longer have fixed addresses for the firmware memory
regions, disable them by default and only enable them together with
the actual user in the board DT.
This frees up unnecessary reserved memory for boards that do not use
some of the remoteprocs and allows moving selected device-specific
properties (such as firmware size) to the board-specific DT part in
the next step.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20230911-msm8916-rmem-v1-7-b7089ec3e3a1@gerhold.net
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Follow the example of MSM8916 and reserve the firmware memory regions
dynamically to allow boards to define only the device-specific parts.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20230911-msm8916-rmem-v1-6-b7089ec3e3a1@gerhold.net
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
At a first glance the MBA memory region on MSM8916 looks intentionally
placed at the fixed address 0x8ea00000. This is what the ELF headers of
the firmware specify as base address, and the typical Qualcomm-specific
bits suggest the binary is not relocatable.
However, on a closer look this is pointless: Unlike other firmware
images the hardware expects to have the raw ELF image loaded to the MBA
region, including the ELF header (without parsing it at all). This
means that we actually just load the ELF header (not the code!) at
0x8ea00000. The real LOAD segments follow at arbitrary aligned
addresses depending on the structure of the ELF binary.
In practice it looks like we can use an arbitrary 1 MiB-aligned region
for MBA. The downstream/vendor kernel just allocates this dynamically
at an arbitrary (aligned) address.
Drop the pointless fixed address and use the new dynamic reserved
memory mechanism to allocate a region close to the others. This reduces
gaps in the memory map and provides Linux with more contiguous memory.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230911-msm8916-rmem-v1-5-b7089ec3e3a1@gerhold.net
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Most of the reserved firmware memory on MSM8916 can be relocated when
respecting the required alignment. To avoid having to precompute the
reserved memory regions in every board DT, describe the actual
requirements (size, alignment, alloc-ranges) using the dynamic reserved
memory allocation.
This approach has several advantages:
1. We can define "templates" for the reserved memory regions in
msm8916.dtsi and keep only device-specific details in the board DT.
This is useful for the "mpss" region size for example, which varies
from device to device. It is no longer necessary to redefine all
firmware regions to shift their addresses.
2. When some of the functionality (e.g. WCNSS, Modem, Venus) is not
enabled or needed for a device, the reserved memory can stay
disabled, freeing up the unused reservation for Linux.
3. Devices with special requirements for one of the firmware regions
are handled automatically. For example, msm8916-longcheer-l8150
has non-relocatable "wcnss" firmware that must be loaded exactly
at address 0x8b600000. When this is defined as a static region,
the other dynamic allocations automatically adjust to a different
place with suitable alignment.
All in all this approach significantly reduces the boilerplate necessary
to define the different firmware regions, and makes it easier to enable
functionality on the different devices.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20230911-msm8916-rmem-v1-4-b7089ec3e3a1@gerhold.net
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
MSM8916/39 do not need signed GPU firmware so it is generally okay to
have it enabled by default. However, currently the GPU does not work
without also enabling MDSS and it's questionable if someone would
really need it without a display in practice.
For consistency let's follow newer SoCs and disable the GPU by default.
Enable it for all existing devices that already have &mdss enabled.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20230911-msm8916-rmem-v1-2-b7089ec3e3a1@gerhold.net
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
