1. Renesas RPC-IF: adjust default setting for pins to accommodate
different flash devices, which should fix 4-bit flash writes with
Renesas AT25QL128A flash.
2. Simplify a bit probe() in PL172 and PL353-SMC.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmbbDM8QHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD11m9D/9+4rfYAIKRuJcLZdqjJiXCy8cdFdQsICg9
QuHvkJ8MLRio/Ep3k/8htslQAsNQJjBfsaWDjALwPGA1322/drkYo8TnVj1JLR3p
N8lfoPTXaPgpe885bH2hQhAsnZqZY1QCg3i5QqWZESuOx3EuGmhn0Uh8YNC/XGvu
GSxiO1o8KpHFCzHvwxSJ8thjq0nS8dKJ9FrS8wQywoEEQW08s+Srz22S7jxlvYrc
HgY2c1bm7XZeXJDDSI7wIK3sgZ7n07bl3S/T5JQ0HElXZ71SvHsbqtHA/4xd6CQE
P2dEfFZq8YNLC7396DzhYI1YAOc+xAW8VPwxGQ3umpwvSU9CTNM9UrZveDCmg+QF
EdGzo9sjUwTJhsImgBjXvZY9Dhr+jXXkyZsBfIN5XCEwItsJHgUlsms4nBkIXHiI
5Du3qC+sHi/1j1KJzRf94YpbX/ldTKyJ7CJWaJRftoTWWR2o5KOKPOGG1iEJHZ/v
UXr+ZX5z2E5Li05g0JnzIP72jpDPyRP1lDI7xHX2BWHLxN1zcSxXGBibBP4KTdnT
0zIjIDiVyq1ync1ZZ634zM5JS1bm9MRHDxR6efOcEhp4mC5q3U0DuDqGay6508ha
fZbSGUfSjOi0rGk3qhyMO0T20Qmi/TibZ5QhWPCjLYYUpLnj0AA68t+cSGFfphFW
vnoQZCHvrQ==
=rd39
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmbhZvcACgkQYKtH/8kJ
Uie+4BAA2oB5HfnM0ofBXvKLaeSWJQpuFa0SR0ttFn4bKYGN+zCPD3ymo34rzJql
ICCFwwtYWVzLQZHHtcbf+PiYSA9W65n0/ClfMMfI57DX2DoOqlqqUDNa4GQvMpdf
Tc54gGms7InjpY+kXTjA162LUODRPNpnYFaOfpY3Mi3ghcocXM5No8GsDFViH3mD
Lsg3Vwkw7XbxsQbSdewdWtlPr79o9ZuJfaIauBmskeG45gio2+504GdwjS952CV0
W0mScZ4BaZoPFTjIQ8bwD1kytdAHUtEC3fwZCFAT3n5ssg4N1ztV/UBkwyRSLnk6
As/20D1DLn8wS8Jgen2P+iETjr9q1Md8A7hfN9+BOJd7N7giriFCNT6uitLWnIzo
qpSJciIAmbHBsI93pHDIbTBZ/AHSrXHUYXNXsiwq7xsd1oui+lbC739EwNRv/B3B
gQzLCm4OWEMIIM5Hun9TVOSESbkxjIj9/nRTJqqJGzAXCoSS68CgKba5LtX2tReD
hcqrWyglpDb4FxP6BVrnqWxFwE+b3rVSWsWvLv30Bo0kDgq9M5SgmvGYyTVdRolF
9wJUjUCz0sxkDOgwKJ2NG/7XUly5YnNIUszvCI+wCWTvgXYue9DsFztl7v5vz1kX
NKJATOApBGtDnxESY1yXQscP73mHE6d//NPsvxsu8jrxzehPL5w=
=71qO
-----END PGP SIGNATURE-----
Merge tag 'memory-controller-drv-6.12-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers
Memory controller drivers for v6.12, part two
1. Renesas RPC-IF: adjust default setting for pins to accommodate
different flash devices, which should fix 4-bit flash writes with
Renesas AT25QL128A flash.
2. Simplify a bit probe() in PL172 and PL353-SMC.
* tag 'memory-controller-drv-6.12-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
memory: pl353-smc: simplify with scoped for each OF child loop
memory: pl172: simplify releasing AMBA regions with devm
memory: renesas-rpc-if: Use Hi-Z state as the default setting for IOVF pins
Link: https://lore.kernel.org/r/20240906140859.71712-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
These two functions have a stub definition when CONFIG_IMX_SCMI_MISC_EXT
is not set, which conflict with the global definition:
In file included from drivers/firmware/imx/sm-misc.c:6:
include/linux/firmware/imx/sm.h:30:1: error: expected identifier or '(' before '{' token
30 | {
| ^
drivers/firmware/imx/sm-misc.c:26:5: error: redefinition of 'scmi_imx_misc_ctrl_get'
26 | int scmi_imx_misc_ctrl_get(u32 id, u32 *num, u32 *val)
| ^~~~~~~~~~~~~~~~~~~~~~
include/linux/firmware/imx/sm.h:24:19: note: previous definition of 'scmi_imx_misc_ctrl_get' with type 'int(u32, u32 *, u32 *)' {aka 'int(unsigned int, unsigned int *, unsigned int *)'}
24 | static inline int scmi_imx_misc_ctrl_get(u32 id, u32 *num, u32 *val)
| ^~~~~~~~~~~~~~~~~~~~~~
There is no real need for the #ifdef, and removing this avoids
the build failure.
Fixes: 0b4f8a68b2 ("firmware: imx: Add i.MX95 MISC driver")
Link: https://lore.kernel.org/r/20240909203023.1275232-1-arnd@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The gpiod_to_irq() function never returns zero. It returns negative
error codes or a positive IRQ number. Update the checking to check
for negatives.
Fixes: 41bb142a40 ("platform: cznic: turris-omnia-mcu: Add support for MCU provided TRNG")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Reviewed-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Support is added for making SCM driver configure the system either for a
full or minimal ramdump following a system crash. The ramdump mode is
changed from being enable-only to enable/disable as requested.
The QSEECOM uefisecapp interface is allow-listed on Surface Laptop 7 and
Lenovo Thinkpad T14s, providing EFI variable access.
The change to match the SMD RPM driver based on the SMD channel name is
reverted, in favor of stepping back to OF-based matching, as a means to
get module autoloading to work properly.
AOSS, APR, ICE, OCMEM, PBS and SMP2P drivers has error handling cleaned
up using scoped resources.
Trace events are added to the BWMON and SMP2P drivers, for better
insights into their operations.
The X1E LLCC configuration data is updated based on recommended values.
A number of platforms are added to the in-kernel PD-mapper.
SocInfo driver is extended with IDs from SM7325, QCS8275 and QCS8300
families.
-----BEGIN PGP SIGNATURE-----
iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmbYs3AVHGFuZGVyc3Nv
bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FjywP/1IDWiKrOrIBYc6ndmssYrQLzlRw
SSt/Q0YjPKogxl4qwTjTQUmBI/1I+vOa7kf9i0/BNpuslnhJYW51r9bZrcI0n3PW
P1Pm7J32WGOIauFU9XoGmqzdlPBCVZKcfeCV3n9xTvF0pAipQqz46+O5mVg77jVU
L5MaVIr4guk/glBJTym97KOlkSSbBsSmheistxiBJUIkUlZqX3YwBQE0Cih1VYOn
DcQy29EjTpxhbLqI5BqFN3iJqGaV3RS32hL9hM8nYlXth0u8ZBy/H9AEViEK8M1K
YakDoRkGyihj0M7oFV405yJdSskEbTBlxAfX7LH7x37XocRpsFf+u/Ti8VWxLMnt
VUciuWA8bg6LnhMK1tQKEGM+3Wp2NZDJStKtV+OnYkvWbKN9QwS4DyiWdPvJGsgJ
j4qq4B3nF3JU8Pu8Ih59LtPPFTa9/jMkOkqmF7smNehji8gjzHmkAhw6fWPCE5+h
p8EC/XrYvXCwkBwPWE5vopip8CIpl3bMPb5bbHYGb4NuY59ztht40EExYxnhQzoN
3ezg+J2jIEaG/HQiBcxt0NrjyLRzkWJVryRxigg1co8Alcmxh7B1UNshiWRI70MA
P3Emjh8Snixnp7ZD5O5hyiJ4yahomsfuCoDjVL6Vk4AYjon4ZjZ8pgcGBLgB1gry
Zvkj5b5vc+8VNHnd
=hZ0b
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmbZvJUACgkQYKtH/8kJ
Uice9w//SXO0VlWitafyNuWwwqZfWZY953j2sjAjPWC2OWLGgjTQPL2sDKaOnvWG
FRl8dZmYRcaEb7C7NeWvs1QrUztvxKDXOCDKlmt82EotyBlH1vLFWJK5KJ3oO0sD
0kQLWDr/KS/QIooXT/PcoFJ0mkpMqYKWV+XLLi+NDQsScMZsGyhZiDdv+qwX3qBw
9lt/srB1VfgW8gBrOGAxmS/WDQ4wup7/KPNpaUTIdPR8JMNFgoMCVY03LkB+FCcM
4s/MeecFzHavshFnZqcWzppf1FNX70lcaWEcbbNopM/bekZICFjGWZGoi+tK/8fZ
WFj3OWZwDGYtxkYjT9M/zvxEJK2xDLosIOICV1dm+OcUN6LAXwknHBuCGMMNDQI1
jOQjZBXn3A+aT/Amy5GpKV0ci4K/tTI6AfBGdlZJq9jsQOMfP8Cygsv6leRp3dpJ
06v2ifSWUTv8+ucwYn/Oz0rZDZAe8ucswybzQo0lyor4Qg8lTZJFIU6iNoT/ZCCZ
wlNg7t1OfkGGr08SuiAhV6+c5/CK2WivxCfKfZjw8+iMLJXyjE57fnf2HaU9Yfwp
iJrV1euITVkLjmyMCg2YJSyWVl8O43T+LBcqreZel2iDJOBgY84zfk5hB/2sLLXj
bo3H9QHD7IlQ3yOafT8zuxtanw3cJfBId34afsYD8h9khVz8OmI=
=6GV4
-----END PGP SIGNATURE-----
Merge tag 'qcom-drivers-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
Qualcomm driver updates for v6.12
Support is added for making SCM driver configure the system either for a
full or minimal ramdump following a system crash. The ramdump mode is
changed from being enable-only to enable/disable as requested.
The QSEECOM uefisecapp interface is allow-listed on Surface Laptop 7 and
Lenovo Thinkpad T14s, providing EFI variable access.
The change to match the SMD RPM driver based on the SMD channel name is
reverted, in favor of stepping back to OF-based matching, as a means to
get module autoloading to work properly.
AOSS, APR, ICE, OCMEM, PBS and SMP2P drivers has error handling cleaned
up using scoped resources.
Trace events are added to the BWMON and SMP2P drivers, for better
insights into their operations.
The X1E LLCC configuration data is updated based on recommended values.
A number of platforms are added to the in-kernel PD-mapper.
SocInfo driver is extended with IDs from SM7325, QCS8275 and QCS8300
families.
* tag 'qcom-drivers-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (33 commits)
firmware: qcom: scm: Allow QSEECOM on Surface Laptop 7 models
dt-bindings: soc: qcom: qcom,pmic-glink: Document SM7325 compatible
soc: qcom: pd_mapper: Add SM7325 compatible
soc: qcom: socinfo: Add Soc IDs for SM7325 family
dt-bindings: arm: qcom,ids: Add IDs for SM7325 family
soc: qcom: socinfo: add QCS8275/QCS8300 SoC ID
dt-bindings: arm: qcom,ids: add SoC ID for QCS8275/QCS8300
soc: qcom: smp2p: use scoped device node handling to simplify error paths
soc: qcom: pbs: use scoped device node handling to simplify error paths
soc: qcom: ocmem: use scoped device node handling to simplify error paths
soc: qcom: ice: use scoped device node handling to simplify error paths
soc: qcom: aoss: simplify with scoped for each OF child loop
soc: qcom: apr: simplify with scoped for each OF child loop
soc: qcom: smd-rpm: add qcom,smd-rpm compatible
dt-bindings: soc: qcom: smd-rpm: add generic compatibles
Revert "soc: qcom: smd-rpm: Match rpmsg channel instead of compatible"
firmware: qcom: scm: Add multiple download mode support
firmware: qcom: scm: Refactor code to support multiple dload mode
soc: qcom: pd_mapper: Add more older platforms without domains
soc: qcom: pd_mapper: Add X1E80100
...
Link: https://lore.kernel.org/r/20240904193042.15118-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
When TSA is compiled as module the following error is reported:
"ucc_mux_set_grant_tsa_bkpt" [drivers/soc/fsl/qe/tsa.ko] undefined!
Indeed, the ucc_mux_set_grant_tsa_bkpt symbol is not exported.
Simply export ucc_mux_set_grant_tsa_bkpt.
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202409051409.fszn8rEo-lkp@intel.com/
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Acked-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- A couple of imx-weim bus driver changes from Wu Bo to support compile
test and use devm_clk_get_enabled() helper to clean up code a bit
-----BEGIN PGP SIGNATURE-----
iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmbYQlAUHHNoYXduZ3Vv
QGtlcm5lbC5vcmcACgkQUFdYWoewfM6C/gf/eWvecmB7fjdWujoUGmpehSdtxUrT
hHAD9wVs9MoU1oUh50tUOlHPiQ1qPY1q8OvT/M0IUkRLgAeHjTvXJERpTS7DAMw5
kOwt3yvVDgTR6ggruqrg8H89UEoN8qmxREOx+zBgt5Olwvy7yXsAwS1a01w9150R
F+d+5oJlRN+B/GJtf9Y5LVLNOOAWABiCe+ZA8szrILOEhb/NFMcz1DEsLu+aMX8P
rkrahtwYtYm61w9ugstKvfZ++FPSFdoS1z5gwhjpPawwwPekLEdcRs/6pSBOUJvT
1Yvy5mhafQR+lHZ1Cl7omMInULHfbzWjtahUzTkmiEkkDrxEopOKhj7R6Q==
=UaVE
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmbZvBMACgkQYKtH/8kJ
UidV+A/9FkgimpLTNcIqCCEAp1oi6q17HAexruJNZ9Ty9LUYbBZqJEWHKXTdzpqO
xFZVaQFc2QuV8SQJ2a2A/TKGdBAtJkcO2MhizClJdkgYriWJ9iyk+5G1j9JDHSc+
yJyCYvtvoS9feNIgPPO+LsCUV/KJujPVP/5NroIdaPqvrIKCSfsbFBUX08gXfZSe
rpiO5PqGLwHcceBDfMilfIQzFePZpOqJZIjYbsLRl9Gj5adZh26B+B0Tw2hxynj/
hIMAz8fKST/1zww/IjIGjcB86dK+fbTTtXjZjRT7AxI17Jhq9/r9iZD/qCu64KNA
NE1G+n1Yi9OuOS2aAGAowgalHzZ08gXGsse56fGxTL7vkN0wSxntcitBihg82LX0
dZYvn8u5WW/qWMe/k4Cq4lw+DeHHhSl2S99SdZDDT0C0zWZ1dP5Pnp0uj+KVOcto
dLvPiz0jixAcOqpcw4qt3VBZTf0LLLBM94ZDL2SGnbMLTu3+6HXKkw74m9SJ7T9q
iYSjEZIdQZRezp8oSPp2V/sfWtqQcj2udfcMqrnNZjUGGoPU+8hqJVbtmU31vgGf
hz/Gok7aytH6w10CdNAUXbeSVcgKHSoRTlorA0LeY75LzptPORZuCrjEX+qpcjuo
bShyvqxApJUXm61JJPsWGs0evFeZEtY8aMwq79CBmv0idIiyb2c=
=+bbh
-----END PGP SIGNATURE-----
Merge tag 'imx-drivers-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/drivers
i.MX drivers changes for 6.12:
- A couple of imx-weim bus driver changes from Wu Bo to support compile
test and use devm_clk_get_enabled() helper to clean up code a bit
* tag 'imx-drivers-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
bus: imx-weim: change to use devm_clk_get_enabled() helper
bus: imx-weim: support compile test
Link: https://lore.kernel.org/r/20240904143439.211552-1-shawnguo2@yeah.net
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Use get_device()/put_device() to keep reset controller devices alive
while their reset controls are acquired.
Enable support for the Amlogic T7 SoC reset controller.
Remove unused EyeQ reset bindings and add a reset controller driver
to be instantiated as auxiliary device by the EyeQ clock driver.
Fix OF node leaks in the k210 and berlin probe() error paths.
Add some simplifications and cleanup in the core, lcp18xx driver, and
uniphier bindings.
-----BEGIN PGP SIGNATURE-----
iI0EABYIADUWIQRRO6F6WdpH1R0vGibVhaclGDdiwAUCZtg4SBcccC56YWJlbEBw
ZW5ndXRyb25peC5kZQAKCRDVhaclGDdiwI3XAP4voAnbJS7rvnqv9zr/V0sXM2ml
UORkWFiRVDVCavLxUwEAy/zDc3ZtcPSx64PE0o6t1Ol8+i2nqivqWUR3dj9WUg4=
=qXYX
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmbZvA0ACgkQYKtH/8kJ
UifHRA/8D7dtCmEKxOdxAIlrntPr2J3kXLA8YsOEH8aWvtJa6UU5yLdKnLOAqZ/u
wiE41oJvcKE7CUphJqGqeOnjHp6j5Vnlb8aRGtwxomBLndxymMiIfYUI7Xe6vuHK
qod6b7/dizqoOhzfa5gkLptRf36tMc4UgXuAS8gOhMe/O7BjBAg2UBSijggSZLOC
g36jJ4eqknp/Vuy+o4B3yYhGm4RpoSbetTiqBulkO41PW0xE+p3h/YcHOYl9CJ6X
3waabEe1/YxHqD+KSDyYQspuwrZdVOctS+DOuUoJsWOls/+n93EftRlzm4GT+5Y4
Ik00sGzC6+p/8V+ecw/4e9kRbTjzAXOaVPTQoc5gIrweaOhUHCovukUQ+b5vcRRs
s8nYfoq4GWzYg59PteCnss4iflbFxuwhKBqrg/ByQ7T8s/EbbwEjKZ3JqVup4Hv8
4go8EVqad60ILwHkmPub8FsnjiyOfkgJfWhS2TxgxRAC5OLqLVQF0asp+gGaKCRJ
xv+Gf8JjDTw09YMW+aWRNsW+7Tg4e27S3KUw18LshFKlBv9+oRsOeAKRKf2z62Nz
0MO1peFHW2tdMhcX6AnGeD9jZUQxHn6DpZvpsAJynvDt/lEAaE49HX+cZPDqBezz
lXQR/g6uC7mY1gWelOGqOYIpBLU2ao+MJ58h0PMpH/+nGclUF5s=
=NcTE
-----END PGP SIGNATURE-----
Merge tag 'reset-for-v6.12' of git://git.pengutronix.de/pza/linux into soc/drivers
Reset controller updates for v6.12
Use get_device()/put_device() to keep reset controller devices alive
while their reset controls are acquired.
Enable support for the Amlogic T7 SoC reset controller.
Remove unused EyeQ reset bindings and add a reset controller driver
to be instantiated as auxiliary device by the EyeQ clock driver.
Fix OF node leaks in the k210 and berlin probe() error paths.
Add some simplifications and cleanup in the core, lcp18xx driver, and
uniphier bindings.
* tag 'reset-for-v6.12' of git://git.pengutronix.de/pza/linux:
reset: eyeq: add platform driver
Revert "dt-bindings: reset: mobileye,eyeq5-reset: add bindings"
reset: reset-meson: Add support for Amlogic T7 SoC reset controller
dt-bindings: reset: Add Amlogic T7 reset controller
reset: core: add get_device()/put_device on rcdev
reset: lpc18xx: simplify with devm_clk_get_enabled()
reset: lpc18xx: simplify with dev_err_probe()
reset: simplify locking with guard()
reset: k210: fix OF node leak in probe() error path
reset: berlin: fix OF node leak in probe() error path
dt-bindings: reset: socionext,uniphier-glue-reset: add top-level constraints
Link: https://lore.kernel.org/r/20240904103921.1479579-1-p.zabel@pengutronix.de
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
QMC driver requires fsl_soc.h to use function get_immrbase().
This header is provided by powerpc architecture and the functions
it declares are defined only when FSL_SOC is selected.
Today the dependency is the following:
depends on CPM1 || QUICC_ENGINE || \
(FSL_SOC && (CPM || QUICC_ENGINE) && COMPILE_TEST)
This dependency tentatively ensure that FSL_SOC is there when doing a
COMPILE_TEST.
CPM1 is only selected by PPC_8xx and cannot be selected manually.
CPM1 selects FSL_SOC
QUICC_ENGINE on the other hand can be selected by ARM or ARM64 which
doesn't select FSL_SOC. QUICC_ENGINE can also be selected with just
COMPILE_TEST.
It is therefore possible to end up with CPM_QMC selected
without FSL_SOC.
So fix it by making it depend on FSL_SOC at all time.
The rest of the above dependency is the same as the one for CPM_TSA on
which CPM_QMC also depends, so it can go away, leaving only a simple
dependency on FSL_SOC.
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Closes: https://lore.kernel.org/lkml/20240904104859.020fe3a9@canb.auug.org.au/
Fixes: 8655b76b70 ("soc: fsl: cpm1: qmc: Handle QUICC Engine (QE) soft-qmc firmware")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Acked-by: Herve Codina <herve.codina@bootlin.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Herve Codina says:
================
This series add support for the QUICC Engine (QE) version of TSA and QMC
components.
CPM1 version is already supported and, as the QE version of those
component are pretty similar to the CPM1 version, the series extend
the already existing drivers to support for the QE version.
The TSA and QMC components are tightly coupled and so the series
provides modifications on both components.
Of course, this series can be split if it is needed. Let me know.
The series is composed of:
- Patches 1 and 2: Fixes related to TRNSYNC in the QMC driver
- Patches 3..6: Fixes of checkpatch detected issues in the TSA driver
- Patch 7: The QE TSA device-tree binding
- Patches 8..13: TSA driver preparations for adding support for QE
- Patches 14 and 15: The support for QE in TSA + MAINTAINERS update
- Patch 16: A TSA API improvement needed for the QE QMC driver
- Patch 17: A clarification in the QE QMC driver
- Patches 18..22: Fixes of checkpatch detected issues in the QMC driver
- Patch 23: The QE QMC device-tree binding
- Patches 24..31: QMC driver preparations for adding support for QE
- Patches 32 and 33: Missing features additions in QE code
- Patches 34..36: The QMC support for QE in QMC + MAINTAINERS update
Compared to the previous iteration, this v2 series updates device-tree
bindings and fixes issues detected by kernel test robots.
Related to the QE QMC device-tree binding, I kept the unit address in
decimal and the 3 compatible strings.
================
Link: https://lore.kernel.org/r/20240808071132.149251-1-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Tested-by: Christophe Leroy <christophe.leroy@csgroup.eu>
This warning was added by commit 07f86917a4 ("soc/fsl/qbman: Use
shared-dma-pool for QMan private memory allocations") but
RESERVEDMEM_OF_DECLARE usage was removed by
commit 3e62273ac6 ("soc: fsl: qbman: Remove RESERVEDMEM_OF_DECLARE
usage") . For non-popwerpc platforms, such as ls1043, this warning
is redundant. ls1043 itself uses shared-dma-mem.
Fixes: 3e62273ac6 ("soc: fsl: qbman: Remove RESERVEDMEM_OF_DECLARE usage")
Signed-off-by: Xiaolei Wang <xiaolei.wang@windriver.com>
Link: https://lore.kernel.org/r/20240802021651.3854295-1-xiaolei.wang@windriver.com
[chleroy: Added more details in commit message]
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
An iommu domain is allocated in portal_set_cpu() and is attached to
pcfg->dev in the same function.
Use iommu_paging_domain_alloc() to make it explicit.
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/20240610085555.88197-14-baolu.lu@linux.intel.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
The Freescale QMC controller driver supports both QE and CPM1.
Add the newly introduced QE files to the existing entry.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-37-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
The QUICC Engine (QE) QMC can use a firmware to have the QMC working in
'soft-qmc' mode.
Handle this optional 'soft-qmc' firmware.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-36-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Add support for the QMC (QUICC Multichannel Controller) available in
some PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321.
This QE QMC is similar to the CPM QMC except that it uses UCCs (Unified
Communication Controllers) instead of SCCs (Serial Communication
Controllers). Also, compared against the CPM QMC, this QE QMC does not
use a fixed area for the UCC/SCC parameters area but it uses a dynamic
area allocated and provided to the hardware at runtime.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-35-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
The PUSHSCHED command is missing in the QE header file.
This command is supported on MPC8321 and is used to modify the start
address for the task running on a given peripheral. It is needed for the
QMC in order to perform the re-initialization procedure and so, ensure
the correct UCC setup in that case.
Simply add the missing command in the commands list available in the QE
header file.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-34-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Introduce devm_cpm_muram_alloc() and devm_cpm_muram_alloc_fixed(), the
resource-managed version of cpm_muram_alloc and cpm_muram_alloc_fixed().
These resource-managed versions simplify the user avoiding the need to
call cpm_muram_free(). Indeed, the allocated area returned by these
functions will be automatically freed on driver detach.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-33-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Current code handles the CPM1 version of QMC.
In order to prepare the support for the QUICC Engine (QE) version of
QMC, introduce qmc_version to identify versions. This will enable the
code to make the distinction between several QMC implementations.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-32-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Current code handles CPM1 version of QMC. Even if GSMRL is specific to
the CPM1 version, the exact same purpose and format register (GUMRL) is
present in the QUICC Engine (QE) version of QMC. Compared to the QE
version, the values defined for the mode bitfield are different and the
0x0A value defined for the QMC mode is CPM1 specific.
In order to prepare the support for the QE version, rename this bitfield
value to clearly identify it as CPM1 specific.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-31-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Current code handles the CPM1 version of QMC, RPACK does not need to
be initialized. This is not the case in the QUICC Engine (QE) version.
In preparation of the support for QE, initialize the RPACK register
when the receiver is initialized and each time it is restarted.
This additional RPACK initialization has no impact in the CPM1 version
of QMC.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-30-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Current code handles CPM1 version of QMC and qmc_chan_command() is
clearly CPM1 specific.
In order to prepare the support for the QUICC Engine (QE) version,
rename qmc_chan_command() to reflect that point.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-29-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Current code handles the CPM1 version of QMC and initialize the QMC used
SCC. The QUICC Engine (QE) version uses an UCC (Unified Communication
Controllers) instead of the SCC (Serial Communication Controllers) used
in the CPM1 version. These controllers serve the same purpose and are
used in the same way but their inializations are slightly different.
In order to prepare the support for QE version of QMC, introduce
qmc_init_xcc() to initialize theses controllers (UCC in QE and SCC in
CPM1) and isolate the CPM1 specific SCC initialization in a specific
function.
Also introduce qmc_exit_xcc() for consistency to revert operations done
in qmc_init_xcc().
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-28-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Current code handles the CPM1 version of QMC. Resources initialisations
(i.e. retrieving base addresses and offsets of different parts) will
be slightly different in the QUICC Engine (QE) version. Indeed, in QE
version, some resources need to be allocated and are no more "staticaly"
defined.
In order to prepare the support for QE version, introduce
qmc_init_resource() to initialize those resources and isolate the CPM1
specific operations in a specific function.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-27-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Current code handles CPM1 version of QMC. In the QUICC Engine (QE)
version, some operations done at probe() need to be done in a different
order.
In order to prepare the support for the QE version, changed the sequence
of operation done at probe():
- Retrieve the tsa_serial earlier, before initializing resources.
- Group SCC initialisation and do this initialization when it is really
needed in the probe() sequence.
Having the QE compatible sequence in the CPM1 version does not lead to
any issue and works correctly without any regressions.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-26-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Current code handles CPM1 version of QMC. Some hardcoded values are used
several times to initialize the QMC state machine. In the QUICC Engine
(QE) version of QMC, these values are different.
In order to prepare the support for the QE version of QMC and avoid the
copy of the hardcoded values, introduce the qmc_data structure to define
these version specific values.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-25-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Add support for the QMC (QUICC Multichannel Controller) available in
some PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321.
This QE QMC is similar to the CPM QMC except that it uses UCCs (Unified
Communication Controllers) instead of SCCs (Serial Communication
Controllers). Also, compared against the CPM QMC, this QE QMC does not
use a fixed area for the UCC/SCC parameters area but it uses a dynamic
area allocated and provided to the hardware at runtime.
Last point, the QE QMC can use a firmware to have the QMC working in
'soft-qmc' mode.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-24-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
checkpatch.pl signals the following improvement for qmc.c
CHECK: Prefer using the BIT macro
Follow its suggestion and convert the code to BIT() and related macros.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-19-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
QMC_TSA_MASK is a bitfield. The value defined is a specific value of
this bitfield and correspond to the use of 8bit resolution for the
routing entry.
Be accurate and rename the defined constant to reflect this point.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-18-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
TSA consumers in CPM1 implementation don't need to know about the serial
device number used by the TSA component. In QUICC Engine implementation,
this information is needed.
Improve the TSA API with tsa_serial_get_num() in order to provide this
information.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-17-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
The Freescale TSA controller driver supports both QE and CPM1.
Add the newly introduced QE files to the existing entry.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-16-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Add support for the time slot assigner (TSA) available in some
PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321.
The QE TSA is similar to the CPM1 TSA except that it uses UCCs (Unified
Communication Controllers) instead of SCCs (Serial Communication
Controllers).
Also, compared against the CPM1 TSA, this QE TSA can handle up to 4 TDMs
instead of 2 and allows to configure the logic level of sync signals.
At a lower level, compared against CPM TSA implementation, some
registers are slightly different even if same features are present.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-15-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Current code handles CPM1 version of TSA.
In order to prepare the support for the QUICC Engine (QE) version of
TSA, introduce tsa_version to identify versions. This will enable the
code to make the distinction between several TSA implementations.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-14-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Current code handles the CPM1 version of TSA. Connecting and
disconnecting the SCC to/from the TSA consists in handling SICR register
which is CPM1 specific. The connection and disconnection operation in
the QUICC Engine (QE) version are slightly different.
In order to prepare the support for the QE version, clearly identify
SICR register as specific to CPM1 and isolate its handling done in
connect and disconnect functions.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-13-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Current code handles the CPM1 version of TSA. Setting up TSA consists in
handling SIMODE and SIGMR registers. These registers are CPM1 specific.
Setting up the QUICC Engine (QE) version of TSA is slightly different.
In order to prepare the support for QE version, clearly identify these
registers as CPM1 compatible and isolate their handling in a CPM1
specific function.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-12-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Current code handles the CPM1 version of TSA. Compared against QUICC
Engine (QE) version of TSA, CPM1 SIRAM entries are slightly different.
In order to prepare the support for the QE version, clearly identify
these entries and functions handling them as CPM1 compatible.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-11-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
