Newer SigmaStar SSD202D SoCs contain a Real Time Clock, capable of
running while the system is sleeping (battery powered), this is not the
case with the other RTC on older SoCs. This adds basic support for this
RTC block.
Signed-off-by: Romain Perier <romain.perier@gmail.com>
Co-developed-by: Daniel Palmer <daniel@0x0f.com>
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Link: https://lore.kernel.org/r/20230913151606.69494-2-romain.perier@gmail.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Merge series from Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>:
New PCI ID, one fix for a delayed IRQ thread causing issues, one
update for debug and one follow-up cleanup for the .remove callback.
Merge series from Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>:
A couple of new boards, one DMI quirk fix and a nice cleanup from
Brent Lu to make all HDMI stuff common across drivers.
The commit referenced in the Fixes tag had a couple problems (as
pointed out by Dan):
- qmp_put was never called, resulting in refcnt leaks
- failling to acquire the QMP mailbox on A7xx would not undo the probe
function properly
- the qmp_put call present in the code was unreachable
Fix all of these issues.
Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
Fixes: 88a0997f2f ("drm/msm/a6xx: Send ACD state to QMP at GMU resume")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/562761/
Signed-off-by: Rob Clark <robdclark@chromium.org>
If the drm/msm init code gets an error during output modeset
initialisation, the kernel will report an error regarding DRM memory
manager not being clean during shutdown. This is because
msm_dsi_modeset_init() allocates a piece of GEM memory for the TX
buffer, but destruction of the buffer happens only at
msm_dsi_host_destroy(), which is called during DSI driver's remove()
time, much later than the DRM MM shutdown.
To solve this issue, move the TX buffer destruction to dsi_unbind(), so
that the buffer is destructed at the correct time. Note, we also have to
store a reference to the address space, because priv->kms->aspace is
cleared before components are unbound.
Reported-by: Bjorn Andersson <andersson@kernel.org>
Fixes: 8f59ee9a57 ("drm/msm/dsi: Adjust probe order")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/562238/
Signed-off-by: Rob Clark <robdclark@chromium.org>
Use exiting function to free the allocated GEM object instead of
open-coding it. This has a bonus of internally calling
msm_gem_put_vaddr() to compensate for msm_gem_get_vaddr() in
msm_get_kernel_new().
Fixes: 1e29dff004 ("drm/msm: Add a common function to free kernel buffer objects")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/562239/
Signed-off-by: Rob Clark <robdclark@chromium.org>
This fixes an error with an incorrect gpio-ranges preventing the PMIC
GPIO instances from being registered on SA877P, and fixes a regression
from a refactoring of the top-level clocks node that caused divclocks to
no longer probe on a few of the MSM8996 devices.
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Merge tag 'qcom-arm64-fixes-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes
Qualcomm ARM64 DeviceTree fixes for v6.6
This fixes an error with an incorrect gpio-ranges preventing the PMIC
GPIO instances from being registered on SA877P, and fixes a regression
from a refactoring of the top-level clocks node that caused divclocks to
no longer probe on a few of the MSM8996 devices.
* tag 'qcom-arm64-fixes-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
arm64: dts: qcom: msm8996-xiaomi: fix missing clock populate
arm64: dts: qcom: apq8096-db820c: fix missing clock populate
arm64: dts: qcom: sa8775p: correct PMIC GPIO label in gpio-ranges
Link: https://lore.kernel.org/r/20231015180112.853805-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
TEST_LENGTH passing ".size = sizeof(struct _struct) - 1" expects -EINVAL
from "if (ucmd.user_size < op->min_size)" check in iommufd_fops_ioctl().
This has been working when min_size is exactly the size of the structure.
However, if the size of the structure becomes larger than min_size, i.e.
the passing size above is larger than min_size, that min_size sanity no
longer works.
Since the first test in TEST_LENGTH() was to test that min_size sanity
routine, rework it to support a min_size calculation, rather than using
the full size of the structure.
Link: https://lore.kernel.org/r/20231015074648.24185-1-nicolinc@nvidia.com
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
The previous patches converted all users of the DSC DPCD caps to look
these up from the connector, so remove the version stored in intel_dp.
A follow-up patchset will read out the MST connector specific
capabilities in intel_dp_add_mst_connector() ->
intel_dp_mst_read_decompression_port_dsc_caps().
v2:
- Rebased on intel_edp_get_dsc_sink_cap() addition in the patchset.
v3:
- Rebased on read-out fix for eDP in the patchset.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231011171606.2540078-3-imre.deak@intel.com
Use the connector's DSC DPCD capabilities in intel_dp_dsc_compute_max_bpp()
instead of the version stored in the encoder.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231006133727.1822579-7-imre.deak@intel.com
Use the connector's DSC DPCD capabilities in i915_dsc_fec_support_show()
instead of the version stored in the encoder. Atm the two are identical,
but a follow-up patch will store the (MST) connector specific version
in the connector.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231006133727.1822579-6-imre.deak@intel.com
Cache the i915 specific device and connector pointers in
i915_dsc_fec_support_show().
v2:
- s/Cahce/Cache typo in commit log. (Stan)
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231006133727.1822579-5-imre.deak@intel.com
Similarly to eDP and SST-DP connectors read out the DSC capabilities for
MST connectors as well. Atm these will match the root port's DSC caps
and only used after a follow-up change enables the decompression for
each stream separately (vs. the current way of enabling it only globally
in the first branch device downstream of the root port).
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231010112504.2156789-3-imre.deak@intel.com
In an MST topology the DSC capabilities are specific to each connector,
retrieved either from the sink if it decompresses the stream, or from a
branch device between the source and the sink in case this branch device
does the decompression. Accordingly each connector needs to cache its
own DSC DPCD and FEC capabilities, along with the AUX device through
which the decompression can be enabled. This patch prepares for that by
storing the capabilities and the DSC AUX device in the connector, for
now these just matching the version stored in intel_dp. The follow-up
patches will convert all users to look up these in the connector instead
of intel_dp, after which the intel_dp copies are removed.
v2:
- Rebased on intel_edp_get_dsc_sink_cap() addition in previous patch.
v3:
- Rebased on read-out fix for eDP in previous patch.
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231011171606.2540078-2-imre.deak@intel.com
Check only the eDP or the DP specific DPCD revision depending on the
sink type. Pass the corresponding revision to the function, which allows
getting the DSC caps of a branch device (in an MST topology, which has
its own DPCD and so DPCD revision).
While at it use DP_DPCD_REV_14 instead of open coding it and for clarity
add a separate function to read out the DSC capability on eDP.
v2:
- Use DP_DPCD_REV_14 instead of open coding it. (Stan)
- Check EDP_DCPD_REV/DPCD_REV in a clearer way. (Ville)
v3:
- Fix the read-out for eDP in intel_dp_detect().
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231011171606.2540078-1-imre.deak@intel.com
RPM master stats is introduced for MSM8226 and MSM8974. The PCIe PHY of
SDX55 is transitioned to the new binding. The hall sensor on the Samsung
Galaxy Tab 4 is inverted.
A number of fixes reported from DeviceTree validation are fixed.
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Merge tag 'qcom-dts-for-6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm ARM DeviceTree updates for v6.7
RPM master stats is introduced for MSM8226 and MSM8974. The PCIe PHY of
SDX55 is transitioned to the new binding. The hall sensor on the Samsung
Galaxy Tab 4 is inverted.
A number of fixes reported from DeviceTree validation are fixed.
* tag 'qcom-dts-for-6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
ARM: dts: qcom: ipq8064: move keys and leds out of soc node
ARM: dts: qcom: mdm9615: populate vsdcc fixed regulator
ARM: dts: qcom: apq8060: drop incorrect regulator-type
ARM: dts: qcom: apq8064: drop incorrect regulator-type
ARM: dts: qcom: sdx65: fix SDHCI clocks order
ARM: dts: qcom: apq8064: drop label property from DSI
ARM: qcom: msm8974: Add rpm-master-stats node
ARM: qcom: msm8226: Add rpm-master-stats node
ARM: dts: qcom: apq8026-samsung-matisse-wifi: Fix inverted hall sensor
ARM: dts: qcom: drop incorrect cell-index from SPMI
ARM: dts: qcom-sdx55: switch PCIe QMP PHY to new style of bindings
Link: https://lore.kernel.org/r/20231015204558.855987-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Currently, all valid MCA_ADDR values are assumed to be usable on AMD
systems. However, this is not correct in most cases. Notifiers expecting
usable addresses may then operate on inappropriate values.
Define a helper function to do AMD-specific checks for a usable memory
address. List out all known cases.
[ bp: Tone down the capitalized words. ]
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20230613141142.36801-3-yazen.ghannam@amd.com
The SM7125 platform is introduced, with support for Xiaomi Redmi Note 9
Pro. Support for Fairphone 5, on QCM6490, and BQ Aquaris M5, on MSM8939,
are introduced.
With the various QMP PHY bindings having been refactored, SC7180,
SC7280, SDM845, SM8150, and SM8250 are transitioned to the new USB/DP
combo PHY binding. IPQ6018, IPQ8074 MSM8998, SC7280, SC8180X, SDM845,
SM8150, SM8250, and SM8450 are transitioned to the new PCIe PHY binding,
and SC8180X is transitioned to the new UFS phy binding.
The UFS power supply situation is clarified, and a range of boards
across MSM8996, MSM8998, SM4250, SM6115, SM6125, SM8350, SM8450, and
SM8550 receives corrections for this.
On IPQ5018 watchdog support is introduced, and the SCM driver has SDI
(debug image) enabled - so that it can be disabled. On IPQ5332 USB is
enabled. The hwspinlock identifier is corrected across IPQ5332, IPQ6018,
IPQ8074 and IPQ9574.
The reserved-memory ranges for the remoteprocs on MSM8916 boards are
refactored, to reduce the amount of duplicated boilerplate definitions.
A number of nodes are transitioned to be disabled by default, to
facilitate new boards.
Samsung Galaxy Tab A 8.0 and Samsung Galaxy Tab A 9.7 gains display
support, and the latter capacitive keys. Samsung Galaxy J5 gains
accelerometer support. The Dragonboard 410c gains missing ADC7533
regulator definition, and an overlay forcing the board to operate in
host mode, for automation purposes.
On MSM8976, the outgoing IPC bits for modem and wcss are corrected, and
reserved-memory regions are updated.
Incorrect reserved-memory regions are also corrected for MSM8992 and
MSM8994 devices.
The QRB2210 RB1 board gets debug UART moved per hardware update.
regulator voltage ranges are corrected, remoteprocs are enabled, USB
SuperSpeed PHY is enabled, and GPIO LEDs are introduced for Bluetooth,
WiFi and a user LED.
Interrupts are described for the SGMII PHYs on SA8775P Ride platform,
and the inline crypto engine is introduced for UFS.
On SC7180 the audio DSP remoteproc is introduced. Additional SKUs of the
Lazor boards are added.The RT5682 audio codec part is reorganized to be
easier to maintain. On Trogdor devices, the touchscreen and display
panels are linked to improve the power cycling behavior across the two.
On SC7280 the cpuidle states are rewritten to support OS-initiated PCSI
mode. LMH interrupts are added, to receive feedback when throttling
occurs. The embedded usb debugger (EUD) description and the dummy
usb-c-connector node is removed, as this is not correctly described. The
USB3 pipe clock input of the global clock controller is properly
described.
Modem remoteproc is introduced on SDM630, and the SDM670 PDC mapping is
corrected.
On the SDM845 MTP PCIe support is introduced. The volumn down and reset
buttons are defined. Remoteproc firmware names and the WiFI
configuration is corrected.
On Sony Xperia XZ2, XZ2 Compact, and XZ3 GPIO lines names are provided
for TLMM and PMICs. The camera regulators are also added.
Display hardware blocks are added to SM6125, and enabled on Sony Xperia
10 II.
The ref clock is wired up to PCIe PHY on SM8150.
On SM8250/QRB5165, and the RB5 board, the DisplayPort controller and the
TCPM is introduced, with all the plumbing to get USB role and
orientation switching, as well as DisplayPort altmode to work.
Interconnects and power-domains are also described for the QUPs on this
platform.
Previously ignored PMICs are described for the SM8350 Hardware
Development Kit (HDK), and PMR735a regulators are introduced. The
pinctrl state for uart18 is corrected.
On SM8450 HDK audio routes are corrected, to enable the analog
microphones on the board. The addition of the PRNG is reverted, in favor
of an upcoming additon of a true RNG.
Constants are replaced with QCOM_SCM_VMID_* defines on a variety of
boards.
The SM8550 QRD board gets Bluetooth support, and the camera clock
controller is described.
Additionally, a number of fixes are introduced in a variety of platforms
and boards, to align with Devicetree bindings.
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Merge tag 'qcom-arm64-for-6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm ARM64 DeviceTree updates for v6.7
The SM7125 platform is introduced, with support for Xiaomi Redmi Note 9
Pro. Support for Fairphone 5, on QCM6490, and BQ Aquaris M5, on MSM8939,
are introduced.
With the various QMP PHY bindings having been refactored, SC7180,
SC7280, SDM845, SM8150, and SM8250 are transitioned to the new USB/DP
combo PHY binding. IPQ6018, IPQ8074 MSM8998, SC7280, SC8180X, SDM845,
SM8150, SM8250, and SM8450 are transitioned to the new PCIe PHY binding,
and SC8180X is transitioned to the new UFS phy binding.
The UFS power supply situation is clarified, and a range of boards
across MSM8996, MSM8998, SM4250, SM6115, SM6125, SM8350, SM8450, and
SM8550 receives corrections for this.
On IPQ5018 watchdog support is introduced, and the SCM driver has SDI
(debug image) enabled - so that it can be disabled. On IPQ5332 USB is
enabled. The hwspinlock identifier is corrected across IPQ5332, IPQ6018,
IPQ8074 and IPQ9574.
The reserved-memory ranges for the remoteprocs on MSM8916 boards are
refactored, to reduce the amount of duplicated boilerplate definitions.
A number of nodes are transitioned to be disabled by default, to
facilitate new boards.
Samsung Galaxy Tab A 8.0 and Samsung Galaxy Tab A 9.7 gains display
support, and the latter capacitive keys. Samsung Galaxy J5 gains
accelerometer support. The Dragonboard 410c gains missing ADC7533
regulator definition, and an overlay forcing the board to operate in
host mode, for automation purposes.
On MSM8976, the outgoing IPC bits for modem and wcss are corrected, and
reserved-memory regions are updated.
Incorrect reserved-memory regions are also corrected for MSM8992 and
MSM8994 devices.
The QRB2210 RB1 board gets debug UART moved per hardware update.
regulator voltage ranges are corrected, remoteprocs are enabled, USB
SuperSpeed PHY is enabled, and GPIO LEDs are introduced for Bluetooth,
WiFi and a user LED.
Interrupts are described for the SGMII PHYs on SA8775P Ride platform,
and the inline crypto engine is introduced for UFS.
On SC7180 the audio DSP remoteproc is introduced. Additional SKUs of the
Lazor boards are added.The RT5682 audio codec part is reorganized to be
easier to maintain. On Trogdor devices, the touchscreen and display
panels are linked to improve the power cycling behavior across the two.
On SC7280 the cpuidle states are rewritten to support OS-initiated PCSI
mode. LMH interrupts are added, to receive feedback when throttling
occurs. The embedded usb debugger (EUD) description and the dummy
usb-c-connector node is removed, as this is not correctly described. The
USB3 pipe clock input of the global clock controller is properly
described.
Modem remoteproc is introduced on SDM630, and the SDM670 PDC mapping is
corrected.
On the SDM845 MTP PCIe support is introduced. The volumn down and reset
buttons are defined. Remoteproc firmware names and the WiFI
configuration is corrected.
On Sony Xperia XZ2, XZ2 Compact, and XZ3 GPIO lines names are provided
for TLMM and PMICs. The camera regulators are also added.
Display hardware blocks are added to SM6125, and enabled on Sony Xperia
10 II.
The ref clock is wired up to PCIe PHY on SM8150.
On SM8250/QRB5165, and the RB5 board, the DisplayPort controller and the
TCPM is introduced, with all the plumbing to get USB role and
orientation switching, as well as DisplayPort altmode to work.
Interconnects and power-domains are also described for the QUPs on this
platform.
Previously ignored PMICs are described for the SM8350 Hardware
Development Kit (HDK), and PMR735a regulators are introduced. The
pinctrl state for uart18 is corrected.
On SM8450 HDK audio routes are corrected, to enable the analog
microphones on the board. The addition of the PRNG is reverted, in favor
of an upcoming additon of a true RNG.
Constants are replaced with QCOM_SCM_VMID_* defines on a variety of
boards.
The SM8550 QRD board gets Bluetooth support, and the camera clock
controller is described.
Additionally, a number of fixes are introduced in a variety of platforms
and boards, to align with Devicetree bindings.
* tag 'qcom-arm64-for-6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (148 commits)
arm64: dts: qcom: apq8016-sbc: Add missing ADV7533 regulators
ARM: dts: qcom: sdx65-mtp: Specify PM7250B SID to use
arm64: dts: qcom: apq8016-sbc: Add overlay for usb host mode
arm64: dts: qcom: qcm6490: Add device-tree for Fairphone 5
dt-bindings: arm: qcom: Add QCM6490 Fairphone 5
arm64: dts: qcom: pm8350c: Add flash led node
arm64: dts: qcom: pm7250b: make SID configurable
arm64: dts: qcom: sc7280: Mark some nodes as 'reserved'
arm64: dts: qcom: msm8939: Fix iommu local address range
arm64: dts: qcom: ipq5018: indicate that SDI should be disabled
arm64: dts: qcom: msm8976: Fix ipc bit shifts
arm64: dts: qcom: msm8976: Split lpass region
arm64: dts: qcom: pm8150l: Add wled node
arm64: dts: qcom: sa8775p: enable the inline crypto engine
arm64: dts: qcom: msm8916/39: Fix venus memory size
arm64: dts: qcom: msm8916/39: Move mpss_mem size to boards
arm64: dts: qcom: msm8916/39: Disable unneeded firmware reservations
arm64: dts: qcom: msm8939: Reserve firmware memory dynamically
arm64: dts: qcom: msm8916: Reserve MBA memory dynamically
arm64: dts: qcom: msm8916: Reserve firmware memory dynamically
...
Link: https://lore.kernel.org/r/20231015191107.854658-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Linux enables MSI-X before disabling INTx, but keeps MSI-X masked until
the table is filled. Then it disables INTx just before clearing MASKALL
bit. Currently this approach is rejected by xen-pciback.
According to the PCIe spec, device cannot use INTx when MSI/MSI-X is
enabled (in other words: enabling MSI/MSI-X implicitly disables INTx).
Change the logic to consider INTx disabled if MSI/MSI-X is enabled. This
applies to three places:
- checking currently enabled interrupts type,
- transition to MSI/MSI-X - where INTx would be implicitly disabled,
- clearing INTx disable bit - which can be allowed even if MSI/MSI-X is
enabled, as device should consider INTx disabled anyway in that case
Fixes: 5e29500eba ("xen-pciback: Allow setting PCI_MSIX_FLAGS_MASKALL too")
Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
Acked-by: Juergen Gross <jgross@suse.com>
Link: https://lore.kernel.org/r/20231016131348.1734721-1-marmarek@invisiblethingslab.com
Signed-off-by: Juergen Gross <jgross@suse.com>
Virtio guests send VIRTIO_MMIO_QUEUE_NOTIFY notification when they need
to notify the backend of an update to the status of the virtqueue. The
backend or another entity, polls the MMIO address for updates to know
when the notification is sent.
It works well if the backend does this polling by itself. But as we move
towards generic backend implementations, we end up implementing this in
a separate user-space program.
Generally, the Virtio backends are implemented to work with the Eventfd
based mechanism. In order to make such backends work with Xen, another
software layer needs to do the polling and send an event via eventfd to
the backend once the notification from guest is received. This results
in an extra context switch.
This is not a new problem in Linux though. It is present with other
hypervisors like KVM, etc. as well. The generic solution implemented in
the kernel for them is to provide an IOCTL call to pass the address to
poll and eventfd, which lets the kernel take care of polling and raise
an event on the eventfd, instead of handling this in user space (which
involves an extra context switch).
This patch adds similar support for xen.
Inspired by existing implementations for KVM, etc..
This also copies ioreq.h header file (only struct ioreq and related
macros) from Xen's source tree (Top commit 5d84f07fe6bf ("xen/pci: drop
remaining uses of bool_t")).
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Juergen Gross <jgross@suse.com>
Link: https://lore.kernel.org/r/b20d83efba6453037d0c099912813c79c81f7714.1697439990.git.viresh.kumar@linaro.org
Signed-off-by: Juergen Gross <jgross@suse.com>
Currently the handling of events is supported either in the kernel or
userspace, but not both.
In order to support fast delivery of interrupts from the guest to the
backend, we need to handle the Queue notify part of Virtio protocol in
kernel and the rest in userspace.
Update the interrupt handler registration flag to IRQF_SHARED for event
channels, which would allow multiple entities to bind their interrupt
handler for the same event channel port.
Also increment the reference count of irq_info when multiple entities
try to bind event channel to irqchip, so the unbinding happens only
after all the users are gone.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Juergen Gross <jgross@suse.com>
Link: https://lore.kernel.org/r/99b1edfd3147c6b5d22a5139dab5861e767dc34a.1697439990.git.viresh.kumar@linaro.org
Signed-off-by: Juergen Gross <jgross@suse.com>
Prepare for the coming implementation by GCC and Clang of the __counted_by
attribute. Flexible array members annotated with __counted_by can have
their accesses bounds-checked at run-time via CONFIG_UBSAN_BOUNDS (for
array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family
functions).
While there, use struct_size() helper, instead of the open-coded
version, to calculate the size for the allocation of the whole
flexible structure, including of course, the flexible-array member.
This code was found with the help of Coccinelle, and audited and
fixed manually.
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Reviewed-by: Kees Cook <keescook@chromium.org>
Reviewed-by: Jason Andryuk <jandryuk@gmail.com>
Link: https://lore.kernel.org/r/ZSRMosLuJJS5Y/io@work
Signed-off-by: Juergen Gross <jgross@suse.com>
In case an error occurs in xenbus_init(), xen_store_domain_type should
be set to XS_UNKNOWN.
Fix one instance where this action is missing.
Fixes: 5b3353949e ("xen: add support for initializing xenstore later as HVM domain")
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <error27@gmail.com>
Link: https://lore.kernel.org/r/202304200845.w7m4kXZr-lkp@intel.com/
Signed-off-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>
Link: https://lore.kernel.org/r/20230822091138.4765-1-jgross@suse.com
Signed-off-by: Juergen Gross <jgross@suse.com>
There are no longer any users of cpus_have_const_cap(), and therefore it
can be removed.
Remove cpus_have_const_cap(). At the same time, remove
__cpus_have_const_cap(), as this is a trivial wrapper of
alternative_has_cap_unlikely(), which can be used directly instead.
The comment for __system_matches_cap() is updated to no longer refer to
cpus_have_const_cap(). As we have a number of ways to check the cpucaps,
the specific suggestions are removed.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Kristina Martsenko <kristina.martsenko@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
In arch_tlbbatch_should_defer() we use cpus_have_const_cap() to check
for ARM64_WORKAROUND_REPEAT_TLBI, but this is not necessary and
alternative_has_cap_*() would be preferable.
For historical reasons, cpus_have_const_cap() is more complicated than
it needs to be. Before cpucaps are finalized, it will perform a bitmap
test of the system_cpucaps bitmap, and once cpucaps are finalized it
will use an alternative branch. This used to be necessary to handle some
race conditions in the window between cpucap detection and the
subsequent patching of alternatives and static branches, where different
branches could be out-of-sync with one another (or w.r.t. alternative
sequences). Now that we use alternative branches instead of static
branches, these are all patched atomically w.r.t. one another, and there
are only a handful of cases that need special care in the window between
cpucap detection and alternative patching.
Due to the above, it would be nice to remove cpus_have_const_cap(), and
migrate callers over to alternative_has_cap_*(), cpus_have_final_cap(),
or cpus_have_cap() depending on when their requirements. This will
remove redundant instructions and improve code generation, and will make
it easier to determine how each callsite will behave before, during, and
after alternative patching.
The cpus_have_const_cap() check in arch_tlbbatch_should_defer() is an
optimization to avoid some redundant work when the
ARM64_WORKAROUND_REPEAT_TLBI cpucap is detected and forces the immediate
use of TLBI + DSB ISH. In the window between detecting the
ARM64_WORKAROUND_REPEAT_TLBI cpucap and patching alternatives this is
not a big concern and there's no need to optimize this window at the
expsense of subsequent usage at runtime.
This patch replaces the use of cpus_have_const_cap() with
alternative_has_cap_unlikely(), which will avoid generating code to test
the system_cpucaps bitmap and should be better for all subsequent calls
at runtime. The ARM64_WORKAROUND_REPEAT_TLBI cpucap is added to
cpucap_is_possible() so that code can be elided entirely when this is
not possible without requiring ifdeffery or IS_ENABLED() checks at each
usage.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
In has_useable_cnp() we use cpus_have_const_cap() to check for
ARM64_WORKAROUND_NVIDIA_CARMEL_CNP, but this is not necessary and
cpus_have_cap() would be preferable.
For historical reasons, cpus_have_const_cap() is more complicated than
it needs to be. Before cpucaps are finalized, it will perform a bitmap
test of the system_cpucaps bitmap, and once cpucaps are finalized it
will use an alternative branch. This used to be necessary to handle some
race conditions in the window between cpucap detection and the
subsequent patching of alternatives and static branches, where different
branches could be out-of-sync with one another (or w.r.t. alternative
sequences). Now that we use alternative branches instead of static
branches, these are all patched atomically w.r.t. one another, and there
are only a handful of cases that need special care in the window between
cpucap detection and alternative patching.
Due to the above, it would be nice to remove cpus_have_const_cap(), and
migrate callers over to alternative_has_cap_*(), cpus_have_final_cap(),
or cpus_have_cap() depending on when their requirements. This will
remove redundant instructions and improve code generation, and will make
it easier to determine how each callsite will behave before, during, and
after alternative patching.
We use has_useable_cnp() to determine whether we have the system-wide
ARM64_HAS_CNP cpucap. Due to the structure of the cpufeature code, we
call has_useable_cnp() in two distinct cases:
1) When finalizing system capabilities, setup_system_capabilities() will
call has_useable_cnp() with SCOPE_SYSTEM to determine whether all
CPUs have the feature. This is called after we've detected any local
cpucaps including ARM64_WORKAROUND_NVIDIA_CARMEL_CNP, but prior to
patching alternatives.
If the ARM64_WORKAROUND_NVIDIA_CARMEL_CNP was detected, we will not
detect ARM64_HAS_CNP.
2) After finalizing system capabilties, verify_local_cpu_capabilities()
will call has_useable_cnp() with SCOPE_LOCAL_CPU to verify that CPUs
have CNP if we previously detected it.
Note that if ARM64_WORKAROUND_NVIDIA_CARMEL_CNP was detected, we will
not have detected ARM64_HAS_CNP.
For case 1 we must check the system_cpucaps bitmap as this occurs prior
to patching the alternatives. For case 2 we'll only call
has_useable_cnp() once per subsequent onlining of a CPU, and as this
isn't a fast path it's not necessary to optimize for this case.
This patch replaces the use of cpus_have_const_cap() with
cpus_have_cap(), which will only generate the bitmap test and avoid
generating an alternative sequence, resulting in slightly simpler annd
smaller code being generated. The ARM64_WORKAROUND_NVIDIA_CARMEL_CNP
cpucap is added to cpucap_is_possible() so that code can be elided
entirely when this is not possible.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
In gic_read_iar() we use cpus_have_const_cap() to check for
ARM64_WORKAROUND_CAVIUM_23154 but this is not necessary and
alternative_has_cap_*() would be preferable.
For historical reasons, cpus_have_const_cap() is more complicated than
it needs to be. Before cpucaps are finalized, it will perform a bitmap
test of the system_cpucaps bitmap, and once cpucaps are finalized it
will use an alternative branch. This used to be necessary to handle some
race conditions in the window between cpucap detection and the
subsequent patching of alternatives and static branches, where different
branches could be out-of-sync with one another (or w.r.t. alternative
sequences). Now that we use alternative branches instead of static
branches, these are all patched atomically w.r.t. one another, and there
are only a handful of cases that need special care in the window between
cpucap detection and alternative patching.
Due to the above, it would be nice to remove cpus_have_const_cap(), and
migrate callers over to alternative_has_cap_*(), cpus_have_final_cap(),
or cpus_have_cap() depending on when their requirements. This will
remove redundant instructions and improve code generation, and will make
it easier to determine how each callsite will behave before, during, and
after alternative patching.
The ARM64_WORKAROUND_CAVIUM_23154 cpucap is detected and patched early
on the boot CPU before the GICv3 driver is initialized and hence before
gic_read_iar() is ever called. Thus it is not necessary to use
cpus_have_const_cap(), and alternative_has_cap() is equivalent.
In addition, arm64's gic_read_iar() lives in irq-gic-v3.c purely for
historical reasons. It was originally added prior to 32-bit arm support
in commit:
6d4e11c5e2 ("irqchip/gicv3: Workaround for Cavium ThunderX erratum 23154")
When support for 32-bit arm was added, 32-bit arm's gic_read_iar()
implementation was placed in <asm/arch_gicv3.h>, but the arm64 version
was kept within irq-gic-v3.c as it depended on a static key local to
irq-gic-v3.c and it was easier to add ifdeffery, which is what we did in
commit:
7936e914f7 ("irqchip/gic-v3: Refactor the arm64 specific parts")
Subsequently the static key was replaced with a cpucap in commit:
a4023f6827 ("arm64: Add hypervisor safe helper for checking constant capabilities")
Since that commit there has been no need to keep arm64's gic_read_iar()
in irq-gic-v3.c.
This patch replaces the use of cpus_have_const_cap() with
alternative_has_cap_unlikely(), which will avoid generating code to test
the system_cpucaps bitmap and should be better for all subsequent calls
at runtime. For consistency, move the arm64-specific gic_read_iar()
implementation over to arm64's <asm/arch_gicv3.h>. The
ARM64_WORKAROUND_CAVIUM_23154 cpucap is added to cpucap_is_possible() so
that code can be elided entirely when this is not possible.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
