"spi-controller" is not a documented property nor used anywhere, so drop
it.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250306-dt-amd-fixes-v1-4-011c423ba99a@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The fixed clocks are not part of "simple-bus", so move them out of the
bus to the top-level. In the process, use the preferred node names of
"clock-<freq>". There's also little reason to have multiple fixed
clocks at the same frequencies, so remove them keeping the labels
to minimize the change.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250306-dt-amd-fixes-v1-2-011c423ba99a@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The HDA hardware on Tegra114 is almost identical to the one found on
Tegra30 or Tegra124. Add a compatible string to allow matching in case
it's ever needed. Typically the match on Tegra30 should be sufficient.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Tegra124 MIPI hardware block is very similar to the one found on
earlier chip generations. Add a corresponding compatible string.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This adds new SoCs and new machines, other than improving support for
currently supported ones.
In particular, for SoCs:
- Airoha EN7581 gets support for its SCU clock controller, SPI NAND,
hardware RNG, pinctrl, and i2c controllers;
- MediaTek MT8365 SoC gets support for all of its Display Controller
components;
- MediaTek Genio 510 MT8370 - a lower binned variant of Genio 700
MT8390 (which, in turn, is the same as MT8188) - is introduced;
- MT8188 gets support for more Display Controller components (DSC
and MERGE), for the tertiary MSDC (eMMC/SD/SDIO) controller, and
for the MTU3 USB DRD controllers;
- MT8195 and MT8188 both get migrated to the new OF Graph used for
defining a pipeline for the Display Controller components (as
this was previously hardcoded per-board in the drm driver, ugh!);
..and for boards:
- Google Kukui (MT8183) is switched to Elan touchscreen driver
instead of hid-over-i2c to fix probe failures in some cases;
- Google Cherry (MT8195) and Geralt (MT8188) Chromebooks get
migrated to using OF Graph for defining their board specific
part of the display pipeline;
- MediaTek Genio 350 (mt8365) EVK board adds support for HDMI output
through the iTE IT66121 chip, and for DSI output to the Startek
KD070FHFID015 display;
- MediaTek Genio 510 EVK board is introduced with a common devicetree
between mt8390 and mt8370 (Genio 700 and Genio 510) EVKs;
- MediaTek Genio 700 (and 510) EVKs get support for their integrated
dual Digital Microphones, for their RichTek RT1715 USB Type-C
Controller with USB-PD capability, the iTE IT5205 Alternate Mode
Passive MUX (USB3.1/DP1.4), and for USB Gadget/Host switching
through the MTU3 DRD Controller, other than for USB in general;
- MediaTek Genio 1200 EVK gets support for its MediaTek MT6360 PMIC
integrated Type-C Controller, and the IT5205 MUX;
- Radxa NIO-12L gets its DSI display pipeline preconfigured and also
the introduction of a devicetree overlay for the official Radxa
8HD DSI panel, enabling display output over DSI.
And fixes/cleanups:
- MT8173 gets fixes for bindings validation: PMIC node drops the
unnecessary address/size cells, disp-pwm gets its compatibles
list fixed (as mt6595 was not expected there), and some nodes
got the right name (clock controllers were disguides as power
controllers, and intpol was changed to interrupt-controller);
- MT8188-based (MT8390) Genio boards get a fix for duplicated
regulator name;
- MT6359 PMIC gets fixes for audio-codec node validation.
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Merge tag 'mtk-dts64-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
MediaTek ARM64 DTS updates for v6.15
This adds new SoCs and new machines, other than improving support for
currently supported ones.
In particular, for SoCs:
- Airoha EN7581 gets support for its SCU clock controller, SPI NAND,
hardware RNG, pinctrl, and i2c controllers;
- MediaTek MT8365 SoC gets support for all of its Display Controller
components;
- MediaTek Genio 510 MT8370 - a lower binned variant of Genio 700
MT8390 (which, in turn, is the same as MT8188) - is introduced;
- MT8188 gets support for more Display Controller components (DSC
and MERGE), for the tertiary MSDC (eMMC/SD/SDIO) controller, and
for the MTU3 USB DRD controllers;
- MT8195 and MT8188 both get migrated to the new OF Graph used for
defining a pipeline for the Display Controller components (as
this was previously hardcoded per-board in the drm driver, ugh!);
..and for boards:
- Google Kukui (MT8183) is switched to Elan touchscreen driver
instead of hid-over-i2c to fix probe failures in some cases;
- Google Cherry (MT8195) and Geralt (MT8188) Chromebooks get
migrated to using OF Graph for defining their board specific
part of the display pipeline;
- MediaTek Genio 350 (mt8365) EVK board adds support for HDMI output
through the iTE IT66121 chip, and for DSI output to the Startek
KD070FHFID015 display;
- MediaTek Genio 510 EVK board is introduced with a common devicetree
between mt8390 and mt8370 (Genio 700 and Genio 510) EVKs;
- MediaTek Genio 700 (and 510) EVKs get support for their integrated
dual Digital Microphones, for their RichTek RT1715 USB Type-C
Controller with USB-PD capability, the iTE IT5205 Alternate Mode
Passive MUX (USB3.1/DP1.4), and for USB Gadget/Host switching
through the MTU3 DRD Controller, other than for USB in general;
- MediaTek Genio 1200 EVK gets support for its MediaTek MT6360 PMIC
integrated Type-C Controller, and the IT5205 MUX;
- Radxa NIO-12L gets its DSI display pipeline preconfigured and also
the introduction of a devicetree overlay for the official Radxa
8HD DSI panel, enabling display output over DSI.
And fixes/cleanups:
- MT8173 gets fixes for bindings validation: PMIC node drops the
unnecessary address/size cells, disp-pwm gets its compatibles
list fixed (as mt6595 was not expected there), and some nodes
got the right name (clock controllers were disguides as power
controllers, and intpol was changed to interrupt-controller);
- MT8188-based (MT8390) Genio boards get a fix for duplicated
regulator name;
- MT6359 PMIC gets fixes for audio-codec node validation.
* tag 'mtk-dts64-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: (35 commits)
arm64: dts: mediatek: mt8395-radxa-nio-12l: Add Radxa 8 HD panel
arm64: dts: mediatek: mt8395-nio-12l: Prepare MIPI DSI port
arm64: dts: mediatek: mt8390-genio-common: Add delay codec for DMIC
arm64: dts: mediatek: mt8390-genio-common: Add routes for DMIC
arm64: dts: mediatek: mt8395-nio-12l: Preconfigure DSI0 pipeline
arm64: mediatek: mt8195-cherry: Add graph for eDP and DP displays
arm64: dts: mediatek: mt8195: Add base display controller graph
arm64: dts: airoha: en7581: Fix clock-controller address
arm64: dts: airoha: en7581: Add more nodes to EN7581 SoC evaluation board
arm64: dts: mediatek: mt8390-genio-common: Configure touch vreg pins
arm64: dts: mediatek: mt8188-geralt: Add graph for DSI and DP displays
arm64: dts: mediatek: mt8188: Add base display controller graph
arm64: dts: mediatek: mt8390-genio-700: Add USB, TypeC Controller, MUX
arm64: dts: mediatek: mt8188: Add MTU3 nodes and correctly describe USB
dt-bindings: usb: mediatek,mtk-xhci: Add port for SuperSpeed EP
arm64: dts: mediatek: mt8395-genio-1200-evk: add support for TCPC port
dt-bindings: usb: mtu3: Add ports property
arm64: dts: mediatek: mt8390-genio-common: Fix duplicated regulator name
arm64: dts: mediatek: mt8183: Switch to Elan touchscreen driver
arm64: dts: mediatek: mt6359: fix dtbs_check error for audio-codec
...
Link: https://lore.kernel.org/r/20250306113540.148342-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Remove "regulator-ramp-delay-scale" property which is both unused in the
kernel and undocumented. Most likely they are leftovers from downstream.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250305224952.2995841-2-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The main and bulk of the addition this time is the support for the Arm
reference Morello System Development Platform (SDP).
The Morello architecture is an experimental extension to Armv8.2-A,
enhancing the AArch64 execution state with capabilities for fine-grained
memory protection and scalable software compartmentalization. However
these changes doesn't add any of the support for security enhancements.
This is mainly adding device tree support for Morello SDP.
The platform iteslf is shipped with ACPI firmware. However, since the
ACPI bindings for GPU, DPU, I2C, I2S,..etc are not well defined or not
provided in the shipped ACPI firmware, there is a need for the device
tree as alternative for the developers focusing on those features.
The CPU is called rainier, the architecture is Morello and the platform
is Morello SDP board. There is FVP equivalent of the same though they
are not completely in feature parity with the real hardware.
These changes provide the initial support for Morello SDP and FVP
platforms.
Apart from this, we have an update to add support for secondary cores
on Corstone1000 FVP platform.
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Merge tag 'juno-updates-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt
Armv8 FVP/Vexpress/Juno updates for v6.15
The main and bulk of the addition this time is the support for the Arm
reference Morello System Development Platform (SDP).
The Morello architecture is an experimental extension to Armv8.2-A,
enhancing the AArch64 execution state with capabilities for fine-grained
memory protection and scalable software compartmentalization. However
these changes doesn't add any of the support for security enhancements.
This is mainly adding device tree support for Morello SDP.
The platform iteslf is shipped with ACPI firmware. However, since the
ACPI bindings for GPU, DPU, I2C, I2S,..etc are not well defined or not
provided in the shipped ACPI firmware, there is a need for the device
tree as alternative for the developers focusing on those features.
The CPU is called rainier, the architecture is Morello and the platform
is Morello SDP board. There is FVP equivalent of the same though they
are not completely in feature parity with the real hardware.
These changes provide the initial support for Morello SDP and FVP
platforms.
Apart from this, we have an update to add support for secondary cores
on Corstone1000 FVP platform.
* tag 'juno-updates-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: corstone1000: Add definitions for secondary CPU cores
MAINTAINERS: Add Vincenzo Frascino as Arm Morello Maintainer
arm64: dts: morello: Add support for fvp dts
arm64: dts: morello: Add support for soc dts
arm64: dts: morello: Add support for common functionalities
dt-bindings: arm-pmu: Add support for ARM Rainier PMU
dt-bindings: arm: Add Rainier compatibility
dt-bindings: arm: Add Morello fvp compatibility
dt-bindings: arm: Add Morello compatibility
arm64: Kconfig: Update description for CONFIG_ARCH_VEXPRESS
Link: https://lore.kernel.org/r/20250304105856.432848-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add support for the second and third Ethernet interfaces on the Gray
Hawk Single development board,
- Add Image Signal Processor helper block (FCPVX and VSPX) support for
the R-Car V3U and V4M SoCs,
- Add Watchdog and System Controller support for the RZ/G3E SoC and
the RZ/G3E SMARC Carrier-II EVK development board,
- Add initial support for the Yuridenki-Shokai Kakip and MYIR Remi Pi
boards,
- Add support for the spare UART and PMOD serial ports on the RZ/G3S
SMARC Carrier II board,
- Add a CPU Operating Performance Points table for the RZ/G3S SoC,
- Add boot phase tags on R-Car Gen2/3/4 and RZ/G2 boards,
- Miscellaneous fixes and improvements.
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Merge tag 'renesas-dts-for-v6.15-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.15
- Add support for the second and third Ethernet interfaces on the Gray
Hawk Single development board,
- Add Image Signal Processor helper block (FCPVX and VSPX) support for
the R-Car V3U and V4M SoCs,
- Add Watchdog and System Controller support for the RZ/G3E SoC and
the RZ/G3E SMARC Carrier-II EVK development board,
- Add initial support for the Yuridenki-Shokai Kakip and MYIR Remi Pi
boards,
- Add support for the spare UART and PMOD serial ports on the RZ/G3S
SMARC Carrier II board,
- Add a CPU Operating Performance Points table for the RZ/G3S SoC,
- Add boot phase tags on R-Car Gen2/3/4 and RZ/G2 boards,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.15-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (34 commits)
ARM: dts: renesas: r9a06g032: Fix UART dma channel order
arm64: dts: renesas: rzg2: Add boot phase tags
arm64: dts: renesas: rcar: Add boot phase tags
ARM: dts: renesas: rcar-gen2: Add boot phase tags
arm64: dts: renesas: white-hawk-csi-dsi: Use names for CSI-2 data line orders
arm64: dts: renesas: ulcb/kf: Use TDM Split Mode for capture
arm64: dts: renesas: Add initial support for MYIR Remi Pi
arm64: dts: renesas: r9a08g045: Add OPP table
arm64: dts: renesas: r9a09g057: Enable SYS node
arm64: dts: renesas: r9a09g047: Add SYS node
arm64: dts: renesas: r9a08g045: Enable SYS node
arm64: dts: renesas: r8a779f0: Disable rswitch ports by default
arm64: dts: renesas: r9a08g045s33-smarc-pmod: Add overlay for SCIF1
arm64: dts: renesas: rzg3s-smarc: Enable SCIF3
arm64: dts: renesas: rzg3s-smarc-switches: Add a header to describe different switches
arm64: dts: renesas: r8a779g0: Restore sort order
arm64: dts: renesas: s4sk: Fix ethernet0 alias for rswitch
arm64: dts: renesas: spider-ethernet: Add ethernetN aliases for rswitch
arm64: dts: renesas: s4sk: Access rswitch ports via phandles
arm64: dts: renesas: spider-ethernet: Access rswitch ports via phandles
...
Link: https://lore.kernel.org/r/cover.1740156747.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Document support for the Yuridenki-Shokai Kakip (based on RZ/V2H)
and MYIR Remi Pi (based on RZ/G2L) boards,
- Document support for the RZ/G3E System Controller.
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Merge tag 'renesas-dt-bindings-for-v6.15-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DT binding updates for v6.15
- Document support for the Yuridenki-Shokai Kakip (based on RZ/V2H)
and MYIR Remi Pi (based on RZ/G2L) boards,
- Document support for the RZ/G3E System Controller.
* tag 'renesas-dt-bindings-for-v6.15-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
dt-bindings: soc: renesas: Document MYIR Remi Pi board
dt-bindings: soc: renesas: Add RZ/G3E variant SYS binding
dt-bindings: soc: renesas: Document Yuridenki-Shokai Kakip board
dt-bindings: vendor-prefixes: Add Yuridenki-Shokai Co. Ltd.
dt-bindings: soc: renesas: Document more Renesas RZ/V2H SoC variants
Link: https://lore.kernel.org/r/cover.1740156745.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Assing the right NPE for EthA
- Fix up erroneous PCI mappings on WG302
- Add LEDs and keys on GPIO to WG302
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Merge tag 'ixp4xx-dts-soc-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into soc/dt
Some minor IXP4xx updates for v6.15:
- Assing the right NPE for EthA
- Fix up erroneous PCI mappings on WG302
- Add LEDs and keys on GPIO to WG302
* tag 'ixp4xx-dts-soc-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: dts: ixp4xx: Add Netgear WG302 v1 GPIOs
ARM: dts: ixp4xx: Fix up PCI on WG302
ARM: dts: Properly assign NPE to ethA
Link: https://lore.kernel.org/r/CACRpkdbi_A_RCufEZSk0cEoQ_H-s0VLGUzJ9zPQECSvsUP7-dQ@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The Radxa 8 HD touchscreen can be used with various Radxa board
and is sold appart from the Radxa NIO 12L development kit.
Add a DTS overlay for this panel.
Signed-off-by: Julien Massot <julien.massot@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250304-radxa-panel-overlay-v2-2-3ee6797d3f86@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This board can use a MIPI-DSI panel on the DSI0 connector: in
preparation for adding an overlay for the Radxa Display 8HD,
add the backlight, and some definitions for pins available
through the DSI0 port.
Signed-off-by: Julien Massot <julien.massot@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250304-radxa-panel-overlay-v2-1-3ee6797d3f86@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
The signal from the dual digital microphones connected to the DMIC_BE
takes 30ms to settle after being enabled. Add a dmic-codec with
corresponding wakeup-delay-ms to prevent an initial "pop" sound when
recording with the microphones.
Co-developed-by: Zoran Zhan <zoran.zhan@mediatek.com>
Signed-off-by: Zoran Zhan <zoran.zhan@mediatek.com>
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250225-genio700-dmic-v2-8-3076f5b50ef7@collabora.com
[Angelo: Resolved merge conflicts]
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Add necessary routes for the onboard dual DMIC present on the Genio
700/510 EVK. The dmic is supplied by micbias0 and micbias2, and inputs
into the MT8188 DMIC DAI.
Co-developed-by: parkeryang <Parker.Yang@mediatek.com>
Signed-off-by: parkeryang <Parker.Yang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20250225-genio700-dmic-v2-6-3076f5b50ef7@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This board can use a MIPI-DSI panel on the DSI0 connector: in
preparation for adding an overlay for the Radxa Display 8HD,
add a pipeline connecting VDOSYS0 components to DSI0.
This pipeline remains disabled by default, as it is expected
to be enabled only by a devicetree overlay that declares the
actual DSI panel node, completing the graph.
Link: https://lore.kernel.org/r/20250213112008.56394-4-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
The base SoC devicetree now defines a display controller graph:
connect the board specific outputs (eDP internal display, DP
external display) to fully migrate Cherry and make it finally
possible to make Chromebooks and other board types to coexist
without per-board driver modifications.
Link: https://lore.kernel.org/r/20250213112008.56394-3-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
The display related IPs in MT8195 are flexible and support being
interconnected with different instances of DDP IPs and/or with
different DDP IPs, forming a full Display Data Path that ends
with an actual display output, which is board specific.
Add a common graph in the main mt8195.dtsi devicetree, which is
shared between all of the currently supported boards.
All boards featuring any display functionality will extend this
common graph to hook the display controller of the SoC to their
specific output port(s).
Link: https://lore.kernel.org/r/20250213112008.56394-2-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Fix the following warning for clock-controller node:
DTC [C] arch/arm64/boot/dts/airoha/en7581-evb.dtb
arch/arm64/boot/dts/airoha/en7581.dtsi:176.37-181.5: Warning (simple_bus_reg): /soc/clock-controller@1fa20000: simple-bus unit address format error, expected "1fb00000"
Fixes: 7693017580 ("arm64: dts: airoha: en7581: Add Clock Controller node")
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250221-en7581-dts-spi-pinctrl-v3-2-4719e2d01555@kernel.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Introduce the following nodes to EN7581 SoC and EN7581 evaluation board:
- rng controller
- pinctrl
- i2c controllers
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250221-en7581-dts-spi-pinctrl-v3-1-4719e2d01555@kernel.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Add a pinctrl configuration for the Touchscreen IC's power line
to make sure that the pin is configured as GPIO and to stop
relying on correct pin configuration from bootloader.
Link: https://lore.kernel.org/r/20250220110948.45596-5-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
The base SoC devicetree now defines a display controller graph:
connect the board specific outputs (eDP internal display, DP
external display) to fully migrate Cherry and make it finally
possible to make Chromebooks and other board types to coexist
without per-board driver modifications.
Tested-by: Chen-Yu Tsai <wenst@chromium.org> # On MT8188 Ciri (int. and ext.)
Link: https://lore.kernel.org/r/20250220110948.45596-4-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Add cpu{1-3} device nodes to the corstone1000 device tree to enable the
support for secondary CPU cores.
This update facilitates symmetric multiprocessing (SMP) support on the
corstone1000 Fixed Virtual Platform (FVP), allowing the secondary cores
to be properly initialised and utilised.
Only FVP platform will have SMP support and hence the secondary cpu
definitions are not added to corstone1000.dtsi.
Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
Message-Id: <20250303170012.469576-1-hugues.kambampiana@arm.com>
(sudeep.holla: Added psci enable-method for cpu0)
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
The Morello architecture is an experimental extension to Armv8.2-A,
which extends the AArch64 state with the principles proposed in
version 7 of the Capability Hardware Enhanced RISC Instructions
(CHERI) ISA.
Introduce Morello fvp dts.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Message-Id: <20250221180349.1413089-10-vincenzo.frascino@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
The Morello architecture is an experimental extension to Armv8.2-A,
which extends the AArch64 state with the principles proposed in
version 7 of the Capability Hardware Enhanced RISC Instructions
(CHERI) ISA.
Introduce Morello SoC dts.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Message-Id: <20250221180349.1413089-9-vincenzo.frascino@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
The Morello architecture is an experimental extension to Armv8.2-A,
which extends the AArch64 state with the principles proposed in
version 7 of the Capability Hardware Enhanced RISC Instructions
(CHERI) ISA.
The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share
some functionalities that have conveniently been included in
morello.dtsi to avoid duplication.
Introduce morello.dtsi.
Note: Morello fvp will be introduced with a future patch series.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Message-Id: <20250221180349.1413089-8-vincenzo.frascino@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Add support for the ARM Rainier CPU core PMU.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Message-Id: <20250221180349.1413089-6-vincenzo.frascino@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Add compatibility to Arm Morello System Development Platform.
Note: Morello is at the same time the name of an Architecture [1], an SoC
[2] and a Board [2].
To distinguish in between Architecture/SoC and Board we refer to the first
as arm,morello and to the second as arm,morello-sdp.
[1] https://developer.arm.com/Architectures/Morello
[2] https://www.morello-project.org/
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Message-Id: <20250221180349.1413089-3-vincenzo.frascino@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Update the description and contextually the help text of
CONFIG_ARCH_VEXPRESS to reflect the inclusion of all ARM Ltd Platforms.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Message-Id: <20250221180349.1413089-2-vincenzo.frascino@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Adds device tree entries for the touchbar digitizer
Co-developed-by: Janne Grunau <j@jannau.net>
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Neal Gompa <neal@gompa.dev>
Acked-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Sasha Finkelstein <fnkl.kernel@gmail.com>
Link: https://lore.kernel.org/r/20250225-z2-dts-v1-1-df101a7c17c8@gmail.com
Signed-off-by: Sven Peter <sven@svenpeter.dev>
The display related IPs in MT8188 are flexible and support being
interconnected with different instances of DDP IPs and/or with
different DDP IPs, forming a full Display Data Path that ends
with an actual display output, which is board specific.
Add a common graph in the main mt8188.dtsi devicetree, which is
shared between all of the currently supported boards.
All boards featuring any display functionality will extend this
common graph to hook the display controller of the SoC to their
specific output port(s).
Tested-by: Chen-Yu Tsai <wenst@chromium.org> # On MT8188 Ciri (int. and ext.)
Link: https://lore.kernel.org/r/20250220110948.45596-2-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This board features multiple USB connectors:
* One Type-C connector with Power Delivery and Alt. Modes;
* One MicroUSB connector, also used for bootloader SW download;
* One USB through the RaspberryPi-compatible pins header.
Add configuration for the MTU3 controllers providing OTG support
with role switching both on the MicroUSB port, RPi pins header,
and the Type-C port found on this board.
Moreover, add the Richtek RT1715 Type-C Power Delivery Controller
which manages current source/sink, linked to the iTE IT5205 Type-C
Alternate Mode Passive Mux, handling both mode switching between
USB (up to 3.1 Gen2 10Gbps) and DisplayPort (four lanes, DP1.4,
op to 8.1Gbps) and plug orientation switching.
All USB ports reside on different controller instances, and all of
them support host or gadget and can be configured as desired at
runtime.
Link: https://lore.kernel.org/r/20250220105514.43107-4-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
The MT8188 SoC has three USB controllers, and all of them are behind
the MTU3 DRD controller.
Add the missing MTU3 nodes, default disabled, for all USB controllers
and move the related XHCI nodes to be children of their MTU3 DRD to
correctly describe the SoC.
In order to retain USB functionality on all of the MT8188 and MT8390
boards, also move the vusb33 supply and enable the relevant MTU3 nodes
with special attention to the MT8188 Geralt Chromebooks, where it was
necessary to set the dr_mode of all MTU3 controllers to host to avoid
interfering with the EC performing DRD on its own.
Tested-by: Chen-Yu Tsai <wenst@chromium.org> # on MT8188 Ciri
Link: https://lore.kernel.org/r/20250220105514.43107-3-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Add a port used to connect the SuperSpeed output endpoint to a
Type-C connector.
Note that the MediaTek XHCI controllers are always in front of a
different controller handling the USB HS (usually, MTU3), so the
only port that this controller provides is SuperSpeed, while the
HighSpeed one comes from elsewhere.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250220105514.43107-2-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Enable USB Type-C support on MediaTek MT8395 Genio 1200 EVK by adding
configuration for TCPC Port, USB-C connector, MUX IT5205 and related
settings.
Configure dual role switch capability, set up PD (Power Delivery) profiles,
and establish endpoints for SS (SuperSpeed) and HS (HighSpeed) USB.
Update pinctrl configurations for U3 P0 VBus default pins and set dr_mode
to "otg" for OTG (On-The-Go) mode operation.
Add ITE IT5205 (TYPEC MUX) under I2C2 bus and configure its properties;
also add references and configurations to 'typec-mux' node.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Yow-Shin Liou <yow-shin.liou@mediatek.com>
Signed-off-by: Simon Sun <simon.sun@yunjingtech.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Link: https://lore.kernel.org/r/20250224114934.3583191-1-macpaul.lin@mediatek.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Define the ports property in the mediatek,mtu3 device tree binding schema.
Include definitions for port@0 and port@1, specifying their roles as
High Speed (HS) and Super Speed (SS) data buses, respectively.
Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Link: https://lore.kernel.org/r/20250220142230.2530583-1-macpaul.lin@mediatek.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
usb_p2_vbus regulator has the same regulator-name property value as
sdio_fixed_3v3, so change it to avoid this.
Fixes: a4fd1943bf ("arm64: dts: mediatek: mt8390-genio-700-evk: update regulator names")
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250221-fix-mtk8390-genio-common-dup-regulator-name-v1-1-92f7b9f7a414@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
After commit 2be404486c ("HID: i2c-hid-of: Add reset GPIO support to
i2c-hid-of"), the i2c-hid-of driver used by some mt8183 devices resets
the touchscreen without having enough post-reset delay. This makes those
touchscreen fail to get probed.
Switch to Elan touchscreen driver, which has enough post-reset delay.
Fixes: 2be404486c ("HID: i2c-hid-of: Add reset GPIO support to i2c-hid-of")
Signed-off-by: Hsin-Te Yuan <yuanhsinte@chromium.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
bootph-all as phase tag was added to dt-schema
(dtschema/schemas/bootph.yaml) to describe various node usage during
boot phases with DT. Add bootph-all for all nodes that are used in the
bootloader on Renesas RZ/G2 SoCs.
All SoC require CPG clock and its input clock, RST Reset, PFC pin
control and PRR ID register access during all stages of the boot
process, those are marked using bootph-all property, and so is the SoC
bus node which contains these IP.
Each board console UART is also marked as bootph-all to make it
available in all stages of the boot process.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250209180616.160253-3-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
