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64,840 commits

Author SHA1 Message Date
Fabio Estevam
72370a5cc2 ARM: mx5/mx51_babbage: Use gpio_request_array for USBH1 pins
Instead of using gpio_request followed by gpio_direction_output use gpio_request_array
when requesting multiple pins.

Also fixed the location of the delay for the reset and make the BABBAGE_USB_PHY_RESET to toggle.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 09:59:56 +02:00
Fabio Estevam
2e7b1bfcb9 ARM: mx5/mx51_babbage: Move GPIO initialization for USB PHY Reset line to common place
The USB PHY Reset GPIO can be configured in the same place as the other GPIOs.

While at it rename the pin as BABBAGE_USB_PHY_RESET to make clearer its purpose.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 09:59:56 +02:00
Troy Kisky
58f45e3c6f ARM: i.MX53: Fix IOMUX type o's
", o" was used for ", 0"

", 17" was used for ", 7 | 0x10"

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 09:59:42 +02:00
Lothar Waßmann
9d73242458 mach-mx5: fix the I2C clock parents
The clock from which the I2C timing is derived is the ipg_perclk not ipg_clk.

I2C bus frequency was lower by a factor of ~8 due to the clock divider
calculation being based on 66.5MHz IPG clock while the bus actually
uses 8MHz ipg_perclk.

Kernel version: 3.0.0-rc2 branch 'imx-for-next' of git://git.pengutronix.de/git/imx/linux-2.6

Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 09:07:46 +02:00
Uwe Kleine-König
23e99d4cae ARM: mxs/tx28: according to the TX28's datasheet D4-D7 are not used for MMC0
The pins are actually used (not in mainline yet):

	D4 -> SSP2_D0
	D5 -> GPIO
	D6 -> GPIO
	D7 -> GPIO for owire

so their pinmapping for SSP0 is wrong.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 09:07:45 +02:00
Axel Lin
b9b65860e7 ARM i.MX23/28: platform-mxsfb: Add missing include of linux/dma-mapping.h
Fix below build error:
  CC      arch/arm/mach-mxs/devices/platform-mxsfb.o
arch/arm/mach-mxs/devices/platform-mxsfb.c: In function 'mx23_add_mxsfb':
arch/arm/mach-mxs/devices/platform-mxsfb.c:27: error: implicit declaration of function 'DMA_BIT_MASK'
make[2]: *** [arch/arm/mach-mxs/devices/platform-mxsfb.o] Error 1
make[1]: *** [arch/arm/mach-mxs/devices] Error 2
make: *** [arch/arm/mach-mxs] Error 2

Signed-off-by: Axel Lin <axel.lin@gmail.com>
Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 09:07:43 +02:00
Fabio Estevam
d7336b837f ARM: mx53: Fix some interrupts marked as reserved.
Mark the actual interrupt source for some interrupts currently marked as reserved.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 09:07:42 +02:00
Troy Kisky
425933b30b MXC: iomux-v3: correct NO_PAD_CTRL definition
iomux-v3.c uses NO_PAD_CTRL as a 32 bit value
so it should not be shifted left by MUX_PAD_CTRL_SHIFT(41)

Previously, anything requesting NO_PAD_CTRL would get
their pad control register set to 0.

Since it is a pad control mask, place it with the other mask values.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Lothar Waßmann <LW@KARO-electronics.de>
Tested-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 09:07:41 +02:00
Fabio Estevam
429a035d1d ARM: mx51: Fix the address space length for SSI
On MX51 the address space length for SSI is 16KB.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 09:07:39 +02:00
Shawn Guo
187e5f26a8 ARM: mxc: imx-dma on imx25 has no other TO version but TO1
The imx25 sdma script only gets TO1 version, so there is no need
to encode "to1" in the variable name.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 09:07:38 +02:00
Shawn Guo
ee8814db96 ARM: mxc: change imx-dma default to_version to 1
The value 0 is not a valid TO version number.  With the current
code, imx-sdma driver will try to load firmware sdma-imx25-to0.bin,
which is obviously not a good name.  Instead, sdma-imx25-to1.bin
makes much more sense.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 09:07:37 +02:00
Shawn Guo
aa5f380cb0 ARM: mxc: sdma on imx25 is a V2 block
The sdma on soc imx25 is not a V1 but V2 block.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 09:07:36 +02:00
Shawn Guo
420766a97a ARM: mxc: imx-sdma device gets 16K iosize than 4K
The sdma on all imx soc gets 16K IO space not 4K.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 09:07:34 +02:00
Fabio Estevam
6cecabb391 ARM: mxc: iomux-v1: Fix build warning
Fix the following warning:

CC      arch/arm/plat-mxc/iomux-v1.o
arch/arm/plat-mxc/iomux-v1.c: In function 'mxc_gpio_setup_multiple_pins':
arch/arm/plat-mxc/iomux-v1.c:160: warning: 'ret' may be used uninitialized in this function
arch/arm/plat-mxc/iomux-v1.c:160: note: 'ret' was declared here

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 09:07:33 +02:00
Fabio Estevam
aec250dc12 ARM: mach-imx/mx27_3ds: Fix regulator support
Fix the 2.8V (VMMC1) and 1.8V (VGEN) voltage generation on mx27_3ds.

Also configure the IOMUX for the PMIC interrupt pin and for the CSPI chip select that is connected
to the MC13783 PMIC.

In order to get the voltage for the LCD (2.8V and 1.8V) it is also necessary to turn on GPO1 and GPO3
supplies because they are connected to switches that enable these two voltages.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 09:07:30 +02:00
Fabio Estevam
581f84e24b mxc: iomuxv1: Do not use gpio_request when setting the pin as GPIO
When setting the IOMUX of multiple pins via mxc_gpio_setup_multiple_pins, gpio_request
is called and this prevents subsequent calls of gpio_request done by drivers to succeed.

Remove gpio_request call from mxc_gpio_setup_multiple_pins function.

As gpio_request is removed from mxc_gpio_setup_multiple_pins, there is no need to have
mxc_gpio_release_multiple_pins anymore, so remove this function.

Tested on a mx27_3ds board and after applying this patch it is possible to define all the
IOMUX setup in a static array

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 09:06:58 +02:00
Fabio Estevam
b2a08e3e46 ARM: mach-imx/mx31_3ds: Fix IOMUX for SPI1 signals
Original code was assuming that the CSPI1 pins on the
MX31PDK were the primary pin function, which is incorrect.

On MX31PDK board these are the pins that provide CSPI1 functionality:

DSR_DCE1 (ALT mode 1) --> CSPI1_CLK
RI_DCE1 (ALT mode 1) --> CSPI1_RDY

DTR_DTE1  -->CSI1_MOSI
DSR_DTE1 --> CSPI1_MISO
DTR_DCE2 ---> CSPI1_SS2

The 3 IOMUX settings above are done via GPR as per Table A-1 of the MX31RM.

This patch fixes the CSPI1 IOMUX and makes the LCD to be functional.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 09:06:57 +02:00
Fabio Estevam
98618cfe22 ARM: mach-imx/mx27_3ds: Use the standard i.MX macro for GPIO numbering
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 09:06:53 +02:00
Marc Kleine-Budde
9333d8731f ARM: mx53: Fix the base addresses for the DDR memory regions
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 08:45:04 +02:00
Fabio Estevam
2aee401e03 ARM: mx53: Fix the chip select addresses
MX53 has 4 chip selects (CS0 - CS3) and the valid combinations are:

- CS0 (128MB)
- CS0 (64MB), CS1 (64MB)
- CS0 (64MB), CS1 (32MB), CS2 (32MB)
- CS0 (32MB), CS1 (32MB), CS2 (32MB) , CS3 (32MB)

Fix these addresses and also take into account all the four possibilities.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 08:45:03 +02:00
Fabio Estevam
f2abaae42e ARM: mx53: Fix alternate modes for MX53_PAD_PATA_DATA6
MX53_PAD_PATA_DATA6 can have the following alternate modes:

PATA_DATA_6:  		mode 0
GPIO2_6:		mode 1
EMI_NANDF_D_6:		mode 3
ESDHC4_DAT6		mode 4
GPU3d_GPU_DEBUG_OUT_6	mode 5
IPU_DIAG_BUS_6		mode 6

Fix the modes accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Dinh Nguyen <dinh.nguyen@freescale.com>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 08:45:01 +02:00
Fabio Estevam
38c7364917 mx51: Let USB Storage be built by default
Let USB Storage be built by default.

Also select NLS_ISO8859 so that the USB device can be mounted.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 08:45:00 +02:00
Shawn Guo
9bb7fa1e65 ARM: mxs_defconfig: Change CONFIG_RTC_CLASS 'm' to 'y'
The patch fixes the warning below.

arch/arm/configs/mxs_defconfig:92:warning: symbol value 'm' invalid for RTC_CLASS

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-07-07 08:44:58 +02:00
Kees Cook
7a3136666b x86, suspend: Restore MISC_ENABLE MSR in realmode wakeup
Some BIOSes will reset the Intel MISC_ENABLE MSR (specifically the
XD_DISABLE bit) when resuming from S3, which can interact poorly with
ebba638ae7. In 32bit PAE mode, this can
lead to a fault when EFER is restored by the kernel wakeup routines,
due to it setting the NX bit for a CPU that (thanks to the BIOS reset)
now incorrectly thinks it lacks the NX feature. (64bit is not affected
because it uses a common CPU bring-up that specifically handles the
XD_DISABLE bit.)

The need for MISC_ENABLE being restored so early is specific to the S3
resume path. Normally, MISC_ENABLE is saved in save_processor_state(),
but this happens after the resume header is created, so just reproduce
the logic here. (acpi_suspend_lowlevel() creates the header, calls
do_suspend_lowlevel, which calls save_processor_state(), so the saved
processor context isn't available during resume header creation.)

[ hpa: Consider for stable if OK in mainline ]

Signed-off-by: Kees Cook <kees.cook@canonical.com>
Link: http://lkml.kernel.org/r/20110707011034.GA8523@outflux.net
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Cc: Rafael J. Wysocki <rjw@sisk.pl>
Cc: <stable@kernel.org> 2.6.38+
2011-07-06 20:09:34 -07:00
Daniel Drake
a0f30f592d x86, olpc: Add XO-1.5 SCI driver
Add a driver for the ACPI-based EC event interface found on the
OLPC XO-1.5 laptop. This enables notification of battery/AC power events,
and enables various devices to be used as wakeup sources through regular
ACPI mechanisms.

This driver can't be built as a module, because some drivers need to know
at boot-time if SCI-based functionality is available via
olpc_ec_wakeup_available().

Signed-off-by: Daniel Drake <dsd@laptop.org>
Link: http://lkml.kernel.org/r/1309019658-1712-12-git-send-email-dsd@laptop.org
Acked-by: Andres Salomon <dilinger@queued.net>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2011-07-06 14:44:43 -07:00
Daniel Drake
cfee95977b x86, olpc: Add XO-1 RTC driver
Add a driver to configure the XO-1 RTC via CS5536 MSRs, to be used as a
system wakeup source via olpc-xo1-pm.

Device detection is based on finding the relevant device tree node.

Signed-off-by: Daniel Drake <dsd@laptop.org>
Link: http://lkml.kernel.org/r/1309019658-1712-11-git-send-email-dsd@laptop.org
Acked-by: Andres Salomon <dilinger@queued.net>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Reviewed-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2011-07-06 14:44:42 -07:00
Daniel Drake
e1040ac693 x86, olpc-xo1-sci: Propagate power supply/battery events
EC events indicate change in AC power connectivity, battery state of
charge, battery error, battery presence, etc. Send notifications to
the power supply subsystem when changes are detected.

Signed-off-by: Daniel Drake <dsd@laptop.org>
Link: http://lkml.kernel.org/r/1309019658-1712-10-git-send-email-dsd@laptop.org
Acked-by: Andres Salomon <dilinger@queued.net>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2011-07-06 14:44:40 -07:00
Daniel Drake
2cf2baea10 x86, olpc-xo1-sci: Add lid switch functionality
Configure the XO-1's lid switch GPIO to trigger an SCI interrupt,
and correctly expose this input device which can be used as a wakeup
source.

Signed-off-by: Daniel Drake <dsd@laptop.org>
Link: http://lkml.kernel.org/r/1309019658-1712-9-git-send-email-dsd@laptop.org
Acked-by: Andres Salomon <dilinger@queued.net>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2011-07-06 14:44:39 -07:00
Daniel Drake
7bc74b3df7 x86, olpc-xo1-sci: Add GPE handler and ebook switch functionality
The EC in the OLPC XO-1 delivers GPE events to provide various
notifications. Add the basic code for GPE/EC event processing and
enable the ebook switch, which can be used as a wakeup source.

Signed-off-by: Daniel Drake <dsd@laptop.org>
Link: http://lkml.kernel.org/r/1309019658-1712-8-git-send-email-dsd@laptop.org
Acked-by: Andres Salomon <dilinger@queued.net>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2011-07-06 14:44:38 -07:00
Daniel Drake
bc4ecd5a5e x86, olpc: EC SCI wakeup mask functionality
Update the EC SCI masks with recent additions.

Add functions to query SCI events and set the wakeup mask, to be used by
followup patches.

Add functions to tweak an event mask used to select certain EC events as
a system wakeup source. Also add a function to determine if EC wakeup
functionality is available, as this depends on child drivers (different
for each laptop model) to configure the SCI interrupt.

Signed-off-by: Daniel Drake <dsd@laptop.org>
Link: http://lkml.kernel.org/r/1309019658-1712-7-git-send-email-dsd@laptop.org
Acked-by: Andres Salomon <dilinger@queued.net>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2011-07-06 14:44:36 -07:00
Daniel Drake
7feda8e9f3 x86, olpc: Add XO-1 SCI driver and power button control
The System Control Interrupt is used in the OLPC XO-1 to control various
features of the laptop. Add the driver base and the power button
functionality.

This driver can't be built as a module, because functionality added in
future patches means that some drivers need to know at boot-time whether
SCI-based functionality is available.

Signed-off-by: Daniel Drake <dsd@laptop.org>
Link: http://lkml.kernel.org/r/1309019658-1712-6-git-send-email-dsd@laptop.org
Acked-by: Andres Salomon <dilinger@queued.net>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2011-07-06 14:44:34 -07:00
Daniel Drake
97c4cb71c1 x86, olpc: Add XO-1 suspend/resume support
Add code needed for basic suspend/resume of the XO-1 laptop.
Based on earlier work by Jordan Crouse, Andres Salomon, and others.

This patch incorporates all earlier feedback from Thomas Gleixner. To
clarify a certain point (now more obvious in the code itself):
On resume, OpenFirmware returns execution to Linux in protected mode
with a kernel-compatible GDT already set up. The changes and
simplifications suggested have all been included.

Signed-off-by: Daniel Drake <dsd@laptop.org>
Link: http://lkml.kernel.org/r/1309019658-1712-5-git-send-email-dsd@laptop.org
Acked-by: Andres Salomon <dilinger@queued.net>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2011-07-06 14:44:32 -07:00
Daniel Drake
a3128588b3 x86, olpc: Rename olpc-xo1 to olpc-xo1-pm
Based on earlier review comments, we'll no longer try to stick all of
our XO-1 goodies in a single driver. We'll split it into a power management
driver, and an EC/SCI driver.

As a first step, rename olpc-xo1 to olpc-xo1-pm, and make it builtin
instead of modular.

Signed-off-by: Daniel Drake <dsd@laptop.org>
Link: http://lkml.kernel.org/r/1309019658-1712-4-git-send-email-dsd@laptop.org
Acked-by: Andres Salomon <dilinger@queued.net>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2011-07-06 14:44:28 -07:00
Daniel Drake
7a0d4fcf6d x86, olpc: Move CS5536-related constants to cs5535.h
Move these definitions into the relevant header file.
This was requested in the review of the upcoming XO-1 suspend/resume code.

Signed-off-by: Daniel Drake <dsd@laptop.org>
Link: http://lkml.kernel.org/r/1309019658-1712-3-git-send-email-dsd@laptop.org
Acked-by: Andres Salomon <dilinger@queued.net>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2011-07-06 14:44:23 -07:00
Daniel Drake
f70d8ef474 x86, olpc: Add missing elements to device tree
In response to new device tree code in the kernel, OLPC will start
using it for probing of certain devices. However, some firmware fixes
are needed to put the devicetree into a usable state.

Retain compatibility with old firmware by fixing up the device tree
at boot-time if it does not contain the new nodes/properties that
we need for probing. This is the same approach taken on PPC platforms.

Signed-off-by: Daniel Drake <dsd@laptop.org>
Link: http://lkml.kernel.org/r/1309019658-1712-2-git-send-email-dsd@laptop.org
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Andres Salomon <dilinger@queued.net>
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2011-07-06 14:44:19 -07:00
Rob Herring
10cdc7e512 ARM: 6960/1: allow enabling SCU code on UP
The scu_power_mode function can be used on UP builds as it drives signals
to an SOC power controller. So make it selectable for !SMP.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-07-06 20:55:15 +01:00
Will Deacon
eca5dc2a00 ARM: 6988/1: multi-cpu: remove arguments from CPU proc macros
The macros for invoking functions via the processor struct in the
MULTI_CPU case define the arguments as part of the macros, making it
impossible to take the address of those functions.

This patch removes the arguments from the macro definitions so that we
can take the address of these functions like we can for the !MULTI_CPU
case.

Reported-by: Frank Hofmann <frank.hofmann@tomtom.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-07-06 20:49:45 +01:00
Linus Walleij
f022e4e41b ARM: 6986/1: mach-realview: add TCM support for PB1176
Enable TCM support on the RealView PB1176 - we have now taken
the precautions necessary to support even multi-board builds of
RealView systems with TCM enabled.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-07-06 20:49:45 +01:00
Linus Walleij
201043f227 ARM: 6985/1: export functions to determine the presence of I/DTCM
By allowing code to detect whether DTCM or ITCM is present, code paths
involving TCM can be avoided when running on platforms that lack it.
This is good for creating single kernels across several archs, if some
of them utilize TCM but others don't.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-07-06 20:49:45 +01:00
Linus Walleij
9715efb8dc ARM: 6984/1: enhance TCM robustness
The PB11MPCore reports "3" DTCM banks, but anything above 2 is an
"undefined" value, so push this to become 0. Further add some checks
if code is compiled to TCM even if there is no D/ITCM present in the
system, and if we can really fit the compiled code. We don't do the
BUG() since it's not helpful, it's better to deal with non-present
TCM dynamically. If there is nothing compiled to the TCM and no TCM
is detected, it will now just shut up even if TCM support is enabled.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-07-06 20:49:45 +01:00
Will Deacon
38a8914f9a ARM: 6987/1: l2x0: fix disabling function to avoid deadlock
The l2x0_disable function attempts to writel with the l2x0_lock held.
This results in deadlock when the writel contains an outer_sync call
for the platform since the l2x0_lock is already held by the disable
function. A further problem is that disabling the L2 without flushing it
first can lead to the spin_lock operation becoming visible after the
spin_unlock, causing any subsequent L2 maintenance to deadlock.

This patch replaces the writel with a call to writel_relaxed in the
disabling code and adds a flush before disabling in the control
register, preventing livelock from occurring.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-07-06 20:48:08 +01:00
Petr Štetiar
186dcaa448 ARM: 6966/1: ep93xx: fix inverted RTS/DTR signals on uart1
It was discovered by Roberto Bergo, that RTS/DTR signals are inverted after
the boot, because it was causing him problems with hardware controlled modem
connected on ttyAM0. Todd Valentic came with this patch for the issue.

Discussion: http://tech.groups.yahoo.com/group/ts-7000/message/20259

Comments from Petr Štetiar:

 Sorry, but forget to add Acked-by[1]:

 1. https://patchwork.kernel.org/patch/873052/

Cc: Ryan Mallon <ryan@bluewatersys.com>
Cc: Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Todd Valentic <todd.valentic@sri.com>
Tested-by: Roberto Bergo <roberto.bergo@robson.it>
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-07-06 20:46:36 +01:00
Wolfram Sang
2eb5af44b1 ARM: 6979/1: mach-vt8500: add forgotten irq_data conversion
This platform has not been converted to 'struct irq_data' when the big
pile was done and fails to compile nowadays. Tested on a JayPC-Tablet.

Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Alexey Charkov <alchark@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-07-06 20:46:04 +01:00
Grant Likely
6eae1ace68 gpio: Move mpc5200 gpio driver to drivers/gpio
GPIO drivers are getting consolidated into drivers/gpio.  While at it,
change the driver name to mpc5200-gpio* to avoid collisions.

Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-07-06 11:57:15 -06:00
Christian Riesch
8d54297b90 davinci: da850: add a .set_rate method to ref_clk
This patch allows setting the input clock frequency of the SoC from
the board specific code using the davinci_set_refclk_rate function.

Suggested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2011-07-06 22:07:30 +05:30
Lei Wen
6662498e13 ARM: pxa168: correct nand pmu setting
The original pair of <0x01db, 208000000> is invalid. Correct it to
the valid value.

The 6th bit of the NFC APMU register indicates NFC works whether
at 156Mhz or 78Mhz. So 0x19b indicates NFC works at 156Mhz, and
0x1db indicates it works at 78Mhz.

Signed-off-by: Lei Wen <leiwen@marvell.com>
Cc: stable@kernel.org
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2011-07-06 23:51:36 +08:00
Lei Wen
d204b2c5b1 ARM: pxa910: correct nand pmu setting
The original pair of <0x01db, 208000000> is invalid.
Correct to the valid value.

Signed-off-by: Lei Wen <leiwen@marvell.com>
Cc: stable@kernel.org
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2011-07-06 23:51:22 +08:00
Paul Parsons
beb0c9b056 ARM: pxa: fix PGSR register address calculation
The file mfp-pxa2xx.c defines a macro, PGSR(), which translates a gpio
bank number to a PGSR register address. The function pxa2xx_mfp_suspend()
erroneously passed in a gpio number instead of a gpio bank number.

Signed-off-by: Paul Parsons <lost.distance@yahoo.com>
Cc: stable@kernel.org
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
2011-07-06 23:47:40 +08:00
Matthias Rosenfelder
6d999da4d2 sparc32,leon: Added __init declaration to leon_flush_needed()
The function leon_flush_needed() is called only during bootup from another
__init function. Therefore, we can also add __init to leon_flush_needed().

Signed-off-by: Matthias Rosenfelder <rosenfelder.lkml@googlemail.com>
Acked-by: Daniel Hellstrom <daniel@gaisler.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-07-06 08:01:52 -07:00
Steven Rostedt
18d85bc558 sparc/irqs: Do not trace arch_local_{*,irq_*} functions
Do not trace arch_local_save_flags(), arch_local_irq_*() and friends.
Although they are marked inline, gcc may still make a function out of
them and add it to the pool of functions that are traced by the function
tracer. This can cause undesirable results (kernel panic, triple faults,
etc).

Add the notrace notation to prevent them from ever being traced.

Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-07-06 08:00:29 -07:00