Sophgo:
Add initial support for "Duo S" Board.
This board uses SG2000(old codename CV181xH),
which is dual-arch, RISC-V and ARM64. This
patch adds the support for ARM64.
Signed-off-by: Chen Wang <chen.wang@linux.dev>
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQTYPcWJ6By3aFu8IuKHG95Quc97dgUCanJ/4wAKCRCHG95Quc97
djWDAQCHF2gqq9CdkNOCnd8S4rgJLoqcf/2ROKS013DaUU2VGwEAh/bXJz5r6mHw
m7vz8DeYqHGlsSDcAM3QhUA3Ot8zngo=
=T9De
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmp58WoACgkQmmx57+YA
GNnagA/+Ig1OuY7L+/SejZdfDmODN4Qld7LZf1P31cYn6eL6rYZL0hmC37LwlpgL
hQC1dHbpaPN4hd9Dl5I7ZEQizce9iIgOHy9Qt32yqpFNlYGcC7oM8tklJmXjMtOk
31wl4crrl8+LUhRbcGEGIcrwUfZi+mV525Q9yA+yZ5ge9TvrtlEoPduzodzLGGt6
MjRAqGKhhxFO17UeIai/ssWumnMFeO1SaUWdaEbfMB2Jg/1XMpyv33L8rydqK3wp
MgnP94DdMX4sW63+3YTMLLoDPvBWWCVYRKEfC/0OkjfuYRJNXMAE+3IzU2pOsdI3
6ykJLRYkns6fqsQpx/3faWb0gb8qq9ZGeNBpwiWKcH7ya9Ivde+4wYrEAGyn0V5e
xf+HwQEdhSetjIdKcnVcjJ90br4q4cHP2vWkSeeiVgLIXwy9TwZniO/F/fg1gX5p
qhTwXe+FJnQ4TfLIesvz0UI6i0bgjvhdRKPhpVzuFsENooceOiC+jJUvc/dsjQCV
k6s7iCNJN3+510k/afKgpczxcvHrg1YlacwQXagqs0X7thN42nRbNb0mQ+pWkgX1
y3h9Sm6OcddWGKjg1GQ52640Dn5xeacutq23GhDpZZx0tAV+z8x9hubk4Q8sDGXW
ta+BKMIS1dJ6tD5tozeCYm6QP0HuspMZ/JtW5+hlrIfYyuthVBc=
=hRBP
-----END PGP SIGNATURE-----
Merge tag 'arm-sophgo-dt-for-v7.3' of https://github.com/sophgo/linux into soc/dt
ARM Devicetrees for v7.3
Sophgo:
Add initial support for "Duo S" Board.
This board uses SG2000(old codename CV181xH),
which is dual-arch, RISC-V and ARM64. This
patch adds the support for ARM64.
Signed-off-by: Chen Wang <chen.wang@linux.dev>
* tag 'arm-sophgo-dt-for-v7.3' of https://github.com/sophgo/linux:
arm64: dts: sophgo: add initial Milk-V Duo S board support
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Sophgo:
The changes of this PR are all for CV18xx serials.
There are three major changes. The first is to allow
DMA multiplexer setting channel number for DMA controller;
the second is to add initial RISC-V support for "Duo S"
board, which uses SG2000, a dual-arch SoC (RISC-V and
ARM64); the third is to add support for "Duo 256M"
board, another dev-board based on SG2002 SoC.
Signed-off-by: Chen Wang <chen.wang@linux.dev>
-----BEGIN PGP SIGNATURE-----
iHUEABYKAB0WIQTYPcWJ6By3aFu8IuKHG95Quc97dgUCanKEvQAKCRCHG95Quc97
dn44AP9HHp2ut8rY0UnmS/s+rCAbWX/2YkhGWdWPPk1o4VkSdQEArt9F9RpXg/Mp
RfmT/LEx81g7zR7wqpGlpy1a5F+TBw4=
=SAg0
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmp57JAACgkQmmx57+YA
GNla7xAAqMRFdMgCOH74zaNtohonnSgbmJi4dL6RakzJHCjZO+VWMnxavg/A8qTb
DrSugeW0SV1pe/NbOKaJbqZ6xa/gJJitivPNJIgn8uM3WauetzE55isGPb+smR1r
soqTG/3AYocT88fy7FgLL3GmvY9yd1dAOHA/CFdTpmBdrqfV5fSSmed08wM0lVQe
O1EgjHe7eNk+v3DYo80buRxwljiW0gpbhFFsz84hbdFoL/Cf/GAXWP1xhZjCTKo1
9/Zex3J7SsdNAaZjDzMyF0S0eolyAPJW0SzToDkMniE/tSYc2lkjW7R1I55iuQvi
BJ+kKK1k2/TrSbmvjuvqCEnwfOh9BzXPf4UWuLrUrEVTpdEBtpe0otFGRBqzg0lO
RkgUPdHWR8uhL57Oos8HM4WH2VN4s0jqP0FN1sUp46fnnQFCEi/nO4vRTnOt+ppy
HxNjJyQRrP97OH7s7zpUTyCVVJBZPL3EF3NuNCzioooXK3LHI4MSApTtDIt9bPBi
yS5U1SaUaNm4RwCaFH9QZSQHXdoEXKe0DPX/P9cROr62T6eSyDhZnIIcucveMw+6
tJie38mJChficq8mCo3/S1P3gMELy5lmBw68XCg/UMBcdV76Mq4AgFq6o5Ow+oXp
KS/sO+RkxZPD7ImnGLKrSuurJnIsMpOR/69lLFBkZ0LBtdZY9W4=
=CrHg
-----END PGP SIGNATURE-----
Merge tag 'riscv-sophgo-dt-for-v7.3' of https://github.com/sophgo/linux into soc/dt
RISC-V Devicetrees for v7.3
Sophgo:
The changes of this PR are all for CV18xx serials.
There are three major changes. The first is to allow
DMA multiplexer setting channel number for DMA controller;
the second is to add initial RISC-V support for "Duo S"
board, which uses SG2000, a dual-arch SoC (RISC-V and
ARM64); the third is to add support for "Duo 256M"
board, another dev-board based on SG2002 SoC.
Signed-off-by: Chen Wang <chen.wang@linux.dev>
* tag 'riscv-sophgo-dt-for-v7.3' of https://github.com/sophgo/linux:
riscv: dts: sophgo: Add Milk-V Duo 256M board support
riscv: dts: sophgo: cv180x: Add PWR_GPIO controller
dt-bindings: soc: sophgo: add Milk-V Duo 256M board
riscv64: dts: sophgo: add initial Milk-V Duo S board support
riscv64: dts: sophgo: add SG2000 dtsi
riscv: dts: sophgo: cv180x: Allow the DMA multiplexer to set channel number for DMA controller
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Any new DTS code should pass dt-check-style 'relaxed' mode without
warnings and should have addressed most of applicable 'strict' mode
ones.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Link: https://lore.kernel.org/r/20260803091740.232536-2-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This contains a new device tree for the Lenove ThinkEdge SE70 Edge
Client device as well as a number of fixes and cleanups for Tegra234 and
Tegra194. Tegra264 sees a number of additions to enable more features.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmpvcb8ACgkQ3SOs138+
s6EVRg//e3keeg7ehCUFVA8mDnGfxtIR5ErkU0I5LkCaQucREvHveHuNSayiNSM0
DQVcqv3n/egea4Nnon+eH4ddpa0fosFUm0tW1agLdvhn41nKhiTg/vNcPUwqNE+p
qw43rl5ecChZslW8l8+4eln9sRoTnxBKKlydu5aKKVQtpLbn23uZTwtlSwMWcduO
0GjNOpvrjNyLWzGQ6lrO7uxRxrTHJPYm68Y/sVt38tZYHKC/Ksosy1/o0fKwJd4Q
kMfk2lu1DxY6LGihNmNgpoITva0EaxtwDN1I4IO+dWLNq+feOrwCdTIaanycQPSw
29COUfEcpblWvkRxd6ffWLwsAEk1ydR49FaJLgaAddb0ImEJfEeiaz8roAMqW24Q
QEEDtSwg8JeC4dhWSgOqPOin328hiz3gEG3qYkP/Bi9NgCq2a0eVRlWfBOkgPI8u
isGcVm1yfb2cxdgC26QWivLtuTxDNeHp/rcyGAinWrzd5FJFMvd/tn76inOS33X1
U4shiIvnYDMh0j1VkvHa2ZvN1lqOTmbAGqHOF0iuCC2fhHuu6VW3/7j7wYgtv4gP
Mp2dfVWEdj1Yp+iedS63XN+rFnEqMqw2733TkI1ThLzF3PXz0BO73QMvY+qAujlV
8eLPr5091lXQKYCKCLx8AGBpLtXOFHzS1BxR/tr+OPWAutGFoXA=
=qSTk
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-7.3-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
arm64: tegra: Device tree changes for v7.3-rc1
This contains a new device tree for the Lenove ThinkEdge SE70 Edge
Client device as well as a number of fixes and cleanups for Tegra234 and
Tegra194. Tegra264 sees a number of additions to enable more features.
* tag 'tegra-for-7.3-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (1469 commits)
arm64: tegra: Correct Tegra234 p3740 interrupt flags
arm64: tegra: Correct Tegra234 p3737 interrupt flags
arm64: tegra: Correct Tegra194 p2972 interrupt flags
arm64: tegra: Drop CPU masks from GICv3 PPI interrupts
arm64: tegra: Add Lenovo ThinkEdge SE70 device tree
arm64: tegra: Add pinctrl nodes for Tegra264
arm64: tegra: Fix CMDQV interrupt type on Tegra264
arm64: tegra: Properly sort devices on Tegra264
arm64: tegra: Add GTE nodes for Tegra264
arm64: tegra: Add Host1x and VIC on Tegra264
arm64: tegra: Populate CPU and L2 cache nodes on Tegra264
arm64: tegra: Enable GPCDMA in Tegra264 and add iommu-map
Linux 7.2-rc5
super: fix emergency thaw deadlock on frozen block devices
tracing: perf: Fix stale head for perf syscall tracing
ftrace: Add global mutex to serialize trace_parser access
tracing: Delay module ref count for "enable_event" trigger
tracing: Fix use-after-free freeing trigger private data
bpf, sockmap: Fix cork use-after-free in tcp_bpf_sendmsg()
tracing: Fix context switch counter truncation
...
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This contains a few fixes for interrupt types and email addresses as
well as the addition of a compatible string for the Lenovo ThinkEdge
SE70 Edge Client.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmpvcBUACgkQ3SOs138+
s6FsAg/+MbBZhYQm08PBRJAvwOuC+3Uny4nBxPDheAyqYmi0pa7a6Az36k1ub5B2
UgXrk32x+yfhGvmSkg/bKsiSvKo9SjKz0hUY4hWOMCeursbNDdv2BcYxLwx291wu
KETB3obUsGRhn3yqcQA6b/8iJOBluDDpdkZh85AT++Ss+akspCt4LeCQnXDxdtK3
aEG0lb8Q63TC0uW0a0Qg5+xh9HH7hNZN8S0giWP0OCi0+V9JNyPWEfVAFdqLaQbH
bcv1udPTKYhvXemNumerMzNXtxPJTBlOTJwugyCgv7rMGRsntk54UTDqc4w6yRen
T9Zf3v9ScMQ+OXpdhicdFffeNC2tky9fruTE8Vjs7Oeif2AtaqYI8wMndyMKvQl5
h4Q1uwAJeX2Wjj+5DxLQ/ets4OGb0GvXw8xdELfQ1R35YKd97eHMXqpgdwFtb5PW
UecGlSly515zL43a7z/ROF33aG4Cbr3DZJANRNfqlo5oDuHWyS53q+jNklq0nhid
t29eMhaB9sh8NGOgs4hHY67vMwvYHDDAUDSp66AcQFVuPkJdf8Mrw8MSaXhcqqW+
Tkn2w/ilrYTn7ZXr1CPqmSHezlr77ky/cmusBoSp2NX1LVCQPkonQAOrj1Pzd6mI
vTGy7U6zj6dbXw1yZTAtBzzBJY6WwTxHsKAxW98uvr7kupbC89Y=
=q7gO
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-7.3-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
dt-bindings: Changes for v7.3-rc1
This contains a few fixes for interrupt types and email addresses as
well as the addition of a compatible string for the Lenovo ThinkEdge
SE70 Edge Client.
* tag 'tegra-for-7.3-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: arm: tegra: Add lenovo,thinkedge-se70 compatible string
dt-bindings: gpu: host1x: Fix email address
dt-bindings: iommu: Fix interrupt type in example
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
No significant changes this time around. Instead, several cleanups
for Meta's San Miguel platform, along with some changes enabling
dt-check-style.
-----BEGIN PGP SIGNATURE-----
iJIEABYKADoWIQSoUT1x3bOSX/nAa8ajM9GZTrjhpgUCanF5jhwcYW5kcmV3QGNv
ZGVjb25zdHJ1Y3QuY29tLmF1AAoJEKMz0ZlOuOGmKM4BAIn485+eqqhirbu9AlZ1
vR71X3FozVRs9a5AJkl2ZLQaAPsE5mLKHPBv9b7tQNTjtweWg+ZzSW+dSwi6fvaT
T5lTAA==
=wBKd
-----END PGP SIGNATURE-----
Merge tag 'aspeed-arm-7.3-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
aspeed: First batch of ARM devicetree changes for 7.3
No significant changes this time around. Instead, several cleanups
for Meta's San Miguel platform, along with some changes enabling
dt-check-style.
* tag 'aspeed-arm-7.3-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux:
ARM: dts: aspeed: Correct indentation
ARM: dts: aspeed: sanmiguel: fix PDB HSC shunt resistor
ARM: dts: aspeed: sanmiguel: Fix PWRGD_RMC_N active-low hog configuration
ARM: dts: aspeed: sanmiguel: Fix FIO IOEXP interrupt pin
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Similar to the 7.3 ARM PR for Nuvoton we have a couple of arm64 tidy-ups
from Tomer.
-----BEGIN PGP SIGNATURE-----
iJIEABYKADoWIQSoUT1x3bOSX/nAa8ajM9GZTrjhpgUCanF2rxwcYW5kcmV3QGNv
ZGVjb25zdHJ1Y3QuY29tLmF1AAoJEKMz0ZlOuOGm7RQBAITiQe5Y+lq06iGFVoCK
uMGOoT2dJ8l7nb/vB+Wq7wcHAQCc+8HzdiIYwg4mAUdu9KBYTa45ENMmc7xCz2ro
lgZQDQ==
=X0Sh
-----END PGP SIGNATURE-----
Merge tag 'nuvoton-arm64-7.3-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
nuvoton: First batch of arm64 devicetree changes for 7.3
Similar to the 7.3 ARM PR for Nuvoton we have a couple of arm64 tidy-ups
from Tomer.
* tag 'nuvoton-arm64-7.3-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux:
arm64: dts: nuvoton: npcm845: Reorder timer0 and PECI nodes
arm64: dts: nuvoton: npcm845: Drop redundant timer clock-names
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This time around we have a couple of cleanups from Tomer that make way for
improvements in the bindings.
-----BEGIN PGP SIGNATURE-----
iJIEABYKADoWIQSoUT1x3bOSX/nAa8ajM9GZTrjhpgUCanFyrBwcYW5kcmV3QGNv
ZGVjb25zdHJ1Y3QuY29tLmF1AAoJEKMz0ZlOuOGmUpYA/RIAIMzFmJ7AAIGeVq6i
Obc906cAt8/t5yazfSno0yT9AQCiNUJCJD28vD1PMglfSGyu+cvhjMI/va/SE021
8s9cDA==
=kqlH
-----END PGP SIGNATURE-----
Merge tag 'nuvoton-arm-7.3-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
nuvoton: First batch of ARM devicetree changes for 7.3
This time around we have a couple of cleanups from Tomer that make way for
improvements in the bindings.
* tag 'nuvoton-arm-7.3-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux:
arm: dts: nuvoton: npcm7xx: Drop redundant FIU clock-names
arm: dts: nuvoton: npcm7xx: Drop bogus FIU memory reg-names
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
- DT support for PRU-ICSS on AM3/4/5
- minor fixes & cleanups
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAmpwuDQACgkQWTcYmtP7
xmXGtA//ROU+70rWugsXkpzQdwPpJDaB7SlGJTzdqX0Nic9BKFv2h2mu4VH+7qLp
ydLVpY2t6eEgolAfNjUQ2MXNl3qK/QMiIjNGgURHlpAl90YeXlST2bOo7kXDMLgG
9mlOVZyN2Wx5FEUN66ezlvcnTXjQP8vC2kXT4ya+a7ZQ6PL28UwfisD16Fs98gGk
m2IgRPPCmCn1o+A2rQ+H+DBwW7p/1oe7t9r2xcFusDmQXx4f8XoghwK0Z5t+qVkk
cDDI7poHBAty+sR0jKY6qa62kXnybig/yZeGQrUIX1F+BOivs+Ko7gUiqMYyO5bl
AFcsf0LDS+OLa1bhw1Mcua2/03cELYQSxKZQiSVAo9/Bel4tXaYn3WWzH3e2Lw1F
2n+OAGfLWHAz7bIj3VfaurG3JUYNFUWqD6oe7PniaGFDg6EinU9ibwYIFtVT9ZB2
Iug4/9TUzcLONnMjvgz2D5ooUcEx62aIYRPsT9AOX4SjOY+rM/+3Wtg8VZzPKClb
deUTvUPLQg1bucWj2RRV0/x56Jae3k4MypZeiXtK5RT+YUrWeNcHzwAqAnhvKglr
wpUw6KU39oXF5o7neUk07A41vRuPh6+TP1nebZlPhB/7yjgjyQg2xFT4Fr+A+v1y
43MAyEgZnxjNrF0UXrdTU3xvVx3b41Q1TXgflyAPwWV82+hHDaI=
=PThB
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v7.3/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/dt
ARM: dts: OMAP updates for v7.3
- DT support for PRU-ICSS on AM3/4/5
- minor fixes & cleanups
* tag 'omap-for-v7.3/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap:
ARM: dts: ti/omap: embt2ws: use mulit-led for RGB LED
ARM: dts: ti: omap: Correct indentation
ARM: dts: ti: Fix typos in comments
ARM: dts: ti: Add specific compatibles for SCM conf nodes
arm: dts: ti: Add device tree support for PRU-ICSS on AM335x
arm: dts: ti: Add device tree support for PRU-ICSS on AM437x
arm: dts: ti: Add device tree support for PRU-ICSS on AM57xx
ARM: dts: ti: var-som-om44: Add USB Ethernet controller node
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
For K3 SoC
- Enable SD card support
- Enable QSPI
- Fix reset delay of ETH PHY
- Fix PHY ID of ETH
- Symbolic PDAM ID
- Add SPI controller support
- Add USB and PHY support
- Add I2S nodes
For K1 SoC
- Symbolic PDAM ID
- Enable cpufreq support
- Fix max CPU core voltage
For boards of K3
- Pico-ITX
- Enable ALDPS on RTL8211F PHY
- Disable 125MHz clock on RTL8211F PHY
- Enable NOR flash
- Add EEPROM support
- CoM260
- Add EEPROM support
For boards of K1
- Milk-V Jupiter
- Enable CPU DVFS
- Banana Pi BPI-CM6
- Add initial support
- OrangePi R2S
- Enable PCIe
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQKvBAABCgCZFiEEtbq4ycMbcRVnAiPcMarqR1lNu+0FAmpupawbFIAAAAAABAAO
bWFudTIsMi41KzEuMTIsMiwyXxSAAAAAAC4AKGlzc3Vlci1mcHJAbm90YXRpb25z
Lm9wZW5wZ3AuZmlmdGhob3JzZW1hbi5uZXRCNUJBQjhDOUMzMUI3MTE1NjcwMjIz
REMzMUFBRUE0NzU5NERCQkVEAAoJEDGq6kdZTbvtuDgP/0+IIPDo/U7U0IhT+dAx
Mxr1fWX1M4h5nEmirD8Zsx8TSfvZrpZr5MvazjrHxZ5U2U4ntkqrcoByhIqEy6Dn
wz3A8arOEe3BU1zXf4UAPAW0CZA3Bp9rEDgwbgsTfyelSLyeDqaMX8l/8XQLU8Sl
f28L5p+5AQota4Cutl36yE/KP6cK+7SBSgXA2Rnb9SXzvwC9cQGuOUq71zUsS7jI
FdpYcvyCbLFmUiq2XoeFAdGB04nYs28VWiFnHg7FNdrCqWH6pgi/zxd3QtlTxjd6
oIrp/NsBnx9WAyx9GDhckpqOLt+sA49BjMTArBHmytVBI0ku2kbueQXJIS2J2OEq
Cj4jkMD36Mbk21UP/3OOohARxPYWDDsRQ6NzvAMqNnmFdGa2lTCGA2pBsXF6pzYA
cgFoSQq3s37ArNWaFxeCgnAnzyUWtEUEA3wcp+04xh4s9a90khxuU/rpF+GuyZwp
5Bfppy9L9dI6BogmfAcMsVHcLd0UhDoC6nokx8QLCtrVKEnpvWHfAtWProzEINfX
k9K+f+fLtvL4aWGevKfZZfbMwFRrDaARI03HqW/flUjLBVggoC2FFo63WOfEmvZr
ldCmIWM2iDgr7gBTSy8FSX+3FNROyc2xDFhM189crVvK0+LCCMyqGhHFNnk6NYbU
NRf7S+rwIN9yrBSUgrX6GCXs
=WKqT
-----END PGP SIGNATURE-----
Merge tag 'spacemit-dt-for-7.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/spacemit/linux into soc/dt
RISC-V SpacemiT DT changes for 7.3
For K3 SoC
- Enable SD card support
- Enable QSPI
- Fix reset delay of ETH PHY
- Fix PHY ID of ETH
- Symbolic PDAM ID
- Add SPI controller support
- Add USB and PHY support
- Add I2S nodes
For K1 SoC
- Symbolic PDAM ID
- Enable cpufreq support
- Fix max CPU core voltage
For boards of K3
- Pico-ITX
- Enable ALDPS on RTL8211F PHY
- Disable 125MHz clock on RTL8211F PHY
- Enable NOR flash
- Add EEPROM support
- CoM260
- Add EEPROM support
For boards of K1
- Milk-V Jupiter
- Enable CPU DVFS
- Banana Pi BPI-CM6
- Add initial support
- OrangePi R2S
- Enable PCIe
* tag 'spacemit-dt-for-7.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/spacemit/linux: (33 commits)
riscv: dts: spacemit: Add cpu scaling for Milk-V Jupiter
riscv: dts: spacemit: k1-bananapi-cm6: fix maximum CPU core voltage
riscv: dts: spacemit: k1-orangepi-r2s: fix maximum CPU core voltage
riscv: dts: spacemit: k1-musepi-pro: fix maximum CPU core voltage
riscv: dts: spacemit: k1-orangepi-rv2: fix maximum CPU core voltage
riscv: dts: spacemit: k1-milkv-jupiter: fix maximum CPU core voltage
riscv: dts: spacemit: k1-bananapi-f3: fix maximum CPU core voltage
riscv: dts: spacemit: Make dtschema recognize the etherent PHY correctly on K3 com260 board
riscv: dts: spacemit: Make dtschema recognize the etherent PHY correctly on K3 pico-itx board
riscv: dts: spacemit: k3: add i2s0-i2s5 nodes
riscv: dts: spacemit: k3: add USB controller and USB phy support
riscv: dts: spacemit: enable PCIe on OrangePi R2S
riscv: dts: spacemit: k3-com260-ifx: add eeprom on i2c1
riscv: dts: spacemit: k3-com260: add eeprom on i2c2
riscv: dts: spacemit: add SPI controllers for K3
riscv: dts: spacemit: add K3 PDMA request numbers
riscv: dts: spacemit: Fix phy id check for the phy on com260 board
riscv: dts: spacemit: Fix phy id check for the phy on pico-itx board
riscv: dts: spacemit: Add enough deassert time for the PHY on com260 board
riscv: dts: spacemit: Add enough deassert time for the PHY on PICO ITX
...
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Orange Pi 5 Pro, Vicharak Axon, Vicharak Vaaman2, Youyeetoo YY3588
New peripherals: eDP support on RK3576
And of course a number of board-fixes, style-fixes and some newly
enabled board-components.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmptHIQQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgc0AB/9BaMz8DtfWjjLRIQTBoIHDCeflNPO/deS0
Gea4KkofOsLapsflB4WvVs9HAxJfX43LE4xFFqQn947wiFVDA7xV9Z1T9V3DkxiE
5GnvrjYbfDGBtYeAJZmYm3Lq2AA7HeIVAQhgOXEow+6MH5GmG3SRWg8aBplNQC0K
pPvLc+AdFyQCLlVVf12iVOeViIZejIEXYGDuofa8euTEUjZxNSlqvxfX/YF5uE2K
1ycQX6MwNLA7x1Gx4GXCytgt+oKTtl42NAQLeIHYwJyinnMd2JY8RrDQBBozENZf
YQVWUE53W7W/9OWsLptfjLN5Jya9iMVxMXcsGRvtNe44SyyGnCT3
=0Vz9
-----END PGP SIGNATURE-----
Merge tag 'v7.3-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
New boards: Graperain G3568, HINLINK H28K, LCKFB Taishan Pi 3M,
Orange Pi 5 Pro, Vicharak Axon, Vicharak Vaaman2, Youyeetoo YY3588
New peripherals: eDP support on RK3576
And of course a number of board-fixes, style-fixes and some newly
enabled board-components.
* tag 'v7.3-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (39 commits)
arm64: dts: rockchip: Fix rk3566-bigtreetech-cb2 touchscreen property
arm64: dts: rockchip: fix label of sys_led for nanopi-r4s
arm64: dts: rockchip: Fix the rk3566-radxa-cm3 Wifi compatible
arm64: dts: rockchip: Fix Gru WLAN sideband interrupt
arm64: dts: rockchip: Add Vicharak Vaaman2 board
dt-bindings: arm: rockchip: Add Vicharak Vaaman2
arm64: dts: rockchip: add Vicharak Axon board
dt-bindings: arm: rockchip: add Vicharak Axon board
arm64: dts: rockchip: Add LCKFB Taishan Pi 3M
dt-bindings: arm: rockchip: Add LCKFB Taishan Pi 3M
arm64: dts: rockchip: Add Orange Pi 5 Pro board support
arm64: dts: rockchip: refactor items from Orange Pi 5/b to prep for Pro
arm64: dts: rockchip: rename PLDO regulator labels to match schematic on rk3588s-orangepi-5
dt-bindings: arm: rockchip: Add Orange Pi 5 Pro
arm64: dts: rockchip: Add devicetree for the Graperain G3568 v2
dt-bindings: arm: rockchip: Add Graperain G3568 series
dt-bindings: vendor-prefixes: Add graperain
Revert "arm64: dts: rockchip: Further describe the WiFi for the Pinephone Pro"
arm64: dts: rockchip: fix HDMI-RX signal detect GPIO on yy3588
arm64: dts: rockchip: Enable USB device mode on rk3588s-roc-pc
...
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Introduce DeviceTree support for the Shikra SoC, its GCC and RPM clock
controllers, CQM, CQS, and IQS SoM platforms, and their evaluation boards.
Document the Hawi and Maili SoCs.
Add the Eliza CQS SoM and EVK platforms, the QCS8550 RB5 Gen 2, Vicharak
Axon Mini, HONOR MagicBook Art 14, Microsoft Surface Pro 12, Xiaomi 12 Lite,
Motorola Edge 30, Sony Xperia M2, and Motorola Moto G2 device trees.
Extend Eliza support with USB, SD card, touchscreen, PMIC, interconnect,
thermal, CPU and LLCC bandwidth-monitor, QUPv3, and ADSP GPR descriptions.
Expand Glymur support with GPU, camera and EVA clock controllers, LPASS
audio, CoreSight, PCIe, USB, IMEM and PIL memory regions, power domains,
thermal cooling, and CRD peripherals. Add SoCCP, PMIC regulator, TRNG, and
CPU-capacity descriptions.
Add display, IPA, camera, USB, audio, crypto, TRNG, CoreSight, and thermal
support to the Kaanapali, Milos, Hamoa, and related platforms. Add embedded
controller support for Hamoa and Glymur boards.
Improve networking-platform descriptions with IPQ PCIe port, PHY, clock,
PWM, regulator, and interrupt updates. Update CTCU, display, Iris, audio,
camera, PCIe, USB-C, power-domain, memory-region, and thermal descriptions
across established Qualcomm platforms.
Correct bindings and DeviceTree validation for Qualcomm compatible strings,
legacy fallback compatibles, node naming and formatting, address ranges,
clock specifiers, reserved memory, regulators, GPIOs, and peripheral wiring.
-----BEGIN PGP SIGNATURE-----
iQJCBAABCgAsFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmprfucOHGJqb3JuQGty
eW8uc2UACgkQCx85Pw2ZrcVSexAAkUYQzdf+LbI2LXMUwhASxt0BcCGFUMnBzi1G
B6QXIP/3H6ucb/QXhYAfghuSrd6SPWCmCueS+FiMJst+eEiuvSDPkPiGyMAWs3kM
fuQbxSWc1VcAgVCbjABrCHSptmJRU+poRent3raLqgCQJ3oip78mnn3p3SEcv4rg
HK4TyjF5EWjzZo6sQWYuS6F3zAeu5Az5ft83Qjd/87PnFYl3A5Y8ZJMleT1o9yi0
eqwBh2XlyMHVZB83Bm6kIRfDFQ+q6CjB/CNCjrjfdXQeKbkYNMnEF3NywIDckPDC
L6O1kTuld3L25koRRfMeHq8bWpOTEWLq4UCqvpEVpj352eZPAgFYfd0zudVhjLQP
CPmoq+5quRbltq7VxO2x7LWz6vzgrrRevC9n3Eyj6uBioCo+JpcMTns/zDGDrzm/
dl43YwGcOI0+U3m3GXJ9567T9zIEA8CzuOd3tHcmTxGmxMU2y313cwfHqgbqy6K6
NLzToYYPclB6aC44yqBPjOhkP653atqDc6qhhMCix7swoTEUqs780fH/G7X6ammY
9XgUM/pxB3dB37dqy8fBBha0TdQ6dQm25DAN2TULgKcolFzHo+O2vd4jR4KpU2eg
3L+pdMUZgF0bvrlqpR9Q8z2TYpIkL/Z5Tc/eEdI6WWF9YXF0TV+iI/7U6S/a+ZJi
gfrBpeo=
=ZLfL
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm Arm64 DeviceTree updates for v7.3
Introduce DeviceTree support for the Shikra SoC, its GCC and RPM clock
controllers, CQM, CQS, and IQS SoM platforms, and their evaluation boards.
Document the Hawi and Maili SoCs.
Add the Eliza CQS SoM and EVK platforms, the QCS8550 RB5 Gen 2, Vicharak
Axon Mini, HONOR MagicBook Art 14, Microsoft Surface Pro 12, Xiaomi 12 Lite,
Motorola Edge 30, Sony Xperia M2, and Motorola Moto G2 device trees.
Extend Eliza support with USB, SD card, touchscreen, PMIC, interconnect,
thermal, CPU and LLCC bandwidth-monitor, QUPv3, and ADSP GPR descriptions.
Expand Glymur support with GPU, camera and EVA clock controllers, LPASS
audio, CoreSight, PCIe, USB, IMEM and PIL memory regions, power domains,
thermal cooling, and CRD peripherals. Add SoCCP, PMIC regulator, TRNG, and
CPU-capacity descriptions.
Add display, IPA, camera, USB, audio, crypto, TRNG, CoreSight, and thermal
support to the Kaanapali, Milos, Hamoa, and related platforms. Add embedded
controller support for Hamoa and Glymur boards.
Improve networking-platform descriptions with IPQ PCIe port, PHY, clock,
PWM, regulator, and interrupt updates. Update CTCU, display, Iris, audio,
camera, PCIe, USB-C, power-domain, memory-region, and thermal descriptions
across established Qualcomm platforms.
Correct bindings and DeviceTree validation for Qualcomm compatible strings,
legacy fallback compatibles, node naming and formatting, address ranges,
clock specifiers, reserved memory, regulators, GPIOs, and peripheral wiring.
* tag 'qcom-arm64-for-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (244 commits)
arm64: dts: qcom: eliza: Describe the ADSP GPR node
arm64: dts: qcom: eliza-evk: Add support for USB and SD card
dt-bindings: arm: qcom-soc: Allow WSA88xx speaker compatible
dt-bindings: arm: qcom-soc: Validate nodes with fallbacks
dt-bindings: arm: qcom-soc: Document more of existing legacy style compatibles
dt-bindings: arm: qcom-soc: Include Eliza, Kaanapali and others in SoC names
arm64: dts: qcom: eliza: Enable cpufreq cooling devices
arm64: dts: qcom: glymur: add SoCCP DT node
arm64: dts: qcom: glymur: fix SoCCP memory mappings
arm64: dts: qcom: mahua: Add QREF regulator supplies to TCSR
arm64: dts: qcom: glymur: Add QREF regulator supplies to TCSR
arm64: dts: qcom: glymur: Add CX power domain to GCC
arm64: dts: qcom: glymur: Drop fake PCIe phy 3B
arm64: dts: qcom: glymur: add TRNG node
arm64: dts: qcom: glymur: enable ETR and CTCU devices
arm64: dts: qcom: glymur: Add PCIe port compatibles and ports
arm64: dts: qcom: smb2370: Disable SMB2370_2 by default
arm64: dts: qcom: eliza-mtp: Enable touchscreen
arm64: dts: qcom: purwa-iot-som: enable video
arm64: dts: qcom: purwa: Override Iris clocks and operating points
...
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
The Milk-V Duo 256M is a small form factor development board based on
the Sophgo SG2002 SoC.
This patch adds basic device tree support for the board, including:
- UART console
- SD/MMC controller
- USB host
- Onboard blue status LED (connected to PWR_GPIO[2] / porte 2)
Tested on actual Milk-V Duo 256M hardware, verified boot to shell and
heartbeat LED functionality.
Signed-off-by: Chen-Yu Yeh <chenyou910331@gmail.com>
Link: https://patch.msgid.link/20260725175346.139173-4-chenyou910331@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <chen.wang@linux.dev>
The CV180x/CV181x family has an additional DesignWare APB GPIO
controller (PWR_GPIO) located in the always-on power domain at
0x5021000. Add the node so that boards can reference GPIOs in this
bank, such as status LEDs.
Signed-off-by: Chen-Yu Yeh <chenyou910331@gmail.com>
Link: https://patch.msgid.link/20260725175346.139173-3-chenyou910331@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <chen.wang@linux.dev>
Change the DMA controller compatible to the sophgo,cv1800b-axi-dma,
which supports setting DMA channel number in DMA phandle args.
This dts change does not break backward compatibility as a fallback
compatiable string is added.
Fixes: 514951a81a ("riscv: dts: sophgo: cv18xx: add DMA controller")
Reported-by: Anton D. Stavinskii <stavinsky@gmail.com>
Closes: https://github.com/sophgo/linux/issues/9
Tested-by: Anton D. Stavinskii <stavinsky@gmail.com>
Link: https://patch.msgid.link/20260511063818.463877-3-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <chen.wang@linux.dev>
Correct a few white-space issues, like missing space before bracket '{'
character or spurious space, which will be flagged by dt-check-style
("redundant-whitespace" warning). No functional changes.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260801210450.384087-4-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
Correct a few white-space issues, like double before bracket '{'
character, which will be flagged by dt-check-style
("redundant-whitespace" warning). No functional changes.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260801210450.384087-3-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
GPIO_ACTIVE_x flags are not correct in the context of interrupt flags.
These are simple defines so they could be used in DTS but they will not
have the same meaning:
1. GPIO_ACTIVE_HIGH = 0 => IRQ_TYPE_NONE
2. GPIO_ACTIVE_LOW = 1 => IRQ_TYPE_EDGE_RISING
Realtek RT5640 codec driver requests interrupt on rising edge, so correct
the interrupt flags, assuming the author of the code wanted the similar
logical behavior behind the name "ACTIVE_xxx", this is:
ACTIVE_HIGH => IRQ_TYPE_EDGE_RISING
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
GPIO_ACTIVE_x flags are not correct in the context of interrupt flags.
These are simple defines so they could be used in DTS but they will not
have the same meaning:
1. GPIO_ACTIVE_HIGH = 0 => IRQ_TYPE_NONE
2. GPIO_ACTIVE_LOW = 1 => IRQ_TYPE_EDGE_RISING
Realtek RT5640 codec driver requests interrupt on rising edge, so correct
the interrupt flags, assuming the author of the code wanted the similar
logical behavior behind the name "ACTIVE_xxx", this is:
ACTIVE_HIGH => IRQ_TYPE_EDGE_RISING
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
GPIO_ACTIVE_x flags are not correct in the context of interrupt flags.
These are simple defines so they could be used in DTS but they will not
have the same meaning:
1. GPIO_ACTIVE_HIGH = 0 => IRQ_TYPE_NONE
2. GPIO_ACTIVE_LOW = 1 => IRQ_TYPE_EDGE_RISING
Realtek RT5658 codec driver requests interrupt on both edges, so correct
the interrupt flags, assuming the author of the code wanted the similar
logical behavior behind the name "ACTIVE_xxx", this is:
ACTIVE_HIGH => IRQ_TYPE_EDGE_RISING
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Unlike older GIC variants, the GICv3 DT bindings do not support
specifying a CPU mask in PPI interrupt specifiers. Drop the masks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add initial device tree support for the Lenovo ThinkEdge SE70, an
industrial edge gateway based on the NVIDIA Jetson Xavier NX module
(P3668-0001) with a custom carrier board.
This initial submission includes:
- 40-pin expansion header pinmux configuration
- External Micro SD card slot with dedicated 3.3V regulator
- I2C bus for 40-pin header
Static verification passed: dt_binding_check and dtbs compilation
complete without errors.
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Jiqi Li <lijq9@lenovo.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the three pin controller (MAIN, UPHY, AON) device-tree nodes found on
Tegra264.
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The CMDQV interrupts on Tegra264 are described as level-triggered, but
per the hardware interrupt documentation these interrupts are actually
edge-triggered.
Correct the interrupt type for all CMDQV nodes from IRQ_TYPE_LEVEL_HIGH
to IRQ_TYPE_EDGE_RISING.
Fixes: fe57d0ac48 ("arm64: tegra: Add nodes for CMDQV")
Reported-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
We always sort by unit-address and fallback to alphanumeric sorting for
nodes that don't have a unit-address.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra264 has a host1x instance with a VIC (video image compositor).
Other multimedia engines have moved outside host1x. Stream IDs are
now namespaced by device rather than being defined globally --
however, the only engine we have using context isolation is VIC so
we only define VIC's range of context devices.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the remaining 12 CPU nodes and all 14 L2 cache nodes for the
Tegra264 CPU Complex, which comprises up to 14 ARM Neoverse V3AE
CPUs. Each CPU has its own private 1MB L2 cache.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Enable GPCDMA in Tegra264 and add the iommu-map property so that each
channel uses a separate stream ID and gets its own IOMMU domain for
memory.
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Lenovo ThinkEdge SE70 is a fanless industrial edge gateway carrier
board based on NVIDIA Tegra194 (Xavier NX) SOM.
Add the corresponding compatible string for device tree validation.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Jiqi Li <lijq9@lenovo.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This adds a couple of fixes and improvements for multiple
MediaTek SoCs.
In particular:
- Indentation/whitespace fixes for some devicetrees
- Documentation improvements for MediaTek Mute-X
- dtbs-check warnings fixes
- MT8390 Tungsten boards: removal of unnecessary cells
- MT6795 SoC: removal of deprecated property in UART DMA
- MT6359 PMIC's RTC now uses the correct compatible string
- MT8183/86/88/92/95 SoCs gain support for the UART DMA IPs
- MT8186 gets a new CCI OPP table to resolve lockups
- MT8188/83 Chromebooks now got the correct SPI NOR supply
- MT8192 Asurada drops support for the (unused) MMC1 port
- MediaTek Genio 510/700/1200 EVKs and Radxa NIO-12L now get
their PMIC power input tree completed with assignment of
the correct supplies
-----BEGIN PGP SIGNATURE-----
iLoEABYKAGIWIQQn3Xxr56ypAcSHzXSaNgTPrZeEeAUCamsKqBsUgAAAAAAEAA5t
YW51MiwyLjUrMS4xMiwyLDIoHGFuZ2Vsb2dpb2FjY2hpbm8uZGVscmVnbm9AY29s
bGFib3JhLmNvbQAKCRCaNgTPrZeEeMdDAP49I6x+l77XLzg/PRjbNu7Af5TB30dZ
8U9Lg/JVkt3ErgEAuTKsOhlN43fk0iBcvmK/A6nLMWW0lb7RnbhAXyRXXwI=
=3hmo
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmprGWkACgkQmmx57+YA
GNnmLBAAq7OGHXTWuWaRNdsUq/LeA+CifO3Hah0giYBQDEJ940XRgosfBIw5/nEA
rPym1hIYQ5G9eJNQHzBGLlVk83dEcCB6RpqXJUwG176sPuaSDULnkL0c8nNDtMIY
Rgpm/WhizEBlZlqawbNLGHlY6Nii0xNZJuHqq8SiP6vwyYR9bBfrfXEAzvA/ymS0
rnVUtPh2NA4OZ2/7RW+STr6X9XrtRL5a3DEtJSsVJevfxDn3/XAicdgRRqd3vqGj
+1VaNffXhFRQRHMbFgVn49e8xhcq8S9tBTgp82mRB2UK4e5yrlJLbI/vJJQvj3+S
AZjoitLf3rdmYMn8pPQ0ohuMSszoh8VkLEscDav42zQ+0LIb++usz5vEoUA9qXLy
wQZx2fmiwuH50J7jOLdUQ9rF/0lmrb0VF7LtwnlvzBuTarZBDR7evb4+eTUb5M4E
Fs7oeaxLI4bV73X8OBCzFv8mxX5hlMKXgftaRDwlhq7uBoyobkj8AdTuMMK01wkn
gXBCMACwoNk13zAJVW86qG6Sr3mzNTxqnuL4lKLCHnt8QuuMmpDRFe1A/HNR3IxA
Ouv18uzqfAzwq+murnpXUFPEQqj58J47HKRzZGL0JrEnfFnQS6Ch4jph/U4Jrt6i
4n//bYqn4XTeMkqm+aeQddWNQulMqN9c9xHEJ7yq5UUbKNYB9OQ=
=iRpe
-----END PGP SIGNATURE-----
Merge tag 'mtk-dts64-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
MediaTek ARM64 DeviceTree updates
This adds a couple of fixes and improvements for multiple
MediaTek SoCs.
In particular:
- Indentation/whitespace fixes for some devicetrees
- Documentation improvements for MediaTek Mute-X
- dtbs-check warnings fixes
- MT8390 Tungsten boards: removal of unnecessary cells
- MT6795 SoC: removal of deprecated property in UART DMA
- MT6359 PMIC's RTC now uses the correct compatible string
- MT8183/86/88/92/95 SoCs gain support for the UART DMA IPs
- MT8186 gets a new CCI OPP table to resolve lockups
- MT8188/83 Chromebooks now got the correct SPI NOR supply
- MT8192 Asurada drops support for the (unused) MMC1 port
- MediaTek Genio 510/700/1200 EVKs and Radxa NIO-12L now get
their PMIC power input tree completed with assignment of
the correct supplies
* tag 'mtk-dts64-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
arm64: dts: mediatek: mt6359: use proper compatible for rtc
arm64: dts: mediatek: mt8395-radxa-nio-12l: Add MT6365 PMIC supplies
arm64: dts: mediatek: mt8395-genio-common: Add MT6365 PMIC supplies
arm64: dts: mediatek: mt8390-genio-common: Add MT6365 PMIC supplies
arm64: dts: mediatek: mt8192-asurada: Disable mmc1 on Spherion
dt-bindings: soc: mediatek: mutex: Improve title and description
arm64: dts: mediatek: mt8195: Add and use UART AP_DMA controller
arm64: dts: mediatek: mt8192: Add and use UART AP_DMA controller
arm64: dts: mediatek: mt8188: Add and use UART AP_DMA controller
arm64: dts: mediatek: mt8186: Add and use UART AP_DMA controller
arm64: dts: mediatek: mt8183: Add and use UART AP_DMA controller
arm64: dts: mediatek: mt6795: Remove deprecated UART DMA property
arm64: dts: mediatek: tungsten-smarc: Remove unnecessary cells
arm64: dts: mediatek: Correct indentation and whitespace
arm64: dts: mediatek: mt8188-geralt: Add supply for SPI NOR flash
arm64: dts: mediatek: mt8183-kukui: Add supply for SPI NOR flash
arm64: dts: mediatek: mt8186: change CCI OPP scaling mapping
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This fixes a minor indentation issue in the MT8127 devicetree
and adds support for the Auxiliary ADC found in the MT6323 PMIC.
-----BEGIN PGP SIGNATURE-----
iLoEABYKAGIWIQQn3Xxr56ypAcSHzXSaNgTPrZeEeAUCamsCiBsUgAAAAAAEAA5t
YW51MiwyLjUrMS4xMiwyLDIoHGFuZ2Vsb2dpb2FjY2hpbm8uZGVscmVnbm9AY29s
bGFib3JhLmNvbQAKCRCaNgTPrZeEeBPiAP9lr1/GKI8x8ic4JtzZRYfTf9wOJUjL
L+k64fFBWZHn8wD+MBGSwiCXpudcN4GkLS0HKN7UkDL5gcdlCgZ4DbeLAgA=
=PxxN
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmprGPcACgkQmmx57+YA
GNnbGhAAmoaFmscdDKzVodn4eQB+TIGpD2XxE6qrYbD9k7LE2Kp2tnrjjvfsTsr4
JBeHQUnjZgAXVmpdWBqxan5GrgXThvKoWvsPtADR06SiIEk2wxCS4Pwh97629FQE
w+zpABMuq/sgPhAiSvVZIsAlhPUzvx8ILuA69HE7wBiHHpDh3Zl9yZiskcikc3K9
Egd2Q2tw+OkgYfW1ccIgQFwyum5ot/tcQoKGLPugvzDa6fHj8gXfiUOFSlqK7ak0
oQCT8Ue+l2MiCVcURLKMEukuxe7sq+PdHtW+V6q0LpVfUskYJ3rWs+qT7e0lWH2n
9zlL0xh8zBTOgVC22uJJvpRcCHrp0tbusXZzbGKQOFVBZSJOhlMkW3uUqk0sAg8B
RldqDsTFH2WfoZjsI4SWV1hRoM1gqvHUu1gDroJYglwcFMjsLJMlMdNmHI7MupsO
DCvG2gAx+Kj5Gz4Gf+LDFx5khS3ucIsjPl+VR+1foGxLcoWYvI0KgV5lqMWecaKr
7NowJYN1SHfqNozyMUkNb/qGJrX+1jBjUHuPp758GC2FnMXh0hB8/XJuFc5n09E7
U/T9DvEdltgx+7dDYrL5BP/ZkxeGY6F/kd47zCd5LVeQovJAiE5wD+lbGN09oYsf
54tTfbIwiO7NH/+uiR2HIa3EMbSV0xIalFe9VS9iXuK5nUE43xc=
=rAn0
-----END PGP SIGNATURE-----
Merge tag 'mtk-dts32-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
MediaTek ARM32 DeviceTree updates
This fixes a minor indentation issue in the MT8127 devicetree
and adds support for the Auxiliary ADC found in the MT6323 PMIC.
* tag 'mtk-dts32-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
ARM: dts: mediatek: mt6323: add AUXADC support
ARM: dts: mediatek: mt8127: Correct indentation
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Enable CPU DVFS on Milk-V Jupiter by including the OPP tables and wiring the
CPU nodes to the CPU regulator supply.
Reviewed-by: Yixun Lan <dlan@kernel.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Link: https://patch.msgid.link/20260729160749.1621415-2-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
On the Banana Pi BPI-CM6 module, the buck1 and buck2 voltage regulators,
which supply the CPU core voltage, are configured with a maximum output
voltage of 3.45V, while the highest operating point requires only
1.050V. This means that a kernel bug, OPP misconfiguration, or
privileged userspace could request a voltage above the safe operating
limit, causing possible permanent CPU damage.
Set the maximum regulator voltage to 1.050V instead.
Fixes: 46a8c01700 ("riscv: dts: spacemit: k1: Add Banana Pi BPI-CM6 IO board")
Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729150722.1598630-7-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
On the OrangePi R2S board, the buck1 and buck2 voltage regulators, which
supply the CPU core voltage, are configured with a maximum output
voltage of 3.45V, while the highest operating point requires only
1.050V. This means that a kernel bug, OPP misconfiguration, or
privileged userspace could request a voltage above the safe operating
limit, causing possible permanent CPU damage.
Set the maximum regulator voltage to 1.050V instead.
Fixes: 793cc54475 ("riscv: dts: spacemit: enable PMIC on OrangePi R2S")
Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net
Cc: stable@vger.kernel.org
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729150722.1598630-6-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
On the MusePi Pro board, the buck1 and buck2 voltage regulators, which
supply the CPU core voltage, are configured with a maximum output
voltage of 3.45V, while the highest operating point requires only
1.050V. This means that a kernel bug, OPP misconfiguration, or
privileged userspace could request a voltage above the safe operating
limit, causing possible permanent CPU damage.
Set the maximum regulator voltage to 1.050V instead.
Fixes: e2dac7c7a3 ("riscv: dts: spacemit: k1-musepi-pro: add PMIC and power infrastructure")
Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net
Cc: stable@vger.kernel.org
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729150722.1598630-5-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
On the OrangePi RV2 board, the buck1 and buck2 voltage regulators, which
supply the CPU core voltage, are configured with a maximum output
voltage of 3.45V, while the highest operating point requires only
1.050V. This means that a kernel bug, OPP misconfiguration, or
privileged userspace could request a voltage above the safe operating
limit, causing possible permanent CPU damage.
Set the maximum regulator voltage to 1.050V instead.
Fixes: c02c047b92 ("riscv: dts: spacemit: Define the P1 PMIC regulators for OrangePi RV2")
Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net
Cc: stable@vger.kernel.org
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729150722.1598630-4-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
On the Milk-V Jupiter board, the buck1 and buck2 voltage regulators,
which supply the CPU core voltage, are configured with a maximum output
voltage of 3.45V, while the highest operating point requires only
1.050V. This means that a kernel bug, OPP misconfiguration, or
privileged userspace could request a voltage above the safe operating
limit, causing possible permanent CPU damage.
Set the maximum regulator voltage to 1.050V instead.
Fixes: 7d307daa12 ("riscv: dts: spacemit: Define the P1 PMIC regulators for Milk-V Jupiter")
Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net
Cc: stable@vger.kernel.org
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729150722.1598630-3-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
On the Banana Pi BPI-F3 board, the buck1 and buck2 voltage regulators,
which supply the CPU core voltage, are configured with a maximum output
voltage of 3.45V, while the highest operating point requires only
1.050V. This means that a kernel bug, OPP misconfiguration, or
privileged userspace could request a voltage above the safe operating
limit, causing possible permanent CPU damage.
Set the maximum regulator voltage to 1.050V instead.
Fixes: 09a412d397 ("riscv: dts: spacemit: define regulator constraints")
Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net
Cc: stable@vger.kernel.org
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260729150722.1598630-2-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
