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1,267,977 commits

Author SHA1 Message Date
Zhengchao Shao
b4c1d4d973 fib: remove unnecessary input parameters in fib_default_rule_add
When fib_default_rule_add is invoked, the value of the input parameter
'flags' is always 0. Rules uses kzalloc to allocate memory, so 'flags' has
been initialized to 0. Therefore, remove the input parameter 'flags' in
fib_default_rule_add.

Signed-off-by: Zhengchao Shao <shaozhengchao@huawei.com>
Reviewed-by: David Ahern <dsahern@kernel.org>
Link: https://lore.kernel.org/r/20240102071519.3781384-1-shaozhengchao@huawei.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-01-03 16:42:48 -08:00
Marcin Wojtas
5fe65375e3 net: mvpp2: initialize port fwnode pointer
Update the port's device structure also with its fwnode pointer
with a recommended device_set_node() helper routine.

Signed-off-by: Marcin Wojtas <marcin.s.wojtas@gmail.com>
Reviewed-by: Suman Ghosh <sumang@marvell.com>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://lore.kernel.org/r/20231231122019.123344-1-marcin.s.wojtas@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-01-03 16:41:42 -08:00
Ilpo Järvinen
73b2e2e3fe net: mdio: mux-bcm-iproc: Use alignment helpers and SZ_4K
Instead of open coding, use IS_ALIGNED() and ALIGN_DOWN() when dealing
with alignment. Replace also literals with SZ_4K.

Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Acked-by: Ray Jui <ray.jui@broadcom.com>
Link: https://lore.kernel.org/r/20231229145232.6163-1-ilpo.jarvinen@linux.intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-01-03 16:40:59 -08:00
Krzysztof Kozlowski
16615a2aa5 arm64: dts: intel: minor whitespace cleanup around '='
The DTS code coding style expects exactly one space before and after '='
sign.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-01-03 18:10:40 -06:00
Krzysztof Kozlowski
e3c163c3a0 arm64: dts: socfpga: agilex: drop redundant status
New device nodes are enabled by default.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-01-03 18:10:40 -06:00
Krzysztof Kozlowski
68d550d00c arm64: dts: socfpga: agilex: add unit address to soc node
The "soc" node has ranges with addresses, so it is should have unit
address  to fix dtc W=1 warnings like:

  socfpga_agilex.dtsi:152.6-674.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-01-03 18:10:40 -06:00
Krzysztof Kozlowski
23c3ebed38 arm64: dts: socfpga: agilex: move firmware out of soc node
The "soc" node is supposed to have only MMIO children, so move the
firmware/svc node to top level to fix dtc W=1 warnings like:

  socfpga_agilex.dtsi:663.12-673.5: Warning (simple_bus_reg): /soc@0/firmware: missing or empty reg/ranges property

The node should still be instantiated by drivers/of/platform.c, just
like in all other platforms.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-01-03 18:10:40 -06:00
Krzysztof Kozlowski
eb68721256 arm64: dts: socfpga: agilex: move FPGA region out of soc node
The "soc" node is supposed to have only MMIO children, so move the FPGA
region node to top level to fix dtc W=1 warnings like:

  socfpga_agilex.dtsi:141.20-146.5: Warning (simple_bus_reg): /soc@0/base_fpga_region: missing or empty reg/ranges property

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-01-03 18:10:40 -06:00
Krzysztof Kozlowski
5c7c75b9cd arm64: dts: socfpga: agilex: align pin-controller name with bindings
Use a generic node name for the pin controller node to fix:

  /socfpga_agilex_n6000.dtb: pinconf@ffd13100: $nodename:0: 'pinconf@ffd13100' does not match '^(pinctrl|pinmux)(@[0-9a-f]+)?$'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-01-03 18:10:40 -06:00
Krzysztof Kozlowski
9241b019b2 arm64: dts: socfpga: stratix10_swvp: drop unsupported DW MSHC properties
altr,dw-mshc-ciu-div and altr,dw-mshc-sdr-timing are neither documented
nor used by Linux, so remove them to fix dtbs_check warnings like:

  socfpga_stratix10_swvp.dtb: mmc@ff808000: Unevaluated properties are not allowed
    ('altr,dw-mshc-ciu-div', 'altr,dw-mshc-sdr-timing' were unexpected)

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-01-03 18:10:40 -06:00
Krzysztof Kozlowski
30bc690422 arm64: dts: socfpga: stratix10_socdk: align NAND chip name with bindings
Bindings expect NAND child node name to match certain patterns:

  socfpga_agilex_socdk_nand.dtb: nand-controller@ffb90000: Unevaluated properties are not allowed ('flash@0' was unexpected)

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-01-03 18:10:40 -06:00
Krzysztof Kozlowski
5e53525fc6 arm64: dts: socfpga: stratix10: add unit address to soc node
The "soc" node has ranges with addresses, so it is should have unit
address  to fix dtc W=1 warnings like:

  socfpga_stratix10.dtsi:128.6-636.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-01-03 18:10:39 -06:00
Krzysztof Kozlowski
9fc0511a47 arm64: dts: socfpga: stratix10: move firmware out of soc node
The "soc" node is supposed to have only MMIO children, so move the
firmware/svc node to top level to fix dtc W=1 warnings like:

  socfpga_stratix10.dtsi:625.12-635.5: Warning (simple_bus_reg): /soc@0/firmware: missing or empty reg/ranges property

The node should still be instantiated by drivers/of/platform.c, just
like in all other platforms.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-01-03 18:10:39 -06:00
Krzysztof Kozlowski
5c8f036f92 arm64: dts: socfpga: stratix10: move FPGA region out of soc node
The "soc" node is supposed to have only MMIO children, so move the FPGA
region node to top level to fix dtc W=1 warnings like:

  socfpga_stratix10.dtsi:136.20-141.5: Warning (simple_bus_reg): /soc@0/base_fpga_region: missing or empty reg/ranges property

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-01-03 18:10:39 -06:00
Krzysztof Kozlowski
179e58703e arm64: dts: socfpga: stratix10: align pincfg nodes with bindings
pinctrl-single bindings require pin configuration node names to match
certain patterns:

  socfpga_stratix10_socdk.dtb: pinctrl@ffd13000: 'i2c1-pmx-func', 'i2c1-pmx-func-gpio'
    do not match any of the regexes: '-pins(-[0-9]+)?$|-pin$', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-01-03 18:10:39 -06:00
Krzysztof Kozlowski
91b491fd03 arm64: dts: socfpga: stratix10: add clock-names to DWC2 USB
The DWC2 USB bindings require clock-names property, to provide such to
fix warnings like:

  socfpga_stratix10_swvp.dtb: usb@ffb40000: 'clock-names' is a required property

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-01-03 18:10:39 -06:00
Krzysztof Kozlowski
2241f81c91 arm64: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size
cdns,page-size and cdns,block-size are neither documented nor used by
Linux, so remove them to fix dtbs_check warnings like:

  socfpga_n5x_socdk.dtb: flash@0: Unevaluated properties are not allowed ('cdns,block-size', 'cdns,page-size' were unexpected)

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-01-03 18:10:39 -06:00
Krzysztof Kozlowski
575c726ce8 ARM: dts: socfpga: align NAND controller name with bindings
Bindings expect NAND controller node name to match certain patterns:

  socfpga_arria10_socdk_nand.dtb: nand@ffb90000: $nodename:0: 'nand@ffb90000' does not match '^nand-controller(@.*)?'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-01-03 18:10:39 -06:00
Krzysztof Kozlowski
a5db395a1c ARM: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size
cdns,page-size and cdns,block-size are neither documented nor used by
Linux, so remove them to fix dtbs_check warnings like:

  socfpga_arria5_socdk.dtb: flash@0: Unevaluated properties are not allowed ('cdns,block-size', 'cdns,page-size' were unexpected)

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2024-01-03 18:10:39 -06:00
Asad Kamal
ff5ab42b79 drm/amd/pm: Update metric table for jpeg/vcn data
Update pmfw metric table to include vcn & jpeg
activity for smu_v_13_0_6

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-01-03 18:59:26 -05:00
Asad Kamal
0cc9e952e6 drm/amd/pm: Use separate metric table for APU
Use separate metric table for APU and Non APU
systems for smu_v_13_0_6 to get metric data

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-01-03 18:58:26 -05:00
Sam Shih
4b4719437d clk: mediatek: add drivers for MT7988 SoC
Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are
typical MediaTek designs.

Also add driver for XFIPLL clock generating the 156.25MHz clock for
the XFI SerDes. It needs an undocumented software workaround and has
an unknown internal design.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/c7574d808e2da1a530182f0fd790c1337c336e1b.1702849494.git.daniel@makrotopia.org
[sboyd@kernel.org: Add module license to infracfg file]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03 15:57:02 -08:00
Wayne Lin
9cdef4f720 drm/amd/display: pbn_div need be updated for hotplug event
link_rate sometime will be changed when DP MST connector hotplug, so
pbn_div also need be updated; otherwise, it will mismatch with
link_rate, causes no output in external monitor.

This is a backport to 6.7 and older.

Cc: stable@vger.kernel.org
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Jerry Zuo <jerry.zuo@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Wade Wang <wade.wang@hp.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-01-03 18:56:48 -05:00
Sam Shih
d9bf944bea clk: mediatek: add pcw_chg_bit control for PLLs of MT7988
Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead
of the previously hardcoded PCW_CHG_MASK macro if set.
This will needed for clocks on the MT7988 SoC.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03 15:55:19 -08:00
Daniel Golle
afd36e9d91 dt-bindings: clock: mediatek: add clock controllers of MT7988
Add various clock controllers found in the MT7988 SoC to existing
bindings (if applicable) and add files for the new ethwarp, mcusys
and xfi-pll clock controllers not previously present in any SoC.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/07e76a544ce4392bcb88e34d5480e99bb7994618.1702849494.git.daniel@makrotopia.org
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03 15:55:17 -08:00
Daniel Golle
5cfa3beb77 dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs
Add reset ID for ethwarp subsystem allowing to reset the built-in
Ethernet switch of the MediaTek MT7988 SoC.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/0c14bbacf471683af67ffa7572bfa1d5c45a0b5d.1702849494.git.daniel@makrotopia.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03 15:55:15 -08:00
Sam Shih
8187e001de dt-bindings: clock: mediatek: add MT7988 clock IDs
Add MT7988 clock dt-bindings for topckgen, apmixedsys, infracfg,
ethernet and xfipll subsystem clocks.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/27f99db432e9ccc804cc5b6501d7d17d72cae879.1702849494.git.daniel@makrotopia.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03 15:55:12 -08:00
AngeloGioacchino Del Regno
ebbf49d4cf clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes
The top_dp and top_edp muxes can be both parented to either TVDPLL1
or TVDPLL2, two identically specced PLLs for the specific purpose of
giving out pixel clock: this becomes a problem when the MediaTek
DisplayPort Interface (DPI) driver tries to set the pixel clock rate.

In the usecase of two simultaneous outputs (using two controllers),
it was seen that one of the displays would sometimes display garbled
output (if any at all) and this was because:
 - top_edp was set to TVDPLL1, outputting X GHz
 - top_dp was set to TVDPLL2, outputting Y GHz
   - mtk_dpi calls clk_set_rate(top_edp, Z GHz)
 - top_dp is switched to TVDPLL1
 - TVDPLL1 changes its rate, top_edp outputs the wrong rate.
 - eDP display is garbled

To solve this issue, remove all TVDPLL1 parents from `top_dp` and
all TVDPLL2 parents from `top_edp`, plus, necessarily switch both
clocks to use the new MUX_GATE_CLR_SET_UPD_INDEXED() macro to be
able to use the right bit index for the new parents list.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20231103102533.69280-4-angelogioacchino.delregno@collabora.com
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Fei Shao <fshao@chromium.org>
Reviewed-by: Fei Shao <fshao@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03 15:55:08 -08:00
AngeloGioacchino Del Regno
831f9216a7 clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes
The top_dp and top_edp muxes can be both parented to either TVDPLL1
or TVDPLL2, two identically specced PLLs for the specific purpose of
giving out pixel clock: this becomes a problem when the MediaTek
DisplayPort Interface (DPI) driver tries to set the pixel clock rate.

In the usecase of two simultaneous outputs (using two controllers),
it was seen that one of the displays would sometimes display garbled
output (if any at all) and this was because:
 - top_edp was set to TVDPLL1, outputting X GHz
 - top_dp was set to TVDPLL2, outputting Y GHz
   - mtk_dpi calls clk_set_rate(top_edp, Z GHz)
     - top_dp is switched to TVDPLL1
     - TVDPLL1 changes its rate, top_edp outputs the wrong rate.
     - eDP display is garbled

To solve this issue, remove all TVDPLL1 parents from `top_dp` and
all TVDPLL2 parents from `top_edp`, plus, necessarily switch both
clocks to use the new MUX_GATE_CLR_SET_UPD_INDEXED() macro to be
able to use the right bit index for the new parents list.

Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20231103102533.69280-3-angelogioacchino.delregno@collabora.com
Reviewed-by: Fei Shao <fshao@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03 15:55:06 -08:00
AngeloGioacchino Del Regno
a6a70a670c clk: mediatek: clk-mux: Support custom parent indices for muxes
Add support for customized parent indices for MediaTek muxes: this is
necessary for the case in which we want to exclude some clocks from
a mux's parent clocks list, where the exclusions are not from the
very bottom of the list but either in the middle or the beginning.

Example:
- MUX1 (all parents)
  - parent1; idx=0
  - parent2; idx=1
  - parent3; idx=2

- MUX1 (wanted parents)
  - parent1; idx=0
  - parent3; idx=2

To achieve that add a `parent_index` array pointer to struct mtk_mux,
then in .set_parent(), .get_parent() callbacks check if this array
was populated and eventually get the index from that.

Also, to avoid updating all clock drivers for all SoCs, rename the
"main" macro to __GATE_CLR_SET_UPD_FLAGS (so, `__` was added) and
add the new member to it; furthermore, GATE_CLK_SET_UPD_FLAGS has
been reintroduced as being fully compatible with the older version.

The new parent_index can be specified with the new `_INDEXED`
variants of the MUX_GATE_CLR_SET_UPD_xxxx macros.

Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20231103102533.69280-2-angelogioacchino.delregno@collabora.com
Tested-by: Fei Shao <fshao@chromium.org>
Reviewed-by: Fei Shao <fshao@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03 15:55:02 -08:00
Stephen Boyd
145916f689 Amlogic clock updates for v6.8
* Add DSI clocks on g12/sm1
 * Add CSI and ISP clocks on g12/sm1
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Merge tag 'clk-meson-v6.8-1' of https://github.com/BayLibre/clk-meson into clk-amlogic

Pull Amlogic clk driver updates from Jerome Brunet:

 - Add DSI clocks on Amlogic g12/sm1
 - Add CSI and ISP clocks on Amlogic g12/sm1

* tag 'clk-meson-v6.8-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: g12a: add CSI & ISP gates clocks
  clk: meson: g12a: add MIPI ISP clocks
  dt-bindings: clock: g12a-clkc: add MIPI ISP & CSI PHY clock ids
  clk: meson: g12a: add CTS_ENCL & CTS_ENCL_SEL clocks
  dt-bindings: clk: g12a-clkc: add CTS_ENCL clock ids
2024-01-03 15:54:05 -08:00
Stephen Boyd
f1b591217f i.MX clocks changes for 6.8
- Document bindings for i.MX93 ANATOP clock driver
 - Free clk_node in SCU driver for resource with different owner
 - Update the LVDS clocks to be compatible with SCU firmware 1.15
 - Fix the name of the fvco in pll14xx by renaming it to fout
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Merge tag 'clk-imx-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx

Pull i.MX clk driver updates from Abel Vesa:

 - Document bindings for i.MX93 ANATOP clock driver
 - Free clk_node in SCU driver for resource with different owner
 - Update the LVDS clocks to be compatible with SCU firmware 1.15
 - Fix the name of the fvco in pll14xx by renaming it to fout

* tag 'clk-imx-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
  clk: imx: pll14xx: change naming of fvco to fout
  clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocks
  clk: imx: scu: Fix memory leak in __imx_clk_gpr_scu()
  dt-bindings: clock: support i.MX93 ANATOP clock module
2024-01-03 15:53:49 -08:00
Stephen Boyd
93beaa981a Qualcomm clock updates for v6.8
New drivers to support global, display, gpu, tcsr, and rpmh clocks for
 the SM8650 platform is introduced.
 
 Global and RPMh clock support for the new X1E80100 platform is added.
 
 Support for the Stromer APCS PLL found in IPQ5018 is added.
 
 A new type of branch clock, with support for controlling separate memory
 control bits is introduced, and used in the newly introduced clock
 driver for the ECPRI on QDU1000 and QRU1000.
 
 A number of missing clock related to CSI2 on MSM8939 are added. Support
 for the camera clock controller on SC8280XP is added.
 
 PLL configuration is corrected in GPU and Video clock controllers for
 SM8150, runtim PM support and a few missing resets are added to the
 video clock controller.
 
 For SM8550 configuration of a variety of GDSCs in GCC is corrected.
 Shared RCGs was not marked appropriately when the driver was upstreamed,
 so this is corrected as well.
 For GPU and Display clock controllers PLL configuration settings are
 reviewed and corrected.
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Merge tag 'qcom-clk-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Pull Qualcomm clk driver updates from Bjorn Andersson:

 - New drivers to support global, display, gpu, tcsr, and rpmh clocks on
   Qualcomm SM8650
 - Global and RPMh clock support for the Qualcomm X1E80100 SoC
 - Support for the Stromer APCS PLL found in Qualcomm IPQ5018
 - Add a new type of branch clock, with support for controlling separate
   memory control bits, to the Qualcomm clk driver
 - Use new branch type in Qualcomm ECPRI clk driver for QDU1000 and
   QRU1000
 - Add a number of missing clocks related to CSI2 on Qualcomm MSM8939
 - Add support for the camera clock controller on Qualcomm SC8280XP
 - Correct PLL configuration in GPU and video clock controllers for
   Qualcomm SM8150
 - Add runtime PM support and a few missing resets to Qualcomm SM8150
   video clock controller
 - Fix configuration of various GCC GDSCs on Qualcomm SM8550
 - Mark shared RCGs appropriately in the Qualcomm SM8550 GCC driver
 - Fix up GPU and display clock controllers PLL configuration settings
   on Qualcomm SM8550

* tag 'qcom-clk-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (41 commits)
  clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config
  clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config
  clk: qcom: dispcc-sm8550: Use the correct PLL configuration function
  clk: qcom: dispcc-sm8550: Update disp PLL settings
  clk: qcom: gpucc-sm8550: Update GPU PLL settings
  clk: qcom: gcc-sm8550: Mark RCGs shared where applicable
  clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCs
  clk: qcom: gcc-sm8550: Mark the PCIe GDSCs votable
  clk: qcom: gcc-sm8550: Add the missing RETAIN_FF_ENABLE GDSC flag
  clk: qcom: camcc-sc8280xp: Prevent error pointer dereference
  clk: qcom: videocc-sm8150: Add runtime PM support
  clk: qcom: videocc-sm8150: Add missing PLL config property
  clk: qcom: videocc-sm8150: Update the videocc resets
  dt-bindings: clock: Update the videocc resets for sm8150
  clk: qcom: rpmh: Add support for X1E80100 rpmh clocks
  clk: qcom: Add Global Clock controller (GCC) driver for X1E80100
  dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for X1E80100
  dt-bindings: clock: qcom: Add X1E80100 GCC clocks
  clk: qcom: Add ECPRICC driver support for QDU1000 and QRU1000
  clk: qcom: branch: Add mem ops support for branch2 clocks
  ...
2024-01-03 15:53:14 -08:00
Inochi Amaoto
5a72f07111 dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC
Add definition for the clock controller of the CV1800 series SoC.

For CV181X, it has a clock that CV180X does not have. To avoid misuse,
also add a compatible string to identify CV181X series SoC.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Link: https://github.com/milkv-duo/duo-files/blob/main/hardware/CV1800B/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdf
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/IA1PR20MB49535E448097F6FFC1218C39BB90A@IA1PR20MB4953.namprd20.prod.outlook.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03 15:52:52 -08:00
Emil Renner Berthing
4287cd628f clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx
This is needed by the dwmac-starfive ethernet driver to set the clock
for 1000, 100 and 10 Mbps links properly.

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
Link: https://lore.kernel.org/r/20231219232442.2460166-3-cristian.ciocaltea@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03 15:51:58 -08:00
Emil Renner Berthing
a242b2051b clk: starfive: Add flags argument to JH71X0__MUX macro
This flag is needed to add the CLK_SET_RATE_PARENT flag on the gmac_tx
clock on the JH7100, which in turn is needed by the dwmac-starfive
driver to set the clock properly for 1000, 100 and 10 Mbps links.

This change was mostly made using coccinelle:

@ match @
expression idx, name, nparents;
@@
 JH71X0__MUX(
-idx, name, nparents,
+idx, name, 0, nparents,
 ...)

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
Link: https://lore.kernel.org/r/20231219232442.2460166-2-cristian.ciocaltea@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-01-03 15:51:55 -08:00
Linus Torvalds
ac865f00af pci-v6.7-fixes-2
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Merge tag 'pci-v6.7-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci

Pull PCI fixes from Bjorn Helgaas:

 - Revert an ASPM patch that caused an unintended reboot when resuming
   after suspend (Bjorn Helgaas)

 - Orphan Cadence PCIe IP (Bjorn Helgaas)

* tag 'pci-v6.7-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci:
  MAINTAINERS: Orphan Cadence PCIe IP
  Revert "PCI/ASPM: Remove pcie_aspm_pm_state_change()"
2024-01-03 14:18:57 -08:00
Ira Weiny
6d0fc416c4 cxl/trace: Pass UUID explicitly to event traces
CXL CPER events are identified by the CPER Section Type GUID. The GUID
correlates with the CXL UUID for the event record. It turns out that a
CXL CPER record is a strict subset of the CXL event record, only the
UUID header field is chopped.

In order to unify handling between native and CPER flavors of CXL
events, prepare the code for the UUID to be passed in rather than
inferred from the record itself.

Later patches update the passed in record to only refer to the common
data between the formats.

Pass the UUID explicitly to each trace event to be able to remove the
UUID from the event structures.

Originally it was desirable to remove the UUID from the well known event
because the UUID value was redundant.  However, the trace API was
already in place.[1]

Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Link: https://lore.kernel.org/all/36f2d12934d64a278f2c0313cbd01abc@huawei.com [1]
Link: https://lore.kernel.org/r/20231220-cxl-cper-v5-1-1bb8a4ca2c7a@intel.com
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2024-01-03 14:15:52 -08:00
Linus Torvalds
d7807d8544 + Bug Fix
- Fix move_mount mediation regression when source is detached
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Merge tag 'apparmor-pr-2024-01-03' of git://git.kernel.org/pub/scm/linux/kernel/git/jj/linux-apparmor

Pull apparmor fix from John Johansen:
 "Detect that the source mount is not in the namespace and if it isn't
  don't use it as a source path match.

  This prevent apparmor from applying the attach_disconnected flag to
  move_mount() source which prevents detached mounts from appearing as /
  when applying mount mediation, which is not only incorrect but could
  result in bad policy being generated"

* tag 'apparmor-pr-2024-01-03' of git://git.kernel.org/pub/scm/linux/kernel/git/jj/linux-apparmor:
  apparmor: Fix move_mount mediation by detecting if source is detached
2024-01-03 13:58:37 -08:00
Steven Rostedt (Google)
4b2df884b8 ring-buffer/Documentation: Add documentation on buffer_percent file
When the buffer_percent file was added to the kernel, the documentation
should have been updated to document what that file does.

Acked-by: "Masami Hiramatsu (Google)" <mhiramat@kernel.org>
Fixes: 03329f9939 ("tracing: Add tracefs file buffer_percentage")
Signed-off-by: "Steven Rostedt (Google)" <rostedt@goodmis.org>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Link: https://lore.kernel.org/r/20231229122402.537eb252@gandalf.local.home
2024-01-03 14:41:52 -07:00
longjin
d78bcf646c Translated the RISC-V architecture boot documentation.
The patch adds a new file boot.rst to the Documentation/translations/zh_CN/
arch/riscv/ directory, and adds a reference to the new file
in the index.rst file.

Signed-off-by: longjin <longjin@DragonOS.org>
Reviewed-by: Yanteng Si <siyanteng@loongson.cn>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Link: https://lore.kernel.org/r/20231218092924.200165-1-longjin@DragonOS.org
2024-01-03 14:29:28 -07:00
Thomas Weißschuh
821bd43ed5 Docs: remove mentions of fdformat from util-linux
Since util-linux commit 13b26e3c36d1
("fdformat: remove command from default build")
the fdformat tool is not built anymore by default.
As a result it is not packaged anymore by distributions and therefore
not usable by users.

Instead mention the "mount" command as more likely to be present
alternative.

Also drop the reference to fdformat from the list of features of new
versions of util-linux.

Signed-off-by: Thomas Weißschuh <linux@weissschuh.net>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Link: https://lore.kernel.org/r/20231220-docs-fdformat-v1-1-0d05279e5d83@weissschuh.net
2024-01-03 14:25:59 -07:00
JiaLong.Yang
0587e62bf4 Docs/zh_CN: Fix the meaning of DEBUG to pr_debug()
We know the macro DEBUG will make pr_debug() save the formatted
string into final binary. But the translation in chinese gives a
opposite meaning.

Signed-off-by: "JiaLong.Yang" <jialong.yang@shingroup.cn>
Reviewed-by: Zenghui Yu <zenghui.yu@linux.dev>
Acked-by: Yanteng Si <siyanteng@loongson.cn>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Link: https://lore.kernel.org/r/20231221055832.4374-1-jialong.yang@shingroup.cn
2024-01-03 14:23:48 -07:00
Vegard Nossum
bb67bf1c4a Documentation: move driver-api/dcdbas to userspace-api/
This file documents a sysfs interface that is intended for systems
management software. It does NOT document any kind of kernel driver
API. It is also not meant to be used directly by system administrators
or users.

Cc: Stuart Hayes <stuart.w.hayes@gmail.com>
Cc: platform-driver-x86@vger.kernel.org
Signed-off-by: Vegard Nossum <vegard.nossum@oracle.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Link: https://lore.kernel.org/r/20231221124816.2978000-3-vegard.nossum@oracle.com
2024-01-03 14:17:40 -07:00
Vegard Nossum
77e075579e Documentation: move driver-api/isapnp to userspace-api/
driver-api/isapnp documents /proc interfaces for interfacing directly
with ISA Plug & Play devices, not any kind of API for kernel developers,
and should thus also live under userspace-api/.

Also fix a few issues while we're at it.

Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Vegard Nossum <vegard.nossum@oracle.com>
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Link: https://lore.kernel.org/r/20231221124816.2978000-2-vegard.nossum@oracle.com
2024-01-03 14:17:39 -07:00
attreyee-muk
89405db5cd Documentation/core-api : fix typo in workqueue
Correct to “boundaries” from “bounaries”

Signed-off-by: Attreyee Mukherjee <tintinm2017@gmail.com>
Acked-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Link: https://lore.kernel.org/r/20231223175316.24951-1-tintinm2017@gmail.com
2024-01-03 14:16:57 -07:00
Matthew Cassell
d3f79db932 Documentation/trace: Fixed typos in the ftrace FLAGS section
Fixed typos in the FTRACE_OPS_FL_RECURSION flag description.

Signed-off-by: Matthew Cassell <mcassell411@gmail.com>
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Link: https://lore.kernel.org/r/20231223185845.2326-1-mcassell411@gmail.com
2024-01-03 14:15:53 -07:00
Randy Dunlap
afa751e84c kernel-doc: handle a void function without producing a warning
Currently a void function can produce a warning:
  main.c:469: warning: contents before sections

This one is from arch/x86/kernel/cpu/sgx/main.c (which is not included
in any produced kernel documentation output).

Handle this by setting $in_doc_sect to 1 whenever any recognized
document section name is processed.

Fixes: f624adef3d ("kernel-doc: limit the "section header:" detection to a select few")
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: linux-doc@vger.kernel.org
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Link: https://lore.kernel.org/r/20231226065219.319-1-rdunlap@infradead.org
2024-01-03 14:04:31 -07:00
Randy Dunlap
75ddc07835 scripts/get_abi.pl: ignore some temp files
When there are filenames of the form ".orig" or ".rej" in
the Documenatation/ABI/ subdirectories, there can be confusing or
erroneous output generated. Example: the file
Documenation/ABI/testing/sysfs-bus-papr-pmem.orig causes this
warning message:

Documentation/ABI/testing/sysfs-bus-papr-pmem:2: WARNING: unknown document: '/powerpc/papr_hcalls'

Prevent this by skipping over filenames that may be created by
patch/diff tools etc.

Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: linux-doc@vger.kernel.org
Acked-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Link: https://lore.kernel.org/r/20231228233113.5218-1-rdunlap@infradead.org
2024-01-03 14:02:17 -07:00
Ian Rogers
ec5257d99e perf x86 test: Add hybrid test for conflicting legacy/sysfs event
The cpu-cycles event is both a legacy event and declared in
/sys/devices/cpu_core/events/cpu-cycles. The cycles event is a legacy
event but with no sysfs version.

Add a test that the sysfs version is preferred to the legacy for
cpu-cycles, while for cycles we use the legacy version.

Suggested-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20240103170159.1435753-2-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2024-01-03 17:55:01 -03:00