Having the plane WM/DDB regitster write functions in skl_watermarks.c
is rather annoying when trying to implement DSB based plane updates.
Move them into the respective files that handle all other plane
register writes. Less places where I need to worry about the DSB
vs. MMIO decisions.
The downside is that we spread the wm struct details a bit further
afield. But if that becomes too annoying we can probably abstract
things a bit more with a few extra functions.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-17-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Get rid of skl_ddb_entry_write() and skl_write_wm_level() and
just call intel_de_write_fw() directly.
This is prep work towards DSB based plane updates where these
wrappers are more of a hinderance.
Done with cocci mostly:
@@
expression D, R, L;
@@
- skl_write_wm_level(D, R, L)
+ intel_de_write_fw(D, R, skl_plane_wm_reg_val(L))
@@
expression D, R, B;
@@
- skl_ddb_entry_write(D, R, B)
+ intel_de_write_fw(D, R, skl_plane_ddb_reg_val(B))
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-16-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Currently every skl+ plane register defines some intermediate
macros to calculate the final register offset. Pull all of that
into common macros, simplifying the final register offset stuff
into just five defines:
- raw register offsets for the planes 1 and 2 on pipes A and B
- the final parametrized macro
v2: Rebase
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240513170040.15393-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Rearrange the plane skl+ universal plane register definitions:
- keep everything related to the same register in one place
- sort based on register offset
- unify the whitespace/etc a bit
v2: Define register contents after all offsets (Jani)
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240513165909.15234-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
On SKL+ the watermark/DDB registers are proper per-plane
registers. Move the definitons to their respective files.
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
CC: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Move most of the SKL+ universal plane register definitions
into their own file. Declutters i915_reg.h a bit more.
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
CC: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-3-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Under some circumstances it may happen that the ks8851 Ethernet driver
stops sending data.
Currently the interrupt handler resets the interrupt status flags in the
hardware after handling TX. With this approach we may lose interrupts in
the time window between handling the TX interrupt and resetting the TX
interrupt status bit.
When all of the three following conditions are true then transmitting
data stops:
- TX queue is stopped to wait for room in the hardware TX buffer
- no queued SKBs in the driver (txq) that wait for being written to hw
- hardware TX buffer is empty and the last TX interrupt was lost
This is because reenabling the TX queue happens when handling the TX
interrupt status but if the TX status bit has already been cleared then
this interrupt will never come.
With this commit the interrupt status flags will be cleared before they
are handled. That way we stop losing interrupts.
The wrong handling of the ISR flags was there from the beginning but
with commit 3dc5d44545 ("net: ks8851: Fix TX stall caused by TX
buffer overrun") the issue becomes apparent.
Fixes: 3dc5d44545 ("net: ks8851: Fix TX stall caused by TX buffer overrun")
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Eric Dumazet <edumazet@google.com>
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Paolo Abeni <pabeni@redhat.com>
Cc: Simon Horman <horms@kernel.org>
Cc: netdev@vger.kernel.org
Cc: stable@vger.kernel.org # 5.10+
Signed-off-by: Ronald Wahl <ronald.wahl@raritan.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
When running the bridge IGMP/MLD selftests on debug kernels we can get
spurious errors when setting up the IGMP/MLD exclude timeout tests
because the membership interval is just 3 seconds and the setup has 2
seconds of sleep plus various validations, the one second that is left
is not enough. Increase the membership interval from 3 to 5 seconds to
make room for the setup validation and 2 seconds of sleep.
Fixes: 34d7ecb3d4 ("selftests: net: bridge: update IGMP/MLD membership interval value")
Reported-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Nikolay Aleksandrov <razor@blackwall.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Mediatek LVTS driver (Julien Panis)
- Remove the num_lvts_sensor and cal_offset fields of the
lvts_ctrl_data as they are not used. These are not functional fixes
but slight memory usage fix of the Mediatek LVTS driver (Julien
Panis)
- Fix wrong lvts_ctrl index leading to a NULL pointer dereference in
the Mediatek LVTS driver (Julien Panis)
-----BEGIN PGP SIGNATURE-----
iQEzBAABCAAdFiEEGn3N4YVz0WNVyHskqDIjiipP6E8FAmZDL8IACgkQqDIjiipP
6E9IGwgAlzaIbugHk6qgrkC1s6JhxdAay/sUAk4zJ7WYirtykdWS0/56hh2DL/Ub
VttvTWgDf6W4k/+gaV/hVWjEq5og82n249DSFlJmcAAcvTQ0Stk2LG2TTqRBmfb4
qPKqLoVWlMhDUlbhnNZoS04jApowRitgfOvtC1G0owqkmbzIOKryJJIbvK6VRWpm
qPo7aR99DJW7Cm3lLujyIC41PGb4vKGS2jFFFrf/s69vj40IVHw2jAHOkSJDS+H1
Jro7fTHtlf7eskg4abL9zUzDSJMJTNOTyyj8vJ0524V2I7SavZxbUBoWVfYc/OSf
gWqCZFlY6sWX7k331hhxrpWjdALlyA==
=e53Q
-----END PGP SIGNATURE-----
Merge tag 'thermal-v6.10-rc1-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/thermal/linux
Merge thermal driver fixes for 6.10-rc1 from Daniel Lezcano:
"- Check for a NULL pointer before using it in the probe routine of the
Mediatek LVTS driver (Julien Panis)
- Remove the num_lvts_sensor and cal_offset fields of the
lvts_ctrl_data as they are not used. These are not functional fixes
but slight memory usage fix of the Mediatek LVTS driver (Julien
Panis)
- Fix wrong lvts_ctrl index leading to a NULL pointer dereference in
the Mediatek LVTS driver (Julien Panis)"
* tag 'thermal-v6.10-rc1-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/thermal/linux:
thermal/drivers/mediatek/lvts_thermal: Fix wrong lvts_ctrl index
thermal/drivers/mediatek/lvts_thermal: Remove unused members from struct lvts_ctrl_data
thermal/drivers/mediatek/lvts_thermal: Check NULL ptr on lvts_data
Adds LED and GPIO Control support for 988x, 9887, 9888, 99x0, 9984
based chipsets with on chipset connected led's using WMI Firmware API.
The LED device will get available named as "ath10k-phyX" at sysfs and
can be controlled with various triggers.
Adds also debugfs interface for gpio control.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Reviewed-by: Steve deRosier <derosier@cal-sierra.com>
[kvalo: major reorg and cleanup]
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
[ansuel: rebase and small cleanup]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
Link: https://msgid.link/20230611080505.17393-1-ansuelsmth@gmail.com
Using 'hw_pressure' for local variable name is confusing in regard to the
per-CPU 'hw_pressure' variable that uses the same name:
include/linux/arch_topology.h:DECLARE_PER_CPU(unsigned long, hw_pressure);
... which puts it into a global scope for all code that includes
<linux/topology.h>, shadowing the local variable.
Rename it to avoid compiler confusion & Sparse warnings.
[ mingo: Expanded the changelog. ]
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Lukasz Luba <lukasz.luba@arm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Link: https://lore.kernel.org/r/20240425073709.379016-1-vincent.guittot@linaro.org
Closes: https://lore.kernel.org/oe-kbuild-all/202404250740.VhQQoD7N-lkp@intel.com/
Fixes: d4dbc99171 ("sched/cpufreq: Rename arch_update_thermal_pressure() => arch_update_hw_pressure()")
Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # QC SM8550 QRD
Some MeeGoPad top-set boxes have an ANX7428 Type-C Switch for USB3.1 Gen 1
and DisplayPort over Type-C alternate mode support.
The ANX7428 has a microcontroller which takes care of the PD negotiation
and automatically sets the builtin Crosspoint Switch to send the right
signal to the 4 highspeed pairs of the Type-C connector. It also takes
care of HPD and AUX channel routing for DP alternate mode.
IOW the ANX7428 operates fully autonomous and to the x5-Z8350 SoC
things look like there simple is a USB-3 Type-A connector and a
separate DisplayPort connector. Except that the BIOS does not
power on the ANX7428 at boot (meh).
Add a driver to power on the ANX7428. This driver is added under
drivers/platform/x86 rather than under drivers/usb/typec for 2 reasons:
1. This driver is specifically written to work with how the ANX7428 is
described in the ACPI tables of the MeeGoPad x86 (Cherry Trail) devices.
2. This driver only powers on the ANX7428 and does not do anything wrt
its Type-C functionality. It should be possible to tell the controller
which data- and/or power-role to negotiate and to swap the role(s) after
negotiation but the MeeGoPad top-set boxes always draw their power from
a separate power-connector and they only support USB host-mode. So this
functionality is unnecessary and due to lack of documentation this is
tricky to support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20240514180343.70795-1-hdegoede@redhat.com
Add panel replay selective update support to debugfs status interface. In
case of sink supporting panel replay we will print out:
Sink support: PSR = no, Panel Replay = yes, Panel Replay Selective Update = yes
and PSR mode will look like this if printing out enabled panel replay
selective update:
PSR mode: Panel Replay Selective Update Enabled
Current PSR and panel replay printouts remain same.
Cc: Kunal Joshi <kunal1.joshi@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-13-jouni.hogander@intel.com
Part of intel_psr2_config_valid is valid for panel replay. rename it as
intel_sel_update_config_valid. Split psr2 specific part and name it as
intel_psr2_config_valid.
v3:
- move early transport check to psr2 specific check
- check intel_psr2_config_valid only for non-Panel Replay case
v2:
- use psr2_global_enabled for panel replay as well
- goto unsupported instead of return when global enabled check fails
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-12-jouni.hogander@intel.com
We are re-using PSR module parameters for panel replay. Update module
parameter descriptions with panel replay information:
enable_psr:
-1 (default) == follow what is in VBT
0 == disable PSR/PR
1 == Allow PSR1 and PR full frame update
2 == allow PSR1/PSR2 and PR Selective Update
enable_psr2_sel_fetch
0 == disable selective fetch for PSR and PR
1 (default) == allow selective fetch for PSR PR
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-11-jouni.hogander@intel.com
DP Panel replay uses SRD_STATUS to track it's status despite selective
update mode.
Bspec: 53370, 68920
v4:
- use PSR2_STATUS for eDP Panel Replay
- handle intel_psr_wait_exit_locked as well
v3:
- do not use PSR2_STATUS for PSR1
v2:
- use intel_dp_is_edp to differentiate
- modify debugfs status as well
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-9-jouni.hogander@intel.com
Currently intel_dp_get_su_granularity doesn't support panel replay.
This fix modifies it to support panel replay as well.
v4:
- use drm_dp_dpcd_readb instead of drm_dp_dpcd_read
- ensure return value is 0 if drm_dp_dpcd_readb fails
v3: use correct offset for DP_PANEL_PANEL_REPLAY_CAPABILITY
v2: rely on PSR definitions on common bits
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-8-jouni.hogander@intel.com
Add new boolean to store panel replay selective update support of sink into
intel_psr struct. Detect panel replay selective update support and store
it into this new boolean.
v3: Clear sink_panel_replay_su_support in intel_dp_detect
v2: Merge adding new boolean into this patch
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-7-jouni.hogander@intel.com
We are about to enable Panel Replay Selective update mode. Vsc revision 0x6
for Panel Replay no matter if it is selective update or full frame update
mode. Take this into account when preparing VSC SDP package.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-4-jouni.hogander@intel.com
After setting has_psr for panel replay as well crtc state dump is
improperly printing "psr: enabled" for Panel Replay as well. Fix this by
checking also has_panel_replay.
Fixes: 5afa6e4960 ("drm/i915/psr: Set intel_crtc_state->has_psr on panel replay as well")
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-3-jouni.hogander@intel.com
We are going to reuse has_psr2 for panel_replay as well. Rename it
as has_sel_update to avoid confusion.
v3: do not add has_psr check into psr2 case in intel_dp_compute_vsc_sdp
v2: Rebase
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-2-jouni.hogander@intel.com
The driver tracks the time spent by NPU executing jobs
and shares it through sysfs `npu_busy_time_us` file.
It can be then used by user space applications to monitor device
utilization.
NPU is considered 'busy' starting with a first job submitted
to firmware and ending when there is no more jobs pending/executing.
Signed-off-by: Tomasz Rusinowicz <tomasz.rusinowicz@intel.com>
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240513120431.3187212-13-jacek.lawrynowicz@linux.intel.com
Failed warm boot causes a cold boot that looses FW state and is
equivalent to a recovery or reset, so reset_counter should be
incremented in order for this failure to be detected by tests.
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240513120431.3187212-12-jacek.lawrynowicz@linux.intel.com
Add module parameter that enforces snooping for all NPU accesses,
both through MMU PTEs mappings and through TCU page table walk
override register bits for MMU page walks / configuration access.
Signed-off-by: Wachowski, Karol <karol.wachowski@intel.com>
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240513120431.3187212-10-jacek.lawrynowicz@linux.intel.com
Implement time based Metric Streamer profiling UAPI.
This is a generic mechanism allowing user mode tools to sample
NPU metrics. These metrics are defined by the FW and transparent to
the driver.
The user space can check for this feature by checking
DRM_IVPU_CAP_METRIC_STREAMER driver capability.
Signed-off-by: Tomasz Rusinowicz <tomasz.rusinowicz@intel.com>
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240513120431.3187212-9-jacek.lawrynowicz@linux.intel.com
Add support for HWS (hardware scheduler). It is disabled by default.
The sched_mode module param can be used to enable it.
Each context has multiple command queues with different priorities and
HWS enables priority based execution on the HW/FW side.
The driver in HWS mode has to send a couple additional messages to
initialize HWS and describe command queue priorities.
Signed-off-by: Wachowski, Karol <karol.wachowski@intel.com>
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240513120431.3187212-7-jacek.lawrynowicz@linux.intel.com
Add JSM messages that will be used to implement hardware scheduler.
Most of these messages are used to create and manage HWS specific
command queues.
Signed-off-by: Wachowski, Karol <karol.wachowski@intel.com>
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240513120431.3187212-6-jacek.lawrynowicz@linux.intel.com
Allocate per-context preemption buffers that are required by HWS.
There are two preemption buffers:
* primary - allocated in user memory range (PIOVA accessible)
* secondary - allocated in shave memory range
Signed-off-by: Wachowski, Karol <karol.wachowski@intel.com>
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240513120431.3187212-5-jacek.lawrynowicz@linux.intel.com
Create multiple command queues per engine with different priorities.
The cmdqs are created on-demand and they support 4 priority levels.
These priorities will later be used by the HWS (hardware scheduler).
Signed-off-by: Wachowski, Karol <karol.wachowski@intel.com>
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240513120431.3187212-4-jacek.lawrynowicz@linux.intel.com
