Since kernel 5.3.4 my laptop (ICH8M controller) does not see Kingston
SV300S37A60G SSD disk connected into a SATA connector on wake from
suspend. The problem was introduced in c312ef1763 ("libata/ahci: Drop
PCS quirk for Denverton and beyond"): the quirk is not applied on wake
from suspend as it originally was.
It is worth to mention the commit contained another bug: the quirk is
not applied at all to controllers which require it. The fix commit
09d6ac8dc5 ("libata/ahci: Fix PCS quirk application") landed in 5.3.8.
So testing my patch anywhere between commits c312ef1763 and
09d6ac8dc5 is pointless.
Not all disks trigger the problem. For example nothing bad happens with
Western Digital WD5000LPCX HDD.
Test hardware:
- Acer 5920G with ICH8M SATA controller
- sda: some SATA HDD connnected into the DVD drive IDE port with a
SATA-IDE caddy. It is a boot disk
- sdb: Kingston SV300S37A60G SSD connected into the only SATA port
Sample "dmesg --notime | grep -E '^(sd |ata)'" output on wake:
sd 0:0:0:0: [sda] Starting disk
sd 2:0:0:0: [sdb] Starting disk
ata4: SATA link down (SStatus 4 SControl 300)
ata3: SATA link down (SStatus 4 SControl 300)
ata1.00: ACPI cmd ef/03:0c:00:00:00:a0 (SET FEATURES) filtered out
ata1.00: ACPI cmd ef/03:42:00:00:00:a0 (SET FEATURES) filtered out
ata1: FORCE: cable set to 80c
ata5: SATA link down (SStatus 0 SControl 300)
ata3: SATA link down (SStatus 4 SControl 300)
ata3: SATA link down (SStatus 4 SControl 300)
ata3.00: disabled
sd 2:0:0:0: rejecting I/O to offline device
ata3.00: detaching (SCSI 2:0:0:0)
sd 2:0:0:0: [sdb] Start/Stop Unit failed: Result: hostbyte=DID_NO_CONNECT
driverbyte=DRIVER_OK
sd 2:0:0:0: [sdb] Synchronizing SCSI cache
sd 2:0:0:0: [sdb] Synchronize Cache(10) failed: Result:
hostbyte=DID_BAD_TARGET driverbyte=DRIVER_OK
sd 2:0:0:0: [sdb] Stopping disk
sd 2:0:0:0: [sdb] Start/Stop Unit failed: Result: hostbyte=DID_BAD_TARGET
driverbyte=DRIVER_OK
Commit c312ef1763 dropped ahci_pci_reset_controller() which internally
calls ahci_reset_controller() and applies the PCS quirk if needed after
that. It was called each time a reset was required instead of just
ahci_reset_controller(). This patch puts the function back in place.
Fixes: c312ef1763 ("libata/ahci: Drop PCS quirk for Denverton and beyond")
Signed-off-by: Adam Vodopjan <grozzly@protonmail.com>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Merge series from Peter Ujfalusi <peter.ujfalusi@linux.intel.com>:
This series contails 2 patches to fix device suspend after a firmware
crash and another patch to allow reading the FW state from debugfs.
If xSPI is in x2/x4/x8 mode to calculate busy
cycles, busy bits count must be divided by the number
of lanes.
If opcommand is using 8 busy bits, but SPI is
in x4 mode, there will be only 2 busy cycles.
Signed-off-by: Witold Sadowski <wsadowski@marvell.com>
Reviewed-by: Chandrakala Chavva <cchavva@marvell.com>
Reviewed-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
Link: https://lore.kernel.org/r/20221219144254.20883-2-wsadowski@marvell.com
Signed-off-by: Mark Brown <broonie@kernel.org>
If the irq is enabled after the spi si registered, there can be a race
with the initialization of the devices on the spi bus.
Eg:
mtk-spi 1100a000.spi: spi-mem transfer timeout
spi-nor: probe of spi0.0 failed with error -110
Unable to handle kernel NULL pointer dereference at virtual address
0000000000000010
...
Call trace:
mtk_spi_can_dma+0x0/0x2c
Fixes: c6f7874687 ("spi: mediatek: Enable irq when pdata is ready")
Reported-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/20221225-mtk-spi-fixes-v1-0-bb6c14c232f8@chromium.org
Signed-off-by: Mark Brown <broonie@kernel.org>
The maximum name length for a platform_device_id entry is 20 characters
including the trailing NUL byte. The sof_nau8825.c file exceeds that,
which causes an obscure error message:
sound/soc/intel/boards/snd-soc-sof_nau8825.mod.c:35:45: error: illegal character encoding in string literal [-Werror,-Winvalid-source-encoding]
MODULE_ALIAS("platform:adl_max98373_nau8825<U+0018><AA>");
^~~~
include/linux/module.h:168:49: note: expanded from macro 'MODULE_ALIAS'
^~~~~~
include/linux/module.h:165:56: note: expanded from macro 'MODULE_INFO'
^~~~
include/linux/moduleparam.h:26:47: note: expanded from macro '__MODULE_INFO'
= __MODULE_INFO_PREFIX __stringify(tag) "=" info
I could not figure out how to make the module handling robust enough
to handle this better, but as a quick fix, using slightly shorter
names that are still unique avoids the build issue.
Fixes: 8d0872f623 ("ASoC: Intel: add sof-nau8825 machine driver")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20221221132515.2363276-1-arnd@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
The snd-soc-sof_nau8825.ko module fails to link unless the
sof_realtek_common support is also enabled:
ERROR: modpost: "sof_rt1015p_codec_conf" [sound/soc/intel/boards/snd-soc-sof_nau8825.ko] undefined!
ERROR: modpost: "sof_rt1015p_dai_link" [sound/soc/intel/boards/snd-soc-sof_nau8825.ko] undefined!
Fixes: 8d0872f623 ("ASoC: Intel: add sof-nau8825 machine driver")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20221221132559.2402341-1-arnd@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
This patch adds the driver data for two nau8318 speaker amplifiers on
SSP1 and nau8825 on SSP0 for ADL platform.
The nau8315 and nau8318 are both Nuvoton Amp chips. They use the same
Amp driver nau8315.c. The acpi_device_id for nau8315 is "NVTN2010",
for nau8318 is "NVTN2012".
The nau8825 is one of Nuvoton headset codec, and its acpi_device_id is
"10508825".
Signed-off-by: Ajye Huang <ajye_huang@compal.corp-partner.google.com>
Acked-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20221222042624.557869-1-ajye_huang@compal.corp-partner.google.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Razer Blade 14 (2022) - RZ09-0427 needs the quirk to enable the built in microphone
Signed-off-by: Wim Van Boven <wimvanboven@gmail.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20221216081828.12382-1-wimvanboven@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Support configuration with SoundWire RT1318 amplifiers on link1 and
link2, and RT711 on link0 for headphone/headset. This product does
not support local microphones.
Signed-off-by: Gongjun Song <gongjun.song@intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20221226010917.2632973-2-yung-chuan.liao@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Support configuration with SoundWire RT1316 amplifiers on link0 and
link1, and RT711 on link2 for headphone/headset. This product does
not support local microphones.
Signed-off-by: Gongjun Song <gongjun.song@intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20221226010917.2632973-1-yung-chuan.liao@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Dpi output needs to adjust the output format to dual edge for MT8186.
Co-developed-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://patchwork.kernel.org/project/linux-mediatek/patch/1666577099-3859-3-git-send-email-xinlei.lee@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
When it fails to allocate fragment, it does not free and return error.
And check the pointer inappropriately.
Fixed merge conflicts with
commit 618887768b ("kunit: update NULL vs IS_ERR() tests")
Shuah Khan <skhan@linuxfoundation.org>
Signed-off-by: YoungJun.park <her0gyugyu@gmail.com>
Reviewed-by: David Gow <davidgow@google.com>
Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
This adds support for the StarFive JH7110 SoC which also
features this SiFive cache controller.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This cache controller is also used on the StarFive JH7110 SoC.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Add device tree bindings for the StarFive JH7110 RISC-V SoC
and the VisionFive 2 board equipped with it.
VisionFive 2 board has version A and version B, which are
different in gmac and phy chip. The version A board has one
1000Mbps and one 100Mbps Ethernet ports while the version B
board has two 1000Mbps Ethernet ports.
Link: https://doc-en.rvspace.org/Doc_Center/jh7110.html
Link: https://doc-en.rvspace.org/Doc_Center/visionfive_2.html
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Radxa E25 is a network application carrier board for the Radxa CM3
Industrial (CM3I) SoM, which is based on the Rockchip RK3568 SoC.
It has the following features:
- MicroSD card socket, on board eMMC flash
- 2x 2.5GbE Realtek RTL8125B Ethernet transceiver
- 1x USB Type-C port (Power and Serial console)
- 1x USB 3.0 OTG port
- mini PCIe socket (USB or PCIe)
- ngff PCIe socket (USB or SATA)
- 1x User LED and 16x RGB LEDs
- 26-pin expansion header
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20221209102524.129367-3-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Radxa CM3 Industrial (CM3I) is an System on Module made by Radxa
based on the Rockchip RK3568 SoC. The first carrier board supported
is the Radxa E25. Add devicetree binding documentation for it.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221209102524.129367-2-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Neural Compute Module 2(Neu2) IO board is an industrial form factor
evaluation board from Edgeble AI.
General features:
- microSD slot
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC battery slot
- 40-pin expansion
Neu2 needs to mount on top of this IO board in order to create complete
Edgeble Neural Compute Module 2(Neu2) IO platform.
Add support for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20221129075424.189655-9-jagan@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module
based on Rockchip RV1126 from Edgeble AI.
General features:
- Rockchip RV1126
- 2/4GB LPDDR4
- 8/16/32GB eMMC
- 2x MIPI CSI2 FPC connector
- Fn-link 8223A-SR WiFi/BT
Industrial grade (-40 °C to +85 °C) version of the same class of module
called Neu2k powered with Rockchip RV1126K.
Neu2 needs to mount on top of Edgeble IO boards for creating complete
platform solutions.
Add support for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20221129075424.189655-8-jagan@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module
based on Rockchip RV1126 from Edgeble AI.
Edgeble Neural Compute Module 2(Neu2) IO board is an industrial
form factor evaluation board from Edgeble AI.
Neu2 needs to mount on top of this IO board in order to create complete
Edgeble Neural Compute Module 2(Neu2) IO platform.
Add dt-bindings for it.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20221129075424.189655-7-jagan@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Edgeble AI is an Artificial Intelligence company with a focus on
deploying Neural Acceleration principles at the Edge.
Add vendor prefix for it.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20221129075424.189655-6-jagan@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
RV1126 is a high-performance vision processor SoC for IPC/CVR,
especially for AI related application.
It is based on quad-core ARM Cortex-A7 32-bit core which integrates
NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core
and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16
hybrid operation and computing power is up to 2.0TOPs.
This patch add basic core dtsi support.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20221129075424.189655-5-jagan@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add pinctrl definitions for Rockchip RV1126.
From RK3568 on-wards pinctrl configurations are maintained
in common conf file rockchip-pinconf.dtsi and it is available
in arm64 path (arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi).
So, include the same conf file to RV1126 pinctrl from arm64 path.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20221129075424.189655-4-jagan@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
While not documented, schema checks for single dtb targets mostly work
already by setting 'CHECK_DTBS=1'. However, the dependencies are not
handled and it only works if 'make dt_bindings_check' was run first and
generated processed-schema.json. In addition, changing a binding file
doesn't cause the schema to be rebuilt and dtb to be revalidated.
Making this work turns out to be simple. Whenever CHECK_DTBS is set,
make 'dt_binding_check' a 'dtbs_prepare' dependency.
I reimplemented here what Masahiro had originally come up with a while
back.
Suggested-by: Masahiro Yamada <masahiroy@kernel.org>
Acked-by: Masahiro Yamada <masahiroy@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20221220013233.2890335-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Add DT binding schema for components belonging to the platform-specific
AHCI glue layer implemented in UniPhier SoCs.
This AHCI glue layer works as a sideband logic for the host controller,
including core reset, PHYs, and some signals to the controller.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221213082449.2721-18-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>
Add DT binding schema for components belonging to the platform-specific
DWC3 USB glue layer implemented in UniPhier SoCs.
This USB glue layer works as a sideband logic for the host controller,
including core reset, vbus control, PHYs, and some signals to the
controller.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221213082449.2721-17-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>
Add devicetree binding schema for the ADAMV block implemented on Socionext
Uniphier SoCs.
The ADAMV block is analog signal amplifier that is a part of the external
video and audio I/O system. This block is implemented on LD11 and LD20,
and this is defined for controlling audio I/O reset only.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221213082449.2721-16-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>
Add devicetree binding schema for the SD interface block implemented on
Socionext Uniphier SoCs.
This SD interface block is attached outside SDHC, and has some SD related
functions such as clock control, reset control, mode switch, and so on.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221213082449.2721-15-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>
Add devicetree binding schema for the media I/O block implemented on
Socionext Uniphier SoCs. This block is implemented on LD4, sLD8, Pro4,
and LD11 SoCs.
Media I/O block implemented on Socionext UniPhier SoCs is an integrated
component of the stream type peripherals including SD, USB2.0, eMMC,
and MIO-DMAC.
Media I/O block has a common logic to control the component.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221213082449.2721-14-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>
Add devicetree binding schema for the peripheral block implemented on
Socionext Uniphier SoCs.
Peripheral block implemented on Socionext UniPhier SoCs is an integrated
component of the peripherals including UART, I2C/FI2C, and SCSSI.
Peripheral block has some function logics to control the component.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221213082449.2721-13-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>
Add devicetree binding schema for the SoC-glue logic debug part
implemented on Socionext Uniphier SoCs.
This SoC-glue logic debug part is a set of miscellaneous function
registers handling signals for specific devices outside system
components, and also has multiple functions such as efuse, debug unit,
several monitors for specific SoC, and so on.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221213082449.2721-12-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>
Add devicetree binding schema for the SoC-glue logic implemented on
Socionext Uniphier SoCs.
This SoC-glue logic is a set of miscellaneous function registers
handling signals for specific devices outside system components,
and also has multiple functions such as I/O pinmux, usb-phy, debug,
clock-mux for a specific SoC, and so on.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221213082449.2721-11-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>
Add devicetree binding schema for the system controller implemented on
Socionext Uniphier SoCs.
This system controller has multiple functions such as clock control,
reset control, internal watchdog timer, thermal management, and so on.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221213082449.2721-10-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>
Prior to adding dt-bindings for SoC-dependent controllers, rename the
parent node to the generic name in the example.
And drop a parent node of the nvmem as it is not directly necessary here.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221213082449.2721-9-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>
Prior to adding dt-bindings for SoC-dependent controllers, rename the
phy nodes and their parent nodes to the generic names in the example.
And drop parent nodes of each phy as they are not directly necessary here.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>]
Link: https://lore.kernel.org/r/20221213082449.2721-8-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>
Prior to adding dt-bindings for SoC-dependent controllers, rename the
thermal node and its parent node to the generic names in the example.
And drop a parent node of the thermal-sensor as it is not directly
necessary.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221213082449.2721-7-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>
Drop a parent node of the watchdog as it is not directly necessary.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221213082449.2721-6-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>
Drop a parent node of the regulator as it is not directly necessary.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221213082449.2721-5-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>
Drop parent node of the pinctrl as it is not directly necessary, and
add more examples, that is "groups", "function", and a child node to set
pin attributes, to express this pinctrl node in detail.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20221213082449.2721-4-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>
Prior to adding dt-bindings for SoC-dependent controllers, rename the
reset nodes to the generic names in the example.
And drop redundant examples and a parent node of the reset as it is not
directly necessary.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221213082449.2721-3-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>
Prior to adding dt-bindings for SoC-dependent controllers, rename the
clock nodes to the generic names in the example.
And drop redundant examples and a parent node of the clock as it is not
directly necessary.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221213082449.2721-2-hayashi.kunihiko@socionext.com
Signed-off-by: Rob Herring <robh@kernel.org>
A common practice is to grep for "WARNING" or "ERROR" text in the report
output from a Coccinelle semantic patch script. So, include the text
"WARNING: " in the report output generated by the semantic patch for
desired filtering of the output. Also improves the readability of the
output. Here is an example of the old and new outputs reported:
xyz_file.c:131:39-40: atomic_add_unless
xyz_file.c:131:39-40: WARNING: atomic_add_unless
xyz_file.c:196:6-25: atomic_dec_and_test variation before object free at line 208.
xyz_file.c:196:6-25: WARNING: atomic_dec_and_test variation before object free at line 208.
Signed-off-by: Deepak R Varma <drv@mailo.com>
Acked-by: Julia Lawall <Julia.Lawall@inria.fr>
