While we are calling intel_dp_aux_transfer() with msg->size=0 whenever
msg->buffer is NULL, passing NULL to memcpy() is undefined according to
the ISO C standard. I haven't found any notes about this in the GNU C's
or the kernel's documentation of the function and can't imagine what it
would do with the NULL ptr. To better document this use of the
parameters it still make sense to add an explicit check for this to the
code.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: David Weinehall <david.weinehall@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1454071949-24677-1-git-send-email-imre.deak@intel.com
Add PCIIDs for new versions of the SOC, based on BSpec. Also add the
name of the versions as code comment where this is available. The new
versions don't have any changes visible to the kernel driver.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453989852-13569-1-git-send-email-imre.deak@intel.com
futex.h's futex_atomic_cmpxchg_inatomic() does not use the
__futex_atomic_op() macro and needs its own PAN toggling. This was missed
when the feature was implemented.
Fixes: 338d4f49d6 ("arm64: kernel: Add support for Privileged Access Never")
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
intel_pt_process_auxtrace_info() creates a pt->unknown_thread thread
that eventually needs to be freed by the last thread__put() on it, when
its refcount hits zero, which may happen in
intel_pt_process_auxtrace_info() error handling path and triggers the
following segfault, which would happen as well at intel_pt_free, when
tools using this intel_pt codebase frees up resources:
# perf record -I -e intel_pt/tsc=1,noretcomp=1/u /bin/ls
0 a anaconda-ks.cfg bin perf.data perf.data.old perf-f23-bringup.todo
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.217 MB perf.data ]
#
# perf script -F event,comm,pid,tid,time,addr,ip,sym,dso,iregs
Samples for 'instructions:u' event do not have IREGS attribute set. Cannot print 'iregs' field.
intel_pt_synth_events: failed to synthesize 'instructions' event type
Segmentation fault (core dumped)
#
The problem is: there's a union in 'struct thread' combines a list_head
and a rb_node. The standard life cycle of a thread is: init rb_node in
the constructor, insert it into machine->threads rbtree using rb_node,
move it to machine->dead_threads using list_head, clean in the last
thread__put: list_del_init(&thread->node).
In the above command, it clean a thread before adding it into list,
causes the above segfault.
Since pt->unknown_thread will never live in an rbtree, initialize its
list node so that when list_del_init() is done on it we don't segfault.
After this patch:
# perf script -F event,comm,pid,tid,time,addr,ip,sym,dso,iregs
Samples for 'instructions:u' event do not have IREGS attribute set. Cannot print 'iregs' field.
intel_pt_synth_events: failed to synthesize 'instructions' event type
0x248 [0x88]: failed to process type: 70
#
Reported-by: Tong Zhang <ztong@vt.edu>
Reported-by: Wang Nan <wangnan0@huawei.com>
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Link: http://lkml.kernel.org/r/1454296865-19749-1-git-send-email-wangnan0@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
The range of set_memory_* is currently restricted to the module address
range because of difficulties in breaking down larger block sizes.
vmalloc maps PAGE_SIZE pages so it is safe to use as well. Update the
function ranges and add a comment explaining why the range is restricted
the way it is.
Suggested-by: Laura Abbott <labbott@fedoraproject.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
On SKL and KBL we can have pipe A/B/C disabled by fuse settings. The
pipes must be fused in descending order (e.g. C, B+C, A+B+C). We simply
decrease info->num_pipes if we find a valid fused out config.
v2: Don't store the pipe disabled mask in device info (Damien)
v3: Don't check FUSE_STRAP register for pipe c disabled
Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[Jani: fixed some checkpatch indentation complaints]
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453300280-10661-1-git-send-email-patrik.jakobsson@linux.intel.com
The change from cur_tp to the function
minstrel_get_tp_avg/minstrel_ht_get_tp_avg changed the unit used for the
current throughput. For example in minstrel_ht the correct
conversion between them would be:
mrs->cur_tp / 10 == minstrel_ht_get_tp_avg(..).
This factor 10 must also be included in the calculation of
minstrel_get_expected_throughput and minstrel_ht_get_expected_throughput to
return values with the unit [Kbps] instead of [10Kbps]. Otherwise routing
algorithms like B.A.T.M.A.N. V will make incorrect decision based on these
values. Its kernel based implementation expects expected_throughput always
to have the unit [Kbps] and not sometimes [10Kbps] and sometimes [Kbps].
The same requirement has iw or olsrdv2's nl80211 based statistics module
which retrieve the same data via NL80211_STA_INFO_TX_BITRATE.
Cc: stable@vger.kernel.org
Fixes: 6a27b2c40b ("mac80211: restructure per-rate throughput calculation into function")
Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Patch fixes this splat
BUG: KASAN: slab-out-of-bounds in minstrel_ht_update_stats.isra.7+0x6e1/0x9e0
[mac80211] at addr ffff8800cee640f4 Read of size 4 by task swapper/3/0
Signed-off-by: Konstantin Khlebnikov <koct9i@gmail.com>
Link: http://lkml.kernel.org/r/CALYGNiNyJhSaVnE35qS6UCGaSb2Dx1_i5HcRavuOX14oTz2P+w@mail.gmail.com
Acked-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Sparse reports the following warnings for structures and functions that
should be declared static:
drivers/clk/tegra/clk-tegra-super-gen4.c:70:35: warning: symbol
'tegra_super_gen_info_gen4' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra-super-gen4.c:96:35: warning: symbol
'tegra_super_gen_info_gen5' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra-super-gen4.c:174:13: warning: symbol
'tegra_super_clk_init' was not declared. Should it be static?
Fix this by making the above static.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Sparse reports the following warnings for functions in clk-tegra210.c
that should be declared as static:
drivers/clk/tegra/clk-tegra210.c:460:6: warning: symbol
'tegra210_pllcx_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:485:6: warning: symbol
'_pllc_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:490:6: warning: symbol
'_pllc2_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:495:6: warning: symbol
'_pllc3_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:500:6: warning: symbol
'_plla1_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:510:6: warning: symbol
'tegra210_plla_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:562:6: warning: symbol
'tegra210_plld_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:701:6: warning: symbol
'tegra210_plld2_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:709:6: warning: symbol
'tegra210_plldp_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:722:6: warning: symbol
'tegra210_pllc4_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:731:6: warning: symbol
'tegra210_pllre_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:844:6: warning: symbol
'tegra210_pllx_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:904:6: warning: symbol
'tegra210_pllmb_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:963:6: warning: symbol
'tegra210_pllp_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:1025:6: warning: symbol
'tegra210_pllu_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:1215:15: warning: symbol
'tegra210_clk_adjust_vco_min' was not declared. Should it be static?
Fix this by declaring the above as static.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Sparse generates the following warning for the pll_m params structure:
drivers/clk/tegra/clk-tegra210.c:1569:10: warning: Initializer entry
defined twice
drivers/clk/tegra/clk-tegra210.c:1570:10: also defined here
Fix this by correcting the index for the MISC1 register.
Fixes: b31eba5ff3f7 ("clk: tegra: Add support for Tegra210 clocks")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
the code directly uses the bit number. Therefore, use the definition,
PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
If the pll_u is not configured by the bootloader, then on kernel boot the
following warning is seen:
clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock
tegra_init_from_table: Failed to enable pll_u_out1
------------[ cut here ]------------
WARNING: at drivers/clk/tegra/clk.c:269
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.0-rc4-next-20151214+ #1
Hardware name: NVIDIA Tegra210 P2371 reference board (E.1) (DT)
task: ffffffc0bc0a0000 ti: ffffffc0bc0a8000 task.ti: ffffffc0bc0a8000
PC is at tegra_init_from_table+0x140/0x164
LR is at tegra_init_from_table+0x140/0x164
pc : [<ffffffc0008fee78>] lr : [<ffffffc0008fee78>] pstate: 80000045
sp : ffffffc0bc0abd50
x29: ffffffc0bc0abd50 x28: ffffffc00090b8a8
x27: ffffffc000a06000 x26: ffffffc0bc019780
x25: ffffffc00086a708 x24: ffffffc00086a790
x23: ffffffc0006d7188 x22: ffffffc0bc010000
x21: 000000000000016e x20: ffffffc0bc00d100
x19: ffffffc000944178 x18: 0000000000000007
x17: 000000000000000e x16: 0000000000000001
x15: 0000000000000007 x14: 000000000000000e
x13: 0000000000000013 x12: 000000000000001a
x11: 000000000000004d x10: 0000000000000750
x9 : ffffffc0bc0a8000 x8 : ffffffc0bc0a07b0
x7 : 0000000000000001 x6 : 0000000002d5f0f8
x5 : 0000000000000000 x4 : 0000000000000000
x3 : 0000000000000002 x2 : ffffffc000996724
x1 : 0000000000000000 x0 : 0000000000000032
---[ end trace cbd20ae519e92ced ]---
Call trace:
[<ffffffc0008fee78>] tegra_init_from_table+0x140/0x164
[<ffffffc000900ac8>] tegra210_clock_apply_init_table+0x20/0x28
[<ffffffc0008fec40>] tegra_clocks_apply_init_table+0x18/0x24
[<ffffffc00008291c>] do_one_initcall+0x90/0x194
[<ffffffc0008cfab0>] kernel_init_freeable+0x148/0x1e8
[<ffffffc000636bb0>] kernel_init+0x10/0xdc
[<ffffffc000085cd0>] ret_from_fork+0x10/0x40
clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock
tegra_init_from_table: Failed to enable pll_u_out2
------------[ cut here ]------------
pll_u can be either controlled by software or hardware and this is
selected via the OVERRIDE bit in the pll_u base register. In the function
tegra210_pll_init(), the OVERRIDE bit for pll_u is cleared, which selects
hardware control of the pll. However, at the same time the pll_u clocks
are populated in the init_table for tegra210 and so software will try to
configure the pll_u if it is not already configured and hence, the above
warning is seen when the pll fails to lock. Remove the pll_u clocks from
the init_table so that software does not try to configure this pll on
boot.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The EMC clock sources for Tegra210 currently incorrectly include pll_c2
and pll_c3. However, both of these should have been pll_mb as shown in
the TRM. If Tegra210 happens to be configured such that the pll_mb is the
default clock for the EMC, as configured by the bootloader, then this will
cause a system hang on boot. This is because the kernel will disable the
pll_mb when disabling unused clock as it appears to be unused when it is
not.
Also add the additional pll_p clock source for the EMC.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The APB2APE clock for the audio subsystem is required for powering up the
audio power domain and accessing the various modules in this subsystem on
Tegra210 devices. Add this clock for Tegra210.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
for_each_child_of_node() performs an of_node_get() on each iteration, so
before breaking out of the loop an of_node_put() is required.
Found using Coccinelle. The semantic patch used for this is as follows:
// <smpl>
@@
expression e;
local idexpression child;
@@
for_each_child_of_node(root, child) {
... when != of_node_put(child)
when != e = child
(
return child;
|
+ of_node_put(child);
? return ...;
)
...
}
// </smpl>
Signed-off-by: Amitoj Kaur Chawla <amitoj1606@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The PLLE SS coefficients are different between Tegra210 and Tegra114.
Add SoC generation specific versions for Tegra114 and Tegra210 and use
them in their respective ->enable() callbacks.
Signed-off-by: Mark Kuo <mkuo@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
While enabling PLLE on both Tegra114 and Tegra210, we should be clearing
PLLE_MISC_VREG_BG_CTRL_MASK and PLLE_MISC_VREG_CTRL_MASK not setting
them. This patch fixes both places where we incorrectly set instead of
cleared those bits.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Software should not disable PLLE if PLLE is already put under hardware
control.
Signed-off-by: Mark Kuo <mkuo@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The logic for calculating the input rate used when figuring out the
proper dynamic steps for pllx was incorrect. It is supposed to be
calculated using parent_rate / m but it was just using the parent rate
directly, therefore using the wrong step values.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Since the ->enable() callback is called with a spinlock held, we cannot
call potentially blocking functions such as clk_get_rate() or
clk_get_parent(), so use the unlocked versions instead.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
[rklein: Adapted from ChromeOS patch, removing pllu_enable cleanup as
it isn't present upstream]
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
When adding the nvenc clock, it was partially named msenc in the code.
Since the msenc clock isn't present in Tegra210 and has been replaced by
the nvenc clock, its misleading to see it present. Therefore, properly
rename it.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Some register for PLLM and PLLMB were named MISC0 but according to the
TRM, they have different names. Sync up the names to make it easier to
understand which register they are really referring to.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The Allwinner sunxi specific interrupt controller cannot be compiled
for any architecture except arm:
drivers/irqchip/irq-sun4i.c:25:26: fatal error: asm/mach/irq.h: No such file or directory
compilation terminated.
It turns out that this header is actually not needed for the driver, so remove
it and allow compilation for other architectures like arm64.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: linux-sunxi@googlegroups.com
Link: http://lkml.kernel.org/r/1454348370-3816-2-git-send-email-andre.przywara@arm.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Fix this typo, consequently used over both files :)
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Lars-Peter Clausen <lars@metafoo.de>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Archit Taneja <architt@codeaurora.org>
This register includes a counter which is decremented by the chip on I2C
failures. Also, it is reset when powering down.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Archit Taneja <architt@codeaurora.org>
The interrupts for EDID_READY or DDC_ERROR were never enabled in this
driver, so reading EDID always timed out when chip was powered down and
interrupts were used. Fix this and also remove clearing the interrupt
flags, they are cleared in POWER_DOWN mode anyhow (unlike the interrupt
enable flags) according to docs and my tests.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Archit Taneja <architt@codeaurora.org>
The datatype __kernel_time_t is u32 on 32bit platform, so its subject to
overflows in the timeval/timespec to cputime conversion.
Currently the following functions are affected:
1. setitimer()
2. timer_create/timer_settime()
3. sys_clock_nanosleep
This can happen on MIPS32 and ARM32 with "Full dynticks CPU time accounting"
enabled, which is required for CONFIG_NO_HZ_FULL.
Enforce u64 conversion to prevent the overflow.
Fixes: 31c1fc8187 ("ARM: Kconfig: allow full nohz CPU accounting")
Signed-off-by: zengtao <prime.zeng@huawei.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Cc: <fweisbec@gmail.com>
Cc: stable@vger.kernel.org
Link: http://lkml.kernel.org/r/1454384314-154784-1-git-send-email-prime.zeng@huawei.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
A83T has similar bus gates that of H3, including single gating register has
different clock parent.
As per H3 and A83T datasheet, usbhost is under AHB2.
However,below shows allwinner source code assignment:
bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
bits 29, 30, 31(ohci0,1,2) => AHB2 for H3.
until, this confusion is cleared keep it H3 way.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
APB0 is part of PRCM, and is compatible with earlier SOCs.
apb0 gates controls R_PIO, R_UART, R_RSB, etc clocks.
This patch adds support for APB0 gates for A83T.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The device power usage counter is increased by pm_runtime_get_noresume
but isn't decreased in err_add_host error path.
Fix this issue by calling pm_runtime_put_noidle() in the error path to
restore the device's power usage counter.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Fixes: f5f17813ae ("mmc: sdhci-of-at91: add PM support)
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Some of the parameter like tx/rx chain mask, number of htt tx desc,
qcache active peer count, etc goes via wmi init cmd to qca4019 firmware
are different.
To make use of 10.4 gen_init function for qca4019, change wmi service
ready handler and 10.4 wmi init functions to adapt qca4019 specific
init values.
Signed-off-by: Raja Mani <rmani@qti.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
Add a new entry in hw_params_list for qca4019 with list of
it's own details.
Signed-off-by: Raja Mani <rmani@qti.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
Abstraction layer for vdev subtype is added to solve
subtype mismatch and to give flexible compatibility
among different firmware revisions.
For instance, 10.2 and 10.4 firmware has different
definition of their vdev subtypes for Mesh.
10.4 defined subtype 6 for 802.11s Mesh while 10.2 uses 5.
Hence use the abstraction API to get right subtype to use.
Signed-off-by: Peter Oh <poh@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
Interface type P2P_GO can be checked by either arvif->vdev_type
and arvif->vdev_subtype or vif->type and vif->p2p.
Use later one to avoid more cpu consumption that could happen
when subtype abstraction layer change is introduced.
Signed-off-by: Peter Oh <poh@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
Update 10.4 WMI service map to sync to the latest 10.4 firmware
as of 1/20/2016.
Signed-off-by: Peter Oh <poh@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
WMI_10_4_SERVICE_MESH bit is for non IEEE802.11s Mesh.
Hence rename it to WMI_10_4_SERVICE_MESH_NON_11S.
Also add _11S as post-fix to each of WMI_SERVICE_MESH and
WMI_VDEV_SUBTYPE_MESH specifying the service is for 11s Mesh.
This will help users to distinguish 11s Mesh from non 11s Mesh.
Signed-off-by: Peter Oh <poh@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
Tx vring needs to be enlarged to get better
performance for traffic over 2Gbps.
Signed-off-by: Hamad Kadmany <qca_hkadmany@qca.qualcomm.com>
Signed-off-by: Maya Erez <qca_merez@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
In case there are multiple WMI commands with the same reply_id,
the following scenario can occur:
- Driver sends the first command to the device
- The reply didn’t get on time and there is timeout
- Reply_id, reply_buf and reply_size are set to 0
- Driver sends second wmi command with the same reply_id as the first
- Driver sets wil->reply_id
- Reply for the first wmi command arrives and handled by wmi_recv_cmd
- As its ID fits the reply_id but the reply_buf is not set yet it is
handled as a reply with event handler, and WARN_ON is printed
This patch guarantee atomic setting of all the reply variables and
prevents the above scenario.
Signed-off-by: Maya Erez <qca_merez@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
cfg80211_ops.disconnect() should wait for disconnect flow to
complete. If it does not, internal state becomes out of sync with
one in cfg80211. If one does stress test connect/disconnect
sequence, cfg80211 will issue next connect before disconnect
completed internally.
Signed-off-by: Vladimir Kondratiev <qca_vkondrat@qca.qualcomm.com>
Signed-off-by: Maya Erez <qca_merez@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
wil_tx_vring locks the vring_tx_data lock before accessing the TX
vring to check if it is enabled and valid for use.
In case of quick disconnect / connect events for the same station,
spin_lock(&txdata->lock) can be called during the lock initialization
in the vring init function.
To prevent such a race, the TX vrings spin lock should be initialized
once during wil6210 driver initialization.
Signed-off-by: Maya Erez <qca_merez@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
The commit fixing the conversion of pxamci to slot-gpio API fixed the
inverted the logic of the read-only gpio. Unfortunately, the commit was
tested on a non-inverted gpio, and not on the inverted one. And the fix
did work partially, by luck.
This is the remaining missing part of the fix, trivial but still necessary.
Fixes: Fixes: 26d49fe719 ("mmc: pxamci: fix read-only gpio detection polarity")
Reported-by: Andrea Adami <andrea.adami@gmail.com>
Tested-by: Andrea Adami <andrea.adami@gmail.com>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: stable@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
