linux

mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ synced 2026-11-10 20:48:12 +00:00

Author	SHA1	Message	Date
Uwe Kleine-König	f00b45db02	clk: Switch back to struct platform_driver::remove() After commit `0edb555a65` ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all clk drivers to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://lore.kernel.org/r/20240909144026.870565-2-u.kleine-koenig@baylibre.com Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-09-21 14:12:05 -07:00
Stephen Boyd	1b189f71e1	Merge branches 'clk-devm', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into clk-next * clk-devm: clk: provide devm_clk_get_optional_enabled_with_rate() clk: fixed-rate: add devm_clk_hw_register_fixed_rate_parent_data() * clk-samsung: clk: samsung: add top clock support for ExynosAuto v920 SoC clk: samsung: clk-pll: Add support for pll_531x dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings clk: samsung: exynos7885: Add USB related clocks to CMU_FSYS clk: samsung: clk-pll: Add support for pll_1418x clk: samsung: exynosautov9: add dpum clock support dt-bindings: clock: exynosautov9: add dpum clock clk: samsung: exynos7885: Add missing MUX clocks from PLLs in CMU_TOP clk: samsung: exynos7885: Update CLKS_NR_FSYS after bindings fix dt-bindings: clock: exynos7885: Add indices for USB clocks dt-bindings: clock: exynos7885: Add CMU_TOP PLL MUX indices dt-bindings: clock: exynos7885: Fix duplicated binding clk: samsung: exynos850: Add TMU clock dt-bindings: clock: exynos850: Add TMU clock * clk-rockchip: dt-bindings: clock, reset: fix top-comment indentation rk3576 headers clk: rockchip: remove unused mclk_pdm0_p/pdm0_p definitions clk: rockchip: fix error for unknown clocks clk: rockchip: rk3588: drop unused code clk: rockchip: Add clock controller for the RK3576 clk: rockchip: Add new pll type pll_rk3588_ddr dt-bindings: clock, reset: Add support for rk3576 dt-bindings: clock: rockchip,rk3588-cru: drop unneeded assigned-clocks clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_p dt-bindings: clock: rockchip: remove CLK_NR_CLKS and CLKPMU_NR_CLKS clk: rockchip: rk3399: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage clk: rockchip: rk3368: Drop CLK_NR_CLKS usage clk: rockchip: rk3328: Drop CLK_NR_CLKS usage clk: rockchip: rk3308: Drop CLK_NR_CLKS usage clk: rockchip: rk3288: Drop CLK_NR_CLKS usage clk: rockchip: rk3228: Drop CLK_NR_CLKS usage clk: rockchip: rk3036: Drop CLK_NR_CLKS usage clk: rockchip: px30: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228 * clk-qcom: (47 commits) clk: qcom: videocc-sm8550: Use HW_CTRL_TRIGGER flag for video GDSC's clk: qcom: dispcc-sm8250: use special function for Lucid 5LPE PLL clk: qcom: dispcc-sm8250: use CLK_SET_RATE_PARENT for branch clocks clk: qcom: ipq5332: Use icc-clk for enabling NoC related clocks clk: qcom: ipq5332: Register gcc_qdss_tsctr_clk_src dt-bindings: usb: qcom,dwc3: Update ipq5332 clock details dt-bindings: interconnect: Add Qualcomm IPQ5332 support clk: qcom: gcc-msm8998: Add Q6 BIMC and LPASS core, ADSP SMMU clocks dt-bindings: clock: gcc-msm8998: Add Q6 and LPASS clocks definitions clk: qcom: Fix SM_CAMCC_8150 dependencies clk: qcom: gcc-sm8150: De-register gcc_cpuss_ahb_clk_src clk: qcom: gcc-sc8180x: Fix the sdcc2 and sdcc4 clocks freq table clk: qcom: gcc-sc8180x: Add GPLL9 support dt-bindings: clock: qcom: Add GPLL9 support on gcc-sc8180x clk: qcom: gcc-sc8180x: Register QUPv3 RCGs for DFS on sc8180x clk: qcom: clk-rpmh: Fix overflow in BCM vote dt-bindings: clock: qcom: Drop required-opps in required on SM8650 camcc dt-bindings: clock: qcom: Drop required-opps in required on sm8650 videocc dt-bindings: clock: qcom,qcs404-turingcc: convert to dtschema dt-bindings: clock: Add x1e80100 LPASSCC reset controller ...	2024-09-21 14:11:05 -07:00
Stephen Boyd	6629108252	Merge branches 'clk-amlogic', 'clk-microchip' and 'clk-imx' into clk-next * clk-amlogic: clk: meson: introduce symbol namespace for amlogic clocks clk: meson: axg-audio: add sm1 earcrx clocks clk: meson: axg-audio: setup regmap max_register based on the SoC dt-bindings: clock: axg-audio: add earcrx clock ids clk: meson: s4: pll: Constify struct regmap_config clk: meson: s4: peripherals: Constify struct regmap_config clk: meson: c3: pll: Constify struct regmap_config clk: meson: c3: peripherals: Constify struct regmap_config clk: meson: a1: pll: Constify struct regmap_config clk: meson: a1: peripherals: Constify struct regmap_config * clk-microchip: clk: at91: sama7g5: Allocate only the needed amount of memory for PLLs clk: at91: sam9x7: add sam9x7 pmc driver dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT clk: at91: sama7g5: move mux table macros to header file clk: at91: sam9x7: add support for HW PLL freq dividers clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs dt-bindings: clocks: atmel,at91rm9200-pmc: add sam9x7 clock controller dt-bindings: clocks: atmel,at91sam9x5-sckc: add sam9x7 * clk-imx: (27 commits) clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL clk: imx95: enable the clock of NETCMIX block control dt-bindings: clock: add RMII clock selection dt-bindings: clock: add i.MX95 NETCMIX block control clk: imx: imx8: Use clk_hw pointer for self registered clock in clk_parent_data clk: imx: composite-7ulp: Use NULL instead of 0 clk: imx: add missing MODULE_DESCRIPTION() macros clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate clk: imx: fracn-gppll: update rate table clk: imx: imx8qxp: Parent should be initialized earlier than the clock clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks clk: imx: imx8qxp: Add LVDS bypass clocks clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one clk: imx: imx8mn: add sai7_ipg_clk clock settings clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D clk: imx: imx8mp: fix clock tree update of TF-A managed clocks clk: imx: fracn-gppll: fix fractional part of PLL getting lost clk: imx: composite-7ulp: Check the PCC present bit ...	2024-09-21 14:10:59 -07:00
Stephen Boyd	c7183ff52f	Merge branches 'clk-assigned-rates', 'clk-renesas' and 'clk-scmi' into clk-next * clk-assigned-rates: clk: clk-conf: support assigned-clock-rates-u64 * clk-renesas: (34 commits) clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT clk: renesas: rzv2h: Add support for dynamic switching divider clocks clk: renesas: r9a08g045: Add clocks, resets and power domains for USB dt-bindings: clock: renesas,cpg-clocks: Add top-level constraints clk: renesas: r8a779h0: Add CANFD clock clk: renesas: Add RZ/V2H(P) CPG driver clk: renesas: Add family-specific clock driver for RZ/V2H(P) dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG clk: renesas: r8a779h0: Add PWM clock dt-bindings: clock: renesas,cpg-mssr: Document RZ/G2M v3.0 (r8a774a3) clock clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs clk: renesas: rcar-gen4: Remove unused fixed PLL clock types clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLs clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLs clk: renesas: r8a779a0: Use defines for PLL control registers clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs clk: renesas: rcar-gen4: Add support for fixed variable PLLs clk: renesas: rcar-gen4: Add support for variable fractional PLLs ... * clk-scmi: clk: scmi: add is_prepared hook	2024-09-21 14:10:53 -07:00
Stephen Boyd	a2b88026f7	Merge branches 'clk-kunit', 'clk-mediatek', 'clk-cleanup' and 'clk-bindings' into clk-next - KUnit tests for clk registration and fixed rate basic clk type * clk-kunit: clk: Add KUnit tests for clks registered with struct clk_parent_data clk: Add KUnit tests for clk fixed rate basic type clk: Add test managed clk provider/consumer APIs platform: Add test managed platform_device/driver APIs of: Add a KUnit test for overlays and test managed APIs dt-bindings: vendor-prefixes: Add "test" vendor for KUnit and friends of: Add test managed wrappers for of_overlay_apply()/of_node_put() of/platform: Allow overlays to create platform devices from the root node * clk-mediatek: dt-bindings: clock: mediatek: Convert MediaTek clock syscons to schema dt-bindings: Move Mediatek clock controllers to "clock" directory dt-bindings: clock: mediatek,apmixedsys: Fix "mediatek,mt6779-apmixed" compatible clk: mediatek: reset: Remove unused mtk_register_reset_controller() clk: mediatek: reset: Return regmap's error code * clk-cleanup: clk: starfive: Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage clk: ti: dra7-atl: Fix leak of of_nodes clk:davinci: make use of dev_err_cast_probe() clk: bcm: bcm53573: fix OF node leak in init clk: lmk04832: Use devm_clk_get_enabled() helpers clk: visconti: Switch to use kmemdup_array() clk: mmp: Switch to use kmemdup_array() clk: hisilicon: Remove unnecessary local variable clk: use clk_core_unlink_consumer() helper clk: Use of_property_present() clk: at91: Use of_property_count_u32_elems() to get property length da8xx-cfgchip.c: replace of_node_put with __free improves cleanup * clk-bindings: dt-bindings: clock: st,stm32mp1-rcc: add top-level constraints dt-bindings: clock: cirrus,lochnagar: add top-level constraints dt-bindings: clock: baikal,bt1-ccu-div: add top-level constraints dt-bindings: clock: nxp,lpc3220-usb-clk: Convert bindings to dtschema dt-bindings: clock: nxp,lpc3220-clk: Convert bindings to DT schema	2024-09-21 14:10:42 -07:00
Stephen Boyd	82cf3b8afc	Qualcomm clock updates for v6.12 This introduces camera, display and gpu clock drivers for SM4450. A camera clock controller is also introduced for SM8150. A bunch of struct freq_tbl are marked const, to reduce .data usage. Support for MSM8226 A7PLL and the Regera PLL is introduced. The Lucid 5LPE PLL configuration sequence is corrected to not reuse Trion, as they do differ. A number of fixes are made to SM8550 display clock controller, and SM8650 is folded into the same driver. Missing clocks and GDSCs needed for audio on MSM8998 are added. For SC8180X missing USB MP resets, GPLL9 clock, and QUPv3 DFS clocks are added, the sdcc clock frequency tables are corrected. The SM8150 gcc_cpuss_ahb_clk_src is dropped. PCIe GDSCs are marked at RET_ON on sm8250 and sm8540, to avoid them turning off during suspend. The SM8550 video clock controller GDSCs are marked to use the newly introduced HW_CTRL mechanism. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmbmDtoVHGFuZGVyc3Nv bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FHAIP/R+sObeN7oyJGT71fL1Ey+D3gUT/ CL17ZhfnE5V1DXbEoo8ff7WPB38F/rRwNh/bl37zcpCKlCxS0TpdslWRmC9ninwK ifxYZFxE85sgTPcIZORPs0bNrlMsIZaoCMUh0ithg4iQs/LeiPqci8NIk38dEQKu RXCiCNkJlgLlbTzD6M6aiHtfFhvT+6mjleVfQckuw6H6zl/tlbbG51qKe70VJcS8 /thGgN+xxJex1n/zIBynbpUN9hjhoqFnqzQnLTZ+t9PfbmE99nL1LJtXCHYVwV3o mqFpKlRIf/O6mQgTD/53mIfHai+oM3g19u+jqeO9CUqqea2le5NjhhEmGUc+Ccea 2ZC5shBPkQp9FPXxnox0axziKibGset7OM+pDEe9uxsaVH27zMLgZHTlKJZ/9sKq OoWZ3AvcqBePu4dFA6QBoM1jlPSSyRXB/QZmZR3rrnTcvHBPn56cvw5KzoKzs8LK FmcK9v67w8YEENYjamt2A9H6jOxeyTVOrv3m0Ba6JOtsLaKBK7ywhQlrsE+ub6Nq msgDBD/7ZgFWz7jxFb4L2RyWGRdD3F5XqpkaSc7Wa5f0JtXNENT5ES+aiTcGGOU9 A8STkpkTxSokfi54ym6JMJDw9DZzJE9hUmv/6sU6aVg8ysPyZKcVVeUHmU7ic9N3 WIFXSLNwfkGRTRdK =hfMs -----END PGP SIGNATURE----- Merge tag 'qcom-clk-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom Pull Qualcomm clk driver updates from Bjorn Andersson: - Add camera, display and GPU clock drivers for Qualcomm SM4450 - Add a camera clock driver for Qualcomm SM8150 - Mark a bunch of struct freq_tbl const to reduce .data usage - Add Qualcomm MSM8226 A7PLL and Regera PLL support - Fix the Qualcomm Lucid 5LPE PLL configuration sequence to not reuse Trion, as they do differ - A number of fixes to the Qualcomm SM8550 display clock driver - Fold Qualcomm SM8650 display clock driver into SM8550 one - Add missing clocks and GDSCs needed for audio on Qualcomm MSM8998 - Add missing USB MP resets, GPLL9, and QUPv3 DFS to Qualcomm SC8180X - Fix sdcc clk frequency tables on Qualcomm SC8180X - Drop the Qualcomm SM8150 gcc_cpuss_ahb_clk_src - Mark Qualcomm PCIe GDSCs as RET_ON on sm8250 and sm8540 to avoid them turning off during suspend - Use the HW_CTRL mechanism on Qualcomm SM8550 video clock controller GDSCs * tag 'qcom-clk-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (47 commits) clk: qcom: videocc-sm8550: Use HW_CTRL_TRIGGER flag for video GDSC's clk: qcom: dispcc-sm8250: use special function for Lucid 5LPE PLL clk: qcom: dispcc-sm8250: use CLK_SET_RATE_PARENT for branch clocks clk: qcom: ipq5332: Use icc-clk for enabling NoC related clocks clk: qcom: ipq5332: Register gcc_qdss_tsctr_clk_src dt-bindings: usb: qcom,dwc3: Update ipq5332 clock details dt-bindings: interconnect: Add Qualcomm IPQ5332 support clk: qcom: gcc-msm8998: Add Q6 BIMC and LPASS core, ADSP SMMU clocks dt-bindings: clock: gcc-msm8998: Add Q6 and LPASS clocks definitions clk: qcom: Fix SM_CAMCC_8150 dependencies clk: qcom: gcc-sm8150: De-register gcc_cpuss_ahb_clk_src clk: qcom: gcc-sc8180x: Fix the sdcc2 and sdcc4 clocks freq table clk: qcom: gcc-sc8180x: Add GPLL9 support dt-bindings: clock: qcom: Add GPLL9 support on gcc-sc8180x clk: qcom: gcc-sc8180x: Register QUPv3 RCGs for DFS on sc8180x clk: qcom: clk-rpmh: Fix overflow in BCM vote dt-bindings: clock: qcom: Drop required-opps in required on SM8650 camcc dt-bindings: clock: qcom: Drop required-opps in required on sm8650 videocc dt-bindings: clock: qcom,qcs404-turingcc: convert to dtschema dt-bindings: clock: Add x1e80100 LPASSCC reset controller ...	2024-09-18 09:44:48 -07:00
Heiko Stuebner	eb3b3f5205	dt-bindings: clock, reset: fix top-comment indentation rk3576 headers Block comments should align the * on each line, as checkpatch rightfully pointed out, so fix that style issue on the newly added rk3576 headers. Fixes: `49c04453db` ("dt-bindings: clock, reset: Add support for rk3576") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20240909223149.85364-1-heiko@sntech.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-09-09 16:13:05 -07:00
Arnd Bergmann	4500f510d9	clk: rockchip: remove unused mclk_pdm0_p/pdm0_p definitions When -Wunused-const-variable is enabled (not the default), there is a warning about two definitions in this file: In file included from drivers/clk/rockchip/clk-rk3576.c:14: drivers/clk/rockchip/clk-rk3576.c:334:7: error: 'mclk_pdm0_p' defined but not used [-Werror=unused-const-variable=] 334 \| PNAME(mclk_pdm0_p) = { "mclk_pdm0_src_top", "xin24m" }; \| ^~~~~~~~~~~ drivers/clk/rockchip/clk.h:564:43: note: in definition of macro 'PNAME' 564 \| #define PNAME(x) static const char const x[] __initconst \| ^ drivers/clk/rockchip/clk-rk3576.c:333:7: error: 'pdm0_p' defined but not used [-Werror=unused-const-variable=] 333 \| PNAME(pdm0_p) = { "clk_pdm0_src_top", "xin24m" }; \| ^~~~~~ drivers/clk/rockchip/clk.h:564:43: note: in definition of macro 'PNAME' 564 \| #define PNAME(x) static const char const x[] __initconst \| ^ Remove them for the moment. If they are needed later, they can be added back at that point. Fixes: `cc40f5baa9` ("clk: rockchip: Add clock controller for the RK3576") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20240909121116.254036-1-arnd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-09-09 14:10:32 -07:00
Stephen Boyd	df947ad4cc	Getting rid of the rest of CLK_NR_CLKS defines that reported the the max number of clocks, but should never have been part of the devicetree binding header. New clock controller driver for the rk3576. And some fixes for rk3228 and rk3588. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmbeGJIQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgXVMB/9HVp0c7tviixkJYdWUwVeCOpQhZfmxZcak 8Hpk05FYCfYrpgo1IQx51iIXv+GXMV6RDSxK9mcoc/BD9RFivUg93X+sbC65fie+ ZchjLE7KMP6tZCAzzmCVo9LTBdhDGmVL8BdBR3TggBZ75m4kuVDNfEcLv6V48zhF HI/VqsnuOFf11bdCBoPDzGX/3VzeELgddHMyhY6XSrdWcGiKGL0JpoI9Se9Vpih8 //LUzuf3iuvdS0C7hBGSkaaOvfD7A55PAF5O1DLJOE5UX02vI0084BnRaE90t1JI w2UY2JCrNGefTK9hDClxelO5shLsepXJ67MPSrMV6T7LRzekJVJN =wpxi -----END PGP SIGNATURE----- Merge tag 'v6.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull Rockchip clk driver updates from Heiko Stübner: - Get rid of CLK_NR_CLKS defines in Rockchip DT binding headers - New clock controller driver for the rk3576 - Some fixes for rk3228 and rk3588 * tag 'v6.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: fix error for unknown clocks clk: rockchip: rk3588: drop unused code clk: rockchip: Add clock controller for the RK3576 clk: rockchip: Add new pll type pll_rk3588_ddr dt-bindings: clock, reset: Add support for rk3576 dt-bindings: clock: rockchip,rk3588-cru: drop unneeded assigned-clocks clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_p dt-bindings: clock: rockchip: remove CLK_NR_CLKS and CLKPMU_NR_CLKS clk: rockchip: rk3399: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage clk: rockchip: rk3368: Drop CLK_NR_CLKS usage clk: rockchip: rk3328: Drop CLK_NR_CLKS usage clk: rockchip: rk3308: Drop CLK_NR_CLKS usage clk: rockchip: rk3288: Drop CLK_NR_CLKS usage clk: rockchip: rk3228: Drop CLK_NR_CLKS usage clk: rockchip: rk3036: Drop CLK_NR_CLKS usage clk: rockchip: px30: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228	2024-09-09 13:58:25 -07:00
Stephen Boyd	4e52054f8d	Samsung SoC clock drivers changes for 6.12 1. Exynos850: Add clock for Thermal Management Unit. 2. Exynos7885: Fix duplicated ID in the header, add missing TOP PLLs and add clocks for USB block in the FSYS clock controller. 3. ExynosAutov9: Add DPUM clock controller 4. ExynosAutov920: Add new (first) clock controllers: TOP and PERIC0 (and a bit more complete bindings). -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmbbCtoQHGtyemtAa2Vy bmVsLm9yZwAKCRDBN2bmhouD14QPD/9JOBcSI0rwjjvbvonm4ciSMZJpZGj4wFSn Hq5lInYvBi1iF1gFA4RdX21l6jRP1wmgMJ21NZMlMxo1/AGUMBnlhlPuFeCXyIwF AFQRZsv1YbXNIV+OE+jxaZhx6k6TzNcdsAyPY1KTyVBX6sT8Y25Fa2RA5qhe0ZB1 +3fO3Lsf7RpAP9X0E3rAjRkLcSiMqHQO8VITXPOTxrq+NCqXPBqiOpgHchkxeew+ urTKRbc0fCt8yY9gG13iHQrzQPcw5TRGyMN1ECEMDjUZZuOu52b2Ss0esqQnWFNN JtJ7751dg6fvwd2NKVvGyvRirWctTNFBGI33s+tTTbMn41We7iH7qh+vjvY9P0Wo vvjAEzDTzZULx3AXIXKbGfn6ezm0kIRH3bx4D/ZnsAKjiVGIM/yiZAwxQHooBkgt cjiVMdXU6TQhWPFBDgw4BuDTcfVlZjZ8OoXlG9rBj/D60B+fSOEFnmGalSuffAr2 nZ+RSWuYh5UBWknpW+hb2wCkLWneCctNXF2cAwOJIx4zqH1MHLxTNk3NNzWAgizU 6SZxoL1wipMIhYTEPkaYQAW+93ievcw8QSPIKYA9FLbKkZlG6oVNb0cpRipqG9tu pjCHmo6j1KHNazQ2KjsNiO1uIbiHQR9/rXxX3NYYtqyh3sl0lQVOgMstqCClkt2i TrqzmlAV3w== =NaSG -----END PGP SIGNATURE----- Merge tag 'samsung-clk-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung Pull Samsung clk driver updates from Krzysztof Kozlowski: - Exynos850: Add clock for Thermal Management Unit - Exynos7885: Fix duplicated ID in the header, add missing TOP PLLs and add clocks for USB block in the FSYS clock controller - ExynosAutov9: Add DPUM clock controller - ExynosAutov920: Add new (first) clock controllers: TOP and PERIC0 (and a bit more complete bindings) * tag 'samsung-clk-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: clk: samsung: add top clock support for ExynosAuto v920 SoC clk: samsung: clk-pll: Add support for pll_531x dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings clk: samsung: exynos7885: Add USB related clocks to CMU_FSYS clk: samsung: clk-pll: Add support for pll_1418x clk: samsung: exynosautov9: add dpum clock support dt-bindings: clock: exynosautov9: add dpum clock clk: samsung: exynos7885: Add missing MUX clocks from PLLs in CMU_TOP clk: samsung: exynos7885: Update CLKS_NR_FSYS after bindings fix dt-bindings: clock: exynos7885: Add indices for USB clocks dt-bindings: clock: exynos7885: Add CMU_TOP PLL MUX indices dt-bindings: clock: exynos7885: Fix duplicated binding clk: samsung: exynos850: Add TMU clock dt-bindings: clock: exynos850: Add TMU clock	2024-09-06 15:18:14 -07:00
Bartosz Golaszewski	9934a1bd45	clk: provide devm_clk_get_optional_enabled_with_rate() There are clock users in the kernel that can't use devm_clk_get_optional_enabled() as they need to set rate after getting the clock and before enabling it. Provide a managed helper that wraps these operations in the correct order. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20240805-clk-new-helper-v2-1-e5fdd1e1d729@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-09-05 13:51:46 -07:00
Nikita Shubin	706ae64464	clk: fixed-rate: add devm_clk_hw_register_fixed_rate_parent_data() Add devm_clk_hw_register_fixed_rate_parent_data(), devres-managed helper to register fixed-rate clock with parent_data. Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me> Link: https://lore.kernel.org/r/20240904-devm_clk_hw_register_fixed_rate_parent_data-v1-1-7f14d6b456e5@maquefel.me Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-09-05 13:48:00 -07:00
Stephen Boyd	a09e3cf770	Merge branch 'clk-imx-old' into clk-imx * clk-imx: (22 commits) clk: imx: composite-7ulp: Use NULL instead of 0 clk: imx: add missing MODULE_DESCRIPTION() macros clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate clk: imx: fracn-gppll: update rate table clk: imx: imx8qxp: Parent should be initialized earlier than the clock clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks clk: imx: imx8qxp: Add LVDS bypass clocks clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one clk: imx: imx8mn: add sai7_ipg_clk clock settings clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D clk: imx: imx8mp: fix clock tree update of TF-A managed clocks clk: imx: fracn-gppll: fix fractional part of PLL getting lost clk: imx: composite-7ulp: Check the PCC present bit clk: imx: composite-93: keep root clock on when mcore enabled clk: imx: composite-8m: Enable gate clk with mcore_booted clk: imx: imx6ul: fix default parent for enet*_ref_sel clk: imx: clk-audiomix: Correct parent clock for earc_phy and audpll clk: imx: clk-audiomix: Add CLK_SET_RATE_PARENT flags for clocks ...	2024-09-05 11:30:59 -07:00
Stephen Boyd	9395f3d21d	i.MX clocks changes for 6.12 - Use clk_hw pointer instead of fw_name for acm_aud_clk[0-1]_sel clocks on i.MX8Q as parents in ACM provider - Add i.MX95 NETCMIX support to the block control provider - Fix parents for ENETx_REF_SEL clocks on i.MX6UL -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEETvPuEU56jyrKp9G4G19EyQCVFVYFAmbYLhgACgkQG19EyQCV FVbk9Q/9FmTp6T4kwfzSytEYe/KGgw8lBt2K0MT82HZIsHGboiNcvO2A5a8G1GHZ BXpz9hiIhlumRzCAIh4N60n0DY5Ck3ZbzL4WyhcCGii5fTxdfcWRIk3hSM27/NCe 2lmHK4wIAOvh3c31oF3jNAupdnawb2IxnHs93dTZ+Bs/8aY/bsA9YxIFUVvWBVdY GkRILwQMAyk0hiGD3TJ8inxtAYy6e78b1koCsD2lsFCNGgvw8e2a36WxbA7FObnX ILD4dgoZRYuQGcRKJu7Ir2pXDrpe4TbtSwlGT06tKXdetQjNIqyv4X2Fscfuy8qt pG4uPpG0uSk1Icbc2h+w1ZtQGzsPBGsxy6We5gcQLEMhxSEpaZEqApdI/O3WxYS8 NN3Apd6StA70HlPiJF7AR2+VRQind51w9F7vBBotCCYXRUT8PEx74/COBZV/eZXC TzVQO7k+WIue+OEOHk5d7EHllM2mNJDY9smRSdMAKvoxseHO2acaw4WyI4T6ayJF wfFAbGTXezixYqZ6tJI7O1+9DN/34WoQIO28wUweXMMDAwjzI6iQDB6B9X7LuK8g RuJTJkSBYSqQVloXerSXDiRRA218/d52rnl5QL7IqapymKjM2fwvtAzIElJZmT9G N2Sg4+BlvM/OxRGjOkznz0RHJf4FeRpy/EWT9RlMSACgSPzIZyQ= =byyI -----END PGP SIGNATURE----- Merge tag 'clk-imx-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx2 Pull i.MX clk driver updates from Abel Vesa: - Use clk_hw pointer instead of fw_name for acm_aud_clk[0-1]_sel clocks on i.MX8Q as parents in ACM provider - Add i.MX95 NETCMIX support to the block control provider - Fix parents for ENETx_REF_SEL clocks on i.MX6UL * tag 'clk-imx-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL clk: imx95: enable the clock of NETCMIX block control dt-bindings: clock: add RMII clock selection dt-bindings: clock: add i.MX95 NETCMIX block control clk: imx: imx8: Use clk_hw pointer for self registered clock in clk_parent_data	2024-09-05 11:18:55 -07:00
Michel Alex	32c055ef56	clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL Commit `4e197ee880` ("clk: imx6ul: add ethernet refclock mux support") sets the internal clock as default ethernet clock. Since IMX6UL_CLK_ENET_REF cannot be parent for IMX6UL_CLK_ENET1_REF_SEL, the call to clk_set_parent() fails. IMX6UL_CLK_ENET1_REF_125M is the correct parent and shall be used instead. Same applies for IMX6UL_CLK_ENET2_REF_SEL, for which IMX6UL_CLK_ENET2_REF_125M is the correct parent. Cc: stable@vger.kernel.org Signed-off-by: Alex Michel <alex.michel@wiedemann-group.com> Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Link: https://lore.kernel.org/r/AS1P250MB0608F9CE4009DCE65C61EEDEA9922@AS1P250MB0608.EURP250.PROD.OUTLOOK.COM Signed-off-by: Abel Vesa <abel.vesa@linaro.org>	2024-09-04 12:39:38 +03:00
Stephen Boyd	f37213104a	clk: renesas: Updates for v6.12 (take two) - Add USB clocks, resets and power domains on RZ/G3S, - Add Generic Timer (GTM), I2C Bus Interface (RIIC), SD/MMC Host Interface (SDHI) and Watchdog Timer (WDT) clocks and resets on RZ/V2H, - Miscellaneous fixes and improvements. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCZtce6wAKCRCKwlD9ZEnx cHiTAP995jEtnc5CnmmWV3SY5bEPRRg4oI3/3R84r2whPmz5AgEA1CcmIXCmSzyD UVlysuC6DIIUvnZjxnZxq41fBTAGfwM= =OrG8 -----END PGP SIGNATURE----- Merge tag 'renesas-clk-for-v6.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull more Renesas clk driver updates from Geert Uytterhoeven: - Add USB clocks, resets and power domains on RZ/G3S - Add Generic Timer (GTM), I2C Bus Interface (RIIC), SD/MMC Host Interface (SDHI) and Watchdog Timer (WDT) clocks and resets on RZ/V2H - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v6.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT clk: renesas: rzv2h: Add support for dynamic switching divider clocks clk: renesas: r9a08g045: Add clocks, resets and power domains for USB dt-bindings: clock: renesas,cpg-clocks: Add top-level constraints	2024-09-03 14:00:29 -07:00
Stephen Boyd	1d777b05da	Microchip clock updates for v6.12 It contains: - support for the Microchip SAM9X7 SoC as follows: -- updates on the PLL drivers -- a new clock driver was added for SAM9X7 -- dt-binding documentation updates (for the new clock driver and for the slow clock controller that SAM9X7 is using) - a fix for the Microchip SAMA7G5 clock driver to avoid allocating mode than necessary memory -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQTsZ8eserC1pmhwqDmejrg/N2X7/QUCZtMj0AAKCRCejrg/N2X7 /XgjAP0e9ETLKbJUgR+mDc5v7N9BNVI7+nDpYmwdet+yi0IdSgD9Hy3FHthumkLh Z71ZCAHPigF7Le+OBTG3PjwvgRAqNg8= =ugya -----END PGP SIGNATURE----- Merge tag 'clk-microchip-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip Pull Microchip clk driver updates from Claudiu Beznea: - support for the Microchip SAM9X7 SoC as follows: - updates on the PLL drivers - a new clock driver was added for SAM9X7 - dt-binding documentation updates (for the new clock driver and for the slow clock controller that SAM9X7 is using) - a fix for the Microchip SAMA7G5 clock driver to avoid allocating mode than necessary memory * tag 'clk-microchip-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: clk: at91: sama7g5: Allocate only the needed amount of memory for PLLs clk: at91: sam9x7: add sam9x7 pmc driver dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT clk: at91: sama7g5: move mux table macros to header file clk: at91: sam9x7: add support for HW PLL freq dividers clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs dt-bindings: clocks: atmel,at91rm9200-pmc: add sam9x7 clock controller dt-bindings: clocks: atmel,at91sam9x5-sckc: add sam9x7	2024-09-03 13:03:10 -07:00
Lad Prabhakar	3aeccbe081	clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT Add clock and reset entries for Generic Timer (GTM), I2C Bus Interface (RIIC), SD/MMC Host Interface (SDHI) and Watchdog Timer (WDT) IP blocks. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828093822.162855-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>	2024-09-02 10:15:38 +02:00
Lad Prabhakar	bc4d25fdfa	clk: renesas: rzv2h: Add support for dynamic switching divider clocks Add support for dynamic switching divider clocks. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828093822.162855-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>	2024-09-02 10:15:38 +02:00
Claudiu Beznea	f0fe60cae6	clk: renesas: r9a08g045: Add clocks, resets and power domains for USB Add clocks, resets and power domains for USB modules available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240822152801.602318-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>	2024-09-02 10:15:31 +02:00
Stephen Boyd	554bc24708	Amlogic clock changes for v6.12 * Constify some structs clean-up * Add SM1 eARC clocks * Introduce a symbol namespace for Amlogic clock specific symbols -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE9OFZrhjz9W1fG7cb5vwPHDfy2oUFAmbRhy8ACgkQ5vwPHDfy 2oVebA//VKlNxUM4MGF9/jkemloaw9N3NcO1OPfjjsHfnv57keA1zNY29yZqqSu2 DaSz1p3w5vQIttxeM8Ae+MEbv6IdXoGeu3Rh0x3lvAlltTXwPSMRrR47EwwKNb0M FpXkO7su2RlH0ETtrPY8/LHG7h+QPOlDgq8f9De7GPfI/9fSGn+JFMxOvEng8sRA U/SAhPgd8KWBnJbwFwsqgyHsNPU/klwABAtN1WyS54m1+TtZ50tNhwjq+1ZMjOAc XxkM+c5+oF8zquzfPuAt9ZCZ1TsznYrGKuKhVb1IoSRZgNNsCqMjzGiRJ47bi0fq gM8bjLwazK7PR/Hp7uiHA+5zCjs/dupDW1TJUqAtZphpx4ISL4c3l+hq4aimuN/u Oen8DiGh6sAVot2zo7oqTVGTA28vrPAuSZJZ4ejYCmmVf+eXuim61g/jMI8x6+ib Cl3eFyGochckUKlO1vjz4Du9JqEUy4nUivA6CvgVjyphZ5dqLJrdz0PXO159/cQs Py8tSTOz6x+nUwqEOngLjq9OnxoR9XGyhxYec7Xn1oDtCc+HpgG4qJ3scqygB1LA uLb2THURLWrh3zFKXaoL3YdFSJ4uwMnk3zfYT45ebkDlNh2xt0VvdYUH4KoLgVTP kv4k9ditcJ4655s7lOYyhAWOwMgGVQ9agqmi+AwFeo0eGxDrtYc= =AsJt -----END PGP SIGNATURE----- Merge tag 'clk-meson-v6.12-1' of https://github.com/BayLibre/clk-meson into clk-amlogic Pull Amlogic clk driver changes from Jerome Brunet: - Constify some Amlogic structs clean-up - Add SM1 eARC clocks for Amlogic - Introduce a symbol namespace for Amlogic clock specific symbols * tag 'clk-meson-v6.12-1' of https://github.com/BayLibre/clk-meson: clk: meson: introduce symbol namespace for amlogic clocks clk: meson: axg-audio: add sm1 earcrx clocks clk: meson: axg-audio: setup regmap max_register based on the SoC dt-bindings: clock: axg-audio: add earcrx clock ids clk: meson: s4: pll: Constify struct regmap_config clk: meson: s4: peripherals: Constify struct regmap_config clk: meson: c3: pll: Constify struct regmap_config clk: meson: c3: peripherals: Constify struct regmap_config clk: meson: a1: pll: Constify struct regmap_config clk: meson: a1: peripherals: Constify struct regmap_config	2024-08-30 12:51:45 -07:00
Sebastian Reichel	12fd64baba	clk: rockchip: fix error for unknown clocks There is a clk == NULL check after the switch to check for unsupported clk types. Since clk is re-assigned in a loop, this check is useless right now for anything but the first round. Let's fix this up by assigning clk = NULL in the loop before the switch statement. Fixes: `a245fecbb8` ("clk: rockchip: add basic infrastructure for clock branches") Cc: stable@vger.kernel.org Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> [added fixes + stable-cc] Link: https://lore.kernel.org/r/20240325193609.237182-6-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-30 16:59:24 +02:00
Sebastian Reichel	2e7b3daa8c	clk: rockchip: rk3588: drop unused code All clocks are registered early using CLK_OF_DECLARE(), which marks the DT node as processed. For the processed DT node the probe routine is never called. Thus this whole code is never executed. This could be "fixed" by using CLK_OF_DECLARE_DRIVER, which avoids marking the DT node as processed. But then the probe routine would re-register all the clocks by calling rk3588_clk_init() again. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20240325193609.237182-2-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-30 16:59:24 +02:00
Elaine Zhang	cc40f5baa9	clk: rockchip: Add clock controller for the RK3576 Add the clock and reset tree definitions for the new RK3576 SoC. As opposed to the other rockchip CRU drivers, the GRF node is looked up via compatible instead of a phandle, which simplifies the device tree bindings. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Liang Chen <cl@rock-chips.com> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Reviewed-by: Elaine Zhang <zhangqing@rock-chips.com> Tested-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/0102019199a7781a-888440f0-a3f7-4a7d-a831-491260cbdfe7-000000@eu-west-1.amazonses.com [dropped additional blank line at EOF in rst-rk3576.c dropped the whole (non-)working as module part] Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-29 11:13:33 +02:00
Elaine Zhang	e781bffc29	clk: rockchip: Add new pll type pll_rk3588_ddr That PLL type is similar to the other rk3588 pll types but the actual rate is twice the configured rate. Therefore, the returned calculated rate must be multiplied by two. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Acked-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/0102019199a76ec4-9d5846d4-d76a-4e69-a241-c88c2983d607-000000@eu-west-1.amazonses.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-29 11:13:28 +02:00
Detlev Casanova	49c04453db	dt-bindings: clock, reset: Add support for rk3576 Add clock and reset ID defines for rk3576. Compared to the downstream bindings written by Elaine, this uses continous gapless IDs starting at 0. Thus all numbers are different between downstream and upstream, but names are kept exactly the same. Also add documentation for the rk3576 CRU core. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/0102019199a76766-f3a2b53f-d063-458b-b0d1-dfbc2ea1893c-000000@eu-west-1.amazonses.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-29 10:28:16 +02:00
Krzysztof Kozlowski	3529dc29fe	dt-bindings: clock: rockchip,rk3588-cru: drop unneeded assigned-clocks assigned-clocks property is redundant, because core dtschema allows them if clocks are provided. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240818173014.122073-4-krzysztof.kozlowski@linaro.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-29 10:14:39 +02:00
Alexander Shiyan	0d02e8d284	clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_p The 32kHz input clock is named "xin32k" in the driver, so the name "32k" appears to be a typo in this case. Lets fix this. Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com> Reviewed-by: Dragan Simic <dsimic@manjaro.org> Fixes: `f1c506d152` ("clk: rockchip: add clock controller for the RK3588") Link: https://lore.kernel.org/r/20240829052820.3604-1-eagle.alexander923@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-29 10:05:23 +02:00
Wei Fang	42dc425fa8	clk: imx95: enable the clock of NETCMIX block control The NETCMIX block control consists of registers for configuration of peripherals in the NETC domain, so enable the clock of NETCMIX to support the configuration. Signed-off-by: Wei Fang <wei.fang@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20240829011849.364987-4-wei.fang@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>	2024-08-29 10:02:18 +03:00
Wei Fang	b4f62001cc	dt-bindings: clock: add RMII clock selection Add RMII clock selection for ENETC0 and ENETC1. Signed-off-by: Wei Fang <wei.fang@nxp.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240829011849.364987-3-wei.fang@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>	2024-08-29 10:02:16 +03:00
Wei Fang	4b78b54762	dt-bindings: clock: add i.MX95 NETCMIX block control Add 'nxp,imx95-netcmix-blk-ctrl' compatible string for i.MX95 platform. Signed-off-by: Wei Fang <wei.fang@nxp.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240829011849.364987-2-wei.fang@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>	2024-08-29 10:02:14 +03:00
Shengjiu Wang	35121e9def	clk: imx: imx8: Use clk_hw pointer for self registered clock in clk_parent_data "acm_aud_clk0_sel" and "acm_aud_clk1_sel" are registered by this ACM driver, but they are the parent clocks for other clocks, in order to use assigned-clock-parents in device tree, the ".fw_name" can't be used, need to assign the clk_hw pointer for the imx8qm_mclk_sels[], imx8qxp_mclk_sels[], imx8dxl_mclk_sels[]. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/1720600860-18866-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>	2024-08-29 10:01:02 +03:00
Yuntao Liu	55c312c1b2	clk: starfive: Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage We need to call pm_runtime_put_noidle() when pm_runtime_get_sync() fails, so use pm_runtime_resume_and_get() instead. this function will handle this. Fixes: `dae5448a32` ("clk: starfive: Add StarFive JH7110 Video-Output clock driver") Signed-off-by: Yuntao Liu <liuyuntao12@huawei.com> Link: https://lore.kernel.org/r/20240815093853.757487-1-liuyuntao12@huawei.com Reviewed-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-08-28 13:20:05 -07:00
David Lechner	9d6e9f10e2	clk: ti: dra7-atl: Fix leak of of_nodes This fix leaking the of_node references in of_dra7_atl_clk_probe(). The docs for of_parse_phandle_with_args() say that the caller must call of_node_put() on the returned node. This adds the missing of_node_put() to fix the leak. Fixes: `9ac33b0ce8` ("CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)") Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://lore.kernel.org/r/20240826-clk-fix-leak-v1-1-f55418a13aa6@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-08-28 13:17:30 -07:00
Yuesong Li	df7e70e38c	clk:davinci: make use of dev_err_cast_probe() Using dev_err_cast_probe() to simplify the code. Signed-off-by: Yuesong Li <liyuesong@vivo.com> Link: https://lore.kernel.org/r/20240828073515.950677-1-liyuesong@vivo.com Reviewed-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-08-28 13:11:21 -07:00
Johan Jonker	fb234516c5	dt-bindings: clock: rockchip: remove CLK_NR_CLKS and CLKPMU_NR_CLKS CLK_NR_CLKS and CLKPMU_NR_CLKS should not be part of the binding. Remove since the kernel code no longer uses it. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/a3292ed0-3489-4887-8567-40ea4983c592@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-28 21:25:50 +02:00
Johan Jonker	1a22986885	clk: rockchip: rk3399: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage In order to get rid of CLK_NR_CLKS and CLKPMU_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/45f83b1f-64f8-4ea5-bc93-ebf7507a9709@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-28 21:25:50 +02:00
Johan Jonker	41563197e7	clk: rockchip: rk3368: Drop CLK_NR_CLKS usage In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/2a19c3cc-5f4d-4d03-90b2-e0bb13b0502f@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-28 21:25:50 +02:00
Johan Jonker	0758fe99bc	clk: rockchip: rk3328: Drop CLK_NR_CLKS usage In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/38ea6be0-3596-49ec-8de9-aef9c7f2bbb6@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-28 21:25:50 +02:00
Johan Jonker	31fe149568	clk: rockchip: rk3308: Drop CLK_NR_CLKS usage In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/9fbca2d8-f904-4913-ba05-8715e748a454@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-28 21:25:50 +02:00
Johan Jonker	545b1313c5	clk: rockchip: rk3288: Drop CLK_NR_CLKS usage In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/af141286-7994-4e3f-93e2-6ee4e718ef8a@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-28 21:25:49 +02:00
Johan Jonker	819b2e19a9	clk: rockchip: rk3228: Drop CLK_NR_CLKS usage In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/2ee6f0a5-a1bb-4b62-ae6b-8f3828f8eccc@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-28 21:25:49 +02:00
Johan Jonker	ec4f4261c3	clk: rockchip: rk3036: Drop CLK_NR_CLKS usage In order to get rid of CLK_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/c8e73847-f472-4473-ac55-068cb28b98f6@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-28 21:25:49 +02:00
Johan Jonker	2496910c84	clk: rockchip: px30: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage In order to get rid of CLK_NR_CLKS and CLKPMU_NR_CLKS and be able to drop it from the bindings, use rockchip_clk_find_max_clk_id helper to find the highest clock id. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/5ad12808-61f5-4e3b-801e-85231375b6a6@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2024-08-28 21:25:49 +02:00
Krzysztof Kozlowski	f92d67e23b	clk: bcm: bcm53573: fix OF node leak in init Driver code is leaking OF node reference from of_get_parent() in bcm53573_ilp_init(). Usage of of_get_parent() is not needed in the first place, because the parent node will not be freed while we are processing given node (triggered by CLK_OF_DECLARE()). Thus fix the leak by accessing parent directly, instead of of_get_parent(). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240826065801.17081-1-krzysztof.kozlowski@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-08-28 11:54:22 -07:00
Krzysztof Kozlowski	4844ab3fe7	dt-bindings: clock: st,stm32mp1-rcc: add top-level constraints Properties with variable number of items per each device are expected to have widest constraints in top-level "properties:" block and further customized (narrowed) in "if:then:". Add missing top-level constraints for clocks and clock-names. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240818173014.122073-5-krzysztof.kozlowski@linaro.org Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-08-28 10:01:27 -07:00
Krzysztof Kozlowski	354831f3a8	dt-bindings: clock: cirrus,lochnagar: add top-level constraints Properties with variable number of items per each device are expected to have widest constraints in top-level "properties:" block and further customized (narrowed) in "if:then:". Add missing top-level constraints for clocks. Drop also redundant assigned-clocks properties, because core dtschema allows them if clocks are provided. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240818173014.122073-2-krzysztof.kozlowski@linaro.org Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-08-28 10:01:25 -07:00
Krzysztof Kozlowski	d6871d25b4	dt-bindings: clock: baikal,bt1-ccu-div: add top-level constraints Properties with variable number of items per each device are expected to have widest constraints in top-level "properties:" block and further customized (narrowed) in "if:then:". Add missing top-level constraints for clocks and clock-names. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240818173014.122073-1-krzysztof.kozlowski@linaro.org Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-08-28 10:01:22 -07:00
Huan Yang	f7e41b65bd	clk: lmk04832: Use devm_clk_get_enabled() helpers The devm_clk_get_enabled() helpers: - call devm_clk_get() - call clk_prepare_enable() and register what is needed in order to call clk_disable_unprepare() when needed, as a managed resource. This simplifies the code and avoids the calls to clk_disable_unprepare(). Signed-off-by: Huan Yang <link@vivo.com> Link: https://lore.kernel.org/r/20240820102119.130298-1-link@vivo.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-08-27 17:25:04 -07:00
Peng Fan	fc953d40bd	clk: scmi: add is_prepared hook Some clocks maybe default enabled by hardware. For clocks that don't have users, that will be left in hardware default state, because prepare count and enable count is zero,if there is no is_prepared hook to get the hardware state. So add is_prepared hook to detect the hardware state. Then when disabling the unused clocks, they can be simply turned OFF to save power during kernel boot. Reviewed-by: Dhruva Gole <d-gole@ti.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20240806145601.1184337-1-peng.fan@oss.nxp.com Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2024-08-27 12:11:45 -07:00

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