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1,248,906 commits

Author SHA1 Message Date
Luca Weiss
fd5afa5d7e arm64: dts: qcom: sm6350: Add Crypto Engine
Add crypto engine (CE) and CE BAM related nodes and definitions for this
SoC.

For reference:

  [    2.297419] qcrypto 1dfa000.crypto: Crypto device found, version 5.5.1

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20240219-sm6350-qce-v2-1-7acb8838f248@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 22:24:28 -05:00
Krishna Kurapati
343dfe6206 arm64: dts: qcom: sc8280xp: Add missing hs_phy_irq in USB nodes
Recent binding update [1] indicates that there are hs_phy_irq
present in primary and secondary usb controllers of sc8280xp.

Add the missing hs_phy_irq for these controllers. Since the driver
doesn't use this interrupt, this change has been only compile
tested.

[1]: https://lore.kernel.org/all/20231227091951.685-2-quic_kriskura@quicinc.com/

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240219075720.640529-1-quic_kriskura@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 22:23:59 -05:00
Anton Bambura
42ee55cb2e arm64: dts: qcom: sc8180x-lenovo-flex-5g: Allow UFS regulators load/mode setting
The UFS driver expects to be able to set load (and by extension, mode)
on the supplied regulators. Add the necessary properties to make that
possible.

Based on https://lore.kernel.org/r/20231214-topic-sc8180_fixes-v1-6-421904863006@linaro.org

Signed-off-by: Anton Bambura <jenneron@postmarketos.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240203191200.99185-7-jenneron@postmarketos.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 21:45:16 -05:00
Anton Bambura
46c2f36e76 arm64: dts: qcom: sc8180x-lenovo-flex-5g: set touchpad i2c frequency to 1 MHz
This solves the issue when touchpad gets stuck on right or middle
click. This also makes touchpad working smoother.

Signed-off-by: Anton Bambura <jenneron@postmarketos.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240203191200.99185-6-jenneron@postmarketos.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 21:44:53 -05:00
Anton Bambura
0d76ffe33e arm64: dts: qcom: sc8180x-lenovo-flex-5g: move pinctrl to appropriate nodes
Split keyboard and touchpad pinctrl nodes since they are for different
devices and move keyboard, touchpad and touchscreen pinctrl references to
appropriate nodes.

Signed-off-by: Anton Bambura <jenneron@postmarketos.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240203191200.99185-4-jenneron@postmarketos.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 21:44:52 -05:00
Anton Bambura
8c28575a4a arm64: dts: qcom: sc8180x-lenovo-flex-5g: set names for i2c hid nodes
Set names, so they correspond to devices connected to these interfaces.

Signed-off-by: Anton Bambura <jenneron@postmarketos.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240203191200.99185-3-jenneron@postmarketos.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 21:44:52 -05:00
Anton Bambura
4aa609a922 arm64: dts: qcom: sc8180x-lenovo-flex-5g: fix GPU firmware path
Fix GPU firmware path so it uses model-specific directory.

Signed-off-by: Anton Bambura <jenneron@postmarketos.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240203191200.99185-2-jenneron@postmarketos.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 21:44:52 -05:00
Richard Acayan
232490b925 arm64: dts: qcom: sdm670-google-sargo: add panel
Add the panel used in the Google Pixel 3a.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Link: https://lore.kernel.org/r/20240209001639.387374-9-mailingradian@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 21:37:29 -05:00
Neil Armstrong
039d379490 arm64: dts: qcom: sm8650: add missing qcom,non-secure-domain property
By default the DSP domains are non secure, add the missing
qcom,non-secure-domain property to mark them as non-secure.

Fixes: 10e0246712 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes")
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240227-topic-sm8x50-upstream-fastrpc-non-secure-domain-v1-3-15c4c864310f@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 21:32:28 -05:00
Neil Armstrong
49c50ad9e6 arm64: dts: qcom: sm8550: add missing qcom,non-secure-domain property
By default the DSP domains are non secure, add the missing
qcom,non-secure-domain property to mark them as non-secure.

Fixes: d0c061e366 ("arm64: dts: qcom: sm8550: add adsp, cdsp & mdss nodes")
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240227-topic-sm8x50-upstream-fastrpc-non-secure-domain-v1-2-15c4c864310f@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 21:32:06 -05:00
Neil Armstrong
033fbfa0eb arm64: dts: qcom: sm8450: add missing qcom,non-secure-domain property
By default the DSP domains are non secure, add the missing
qcom,non-secure-domain property to mark them as non-secure.

Fixes: 91d70eb708 ("arm64: dts: qcom: sm8450: add fastrpc nodes")
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240227-topic-sm8x50-upstream-fastrpc-non-secure-domain-v1-1-15c4c864310f@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 21:31:34 -05:00
Bjorn Andersson
6e995a1b53 arm64: dts: qcom: qcs6490-rb3gen2: Name the regulators
Without explicitly specifying names for the regulators they are named
based on the DeviceTree node name. This results in multiple regulators
with the same name, making debug prints and regulator_summary impossible
to reason about.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240227-rb3gen2-regulator-names-v1-1-63ceb845dcc8@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 21:30:04 -05:00
Krzysztof Kozlowski
76cbe23e43 arm64: dts: qcom: x1e80100-crd: switch WSA8845 speakers to shared reset-gpio
Each pair of WSA8845 speakers share the powerdown SD_N GPIO, thus this
GPIO is specified twice in each WSA8845 device node.  Such DTS was added
hoping non-exclusive GPIO usage would be accepted, but it turned out
otherwise: it is not supported by the Linux kernel.

Linux kernel however supports sharing reset GPIOs, when used bia the
reset controller framework as implemented in commit 26c8a435fc ("ASoC:
dt-bindings: qcom,wsa8840: Add reset-gpios for shared line") and
commit c721f189e8 ("reset: Instantiate reset GPIO controller for
shared reset-gpios").

Convert the property with shutdown GPIO to "reset-gpios" to use
mentioned Linux kernel feature.  This allows to bring all four speakers
out of reset.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240227142725.625561-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 21:28:43 -05:00
Krzysztof Kozlowski
d4fac32cbe arm64: dts: qcom: x1e80100: correct SWR1 pack mode
Correct the SWR1 Soundwire controller port block pack mode to match
reference code.  Not sure if this has any impact.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240227142725.625561-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 21:28:43 -05:00
Loic Poulain
7d6d561fa9 arm64: dts: qcom: qcm2290: Add LMH node
Add a node for the Limits Management Hardware to ensure it can be
configured by the operating system.

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
[Konrad: add commit msg, rebase]
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240308-topic-rb1_lmh-v2-3-bac3914b0fe3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 20:28:06 -05:00
Konrad Dybcio
27ef06ebd2 arm64: dts: qcom: sc8280xp: Describe TCSR download mode register
To allow for swift EDL reboots, describe the respective register under
the scm node.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240307-topic-8280_nodes-v1-4-4eba20e08902@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 20:27:06 -05:00
Konrad Dybcio
865ff2e6f5 arm64: dts: qcom: sc8280xp: Add PS_HOLD restart
Killing the platform with a single write and no firmware involvement is
pretty cool, add support for it.

Note that due to restart notifier priority settings, PSCI reset will
be used instead, unless:

a) PSCI is not exposed by the firmware (e.g. because the fw was replaced)
or
b) PSCI restart fails for some reason

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240307-topic-8280_nodes-v1-3-4eba20e08902@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 20:27:06 -05:00
Konrad Dybcio
dc6cb3854c arm64: dts: qcom: sc8280xp: Add QFPROM node
Describe the QFPROM NVMEM block. Also, add a subnode to represent the
GPU speed bin region within it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240307-topic-8280_nodes-v1-2-4eba20e08902@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 20:27:06 -05:00
Jianhua Lu
91905d8368 arm64: dts: qcom: sm8250-xiaomi-elish: add usb pd negotiation support
Add usb pd negotiation, but charging is controlled by pm8150b pmic,
so it can only charge battery with 5W,

Signed-off-by: Jianhua Lu <lujianhua000@gmail.com>
Link: https://lore.kernel.org/r/20240302131025.13741-1-lujianhua000@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 20:26:33 -05:00
Johan Hovold
81051f14a6 arm64: dts: qcom: sc8280xp: enable GICv3 ITS for PCIe
The DWC PCIe controller can be used with its internal MSI controller or
with an external one such as the GICv3 Interrupt Translation Service
(ITS).

Add the msi-map properties needed to use the GIC ITS. This will also
make Linux switch to the ITS implementation, which allows for assigning
affinity to individual MSIs.

Note that using the GIC ITS on SC8280XP will cause Advanced Error
Reporting (AER) interrupts to be received on errors unlike when using
the internal MSI controller. This will specifically lead to
notifications about Correctable Errors being logged for the Wi-Fi
controller on the Lenovo ThinkPad X13s when ASPM L0s is enabled.

Suggested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20240306095651.4551-6-johan+linaro@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 20:26:19 -05:00
Johan Hovold
2b62197155 arm64: dts: qcom: sc8280xp: add missing PCIe minimum OPP
Add the missing PCIe CX performance level votes to avoid relying on
other drivers (e.g. USB or UFS) to maintain the nominal performance
level required for Gen3 speeds.

Fixes: 813e831570 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes")
Cc: stable@vger.kernel.org      # 6.2
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20240306095651.4551-5-johan+linaro@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 20:26:19 -05:00
Konrad Dybcio
9fa6a0bad7 arm64: dts: qcom: sc8280xp: Add missing LMH interrupts
Hook up the interrupts that signal the Limits Management Hardware has
started some sort of throttling action.

In testing, you may notice the A78C cluster throttle IRQ fire count stays
at zero. After an hour of painful experiments on an X13s, I was able to
get that cluster to heat up near 90 degC, after which the IRQ has indeed
fired. So it stands to reason that the heat output difference between the
A78C and X1C clusters is so massive that LMH rarely decides to throttle
the "little" one based on its power metrics.

Fixes: 152d1faf1e ("arm64: dts: qcom: add SC8280XP platform")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240217-topic-8280_lmh-v1-1-d72dd4fedfb8@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 11:52:56 -05:00
Ritesh Kumar
629c635eaf arm64: dts: qcom: qcm6490-idp: add display and panel
Enable Display Subsystem with Novatek NT36672E Panel
on qcm6490 idp platform.

Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240215103929.19357-3-quic_riteshk@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-17 11:46:04 -05:00
Jianhua Lu
2219626708 arm64: dts: qcom: sm8250-xiaomi-elish: set rotation
Xiaomi Pad 5 Pro has a 2560x1600 portrait screen, set RIGHT_UP rotation
to make it look like a landscape screen.

Signed-off-by: Jianhua Lu <lujianhua000@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240227121744.10918-1-lujianhua000@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-03 20:06:13 -08:00
Abel Vesa
a4f82b8045 arm64: dts: qcom: sm8650: Fix SPMI channels size
The actual size of the channels registers region is 4MB, according to the
documentation. This issue was not caught until now because the driver was
supposed to allow same regions being mapped multiple times for supporting
multiple buses. Thie driver is using platform_get_resource_byname() and
devm_ioremap() towards that purpose, which intentionally avoids
devm_request_mem_region() altogether.

Fixes: 10e0246712 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
Link: https://lore.kernel.org/r/20240221-dts-qcom-sm8550-fix-spmi-chnls-size-v2-2-72b5efd9dc4f@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-03 19:53:44 -08:00
Abel Vesa
77dd1e50ff arm64: dts: qcom: sm8550: Fix SPMI channels size
The actual size of the channels registers region is 4MB, according to the
documentation. This issue was not caught until now because the driver was
supposed to allow same regions being mapped multiple times for supporting
multiple buses. Thie driver is using platform_get_resource_byname() and
devm_ioremap() towards that purpose, which intentionally avoids
devm_request_mem_region() altogether.

Fixes: ffc50b2d38 ("arm64: dts: qcom: Add base SM8550 dtsi")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Link: https://lore.kernel.org/r/20240221-dts-qcom-sm8550-fix-spmi-chnls-size-v2-1-72b5efd9dc4f@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-03-03 19:53:44 -08:00
Dmitry Baryshkov
f176168bcb arm64: dts: qcom: sm6115: fix USB PHY configuration
The patch adding Type-C support for sm6115 was misapplied. All the
orientation switch configuration ended up at the UFS PHY node instead of
the USB PHY node. Move the data bits to the correct place.

Fixes: a06a2f12f9 ("arm64: dts: qcom: qrb4210-rb2: enable USB-C port handling")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240220173104.3052778-1-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-20 11:54:53 -06:00
Manivannan Sadhasivam
dfc554d521 arm64: dts: sm8650: Add msi-map-mask for PCIe nodes
"msi-map-mask" is a required property for all Qcom PCIe controllers as it
would allow all PCIe devices under a bus to share the same MSI identifier.

Without this property, each device has to use a separate MSI identifier
which is not possible due to platform limitations.

Currently, this is not an issue since only one device is connected to the
bus on boards making use of this SoC.

Fixes: a33a532b3b ("arm64: dts: qcom: sm8650: Use GIC-ITS for PCIe0 and PCIe1")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240216-sm8550-msi-map-fix-v1-1-b66d83ce48b7@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-18 23:06:56 -06:00
Krzysztof Kozlowski
408e177651 arm64: dts: qcom: replace underscores in node names
Underscores should not be used in node names (dtc with W=2 warns about
them), so replace them with hyphens.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20240213145124.342514-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-18 23:02:55 -06:00
Stefan Hansson
2a478a5218 dt-bindings: arm: qcom: Add Samsung Galaxy Tab 4 10.1 LTE
This documents Samsung Galaxy Tab 4 10.1 LTE (samsung,matisselte)
which is a tablet by Samsung based on the MSM8926 SoC.

Signed-off-by: Stefan Hansson <newbyte@postmarketos.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240215180322.99089-3-newbyte@postmarketos.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-18 23:00:21 -06:00
Dmitry Baryshkov
46ea59235c arm64: dts: qcom: pm4125: define USB-C related blocks
Define VBUS regulator and the Type-C handling block as present on the
Quacomm PM4125 PMIC.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20240202-pm4125-typec-v2-3-12771d85700d@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-16 18:00:43 -06:00
Lucas Karpinski
07bbe3fd07 arm64: dts: qcom: sa8540p-ride: disable pcie2a node
pcie2a and pcie3a both cause interrupt storms to occur. However, when
both are enabled simultaneously, the two combined interrupt storms will
lead to rcu stalls. Red Hat is the only company still using this board
and since we still need pcie3a, just disable pcie2a.

Signed-off-by: Lucas Karpinski <lkarpins@redhat.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/r/qcoqksikfvdqxk6stezbzc7l2br37ccgqswztzqejmhrkhbrwt@ta4npsm35mqk
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-16 17:52:58 -06:00
Viken Dadhaniya
498006fd49 arm64: dts: qcom: sc7280: add slimbus DT node
Populate the DTSI node for slimbus instance to be
used by bluetooth FM audio case.

Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com>
Link: https://lore.kernel.org/r/20240215090910.30021-1-quic_vdadhani@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-16 17:12:48 -06:00
Ankit Sharma
942bf463de arm64: dts: qcom: sc7280: Add capacity and DPC properties
The "capacity-dmips-mhz" and "dynamic-power-coefficient" are
used to build Energy Model which in turn is used by EAS to take
placement decisions. So add it to SC7280 soc.

Signed-off-by: Ankit Sharma <quic_anshar@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231103105440.23904-1-quic_anshar@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-16 15:32:52 -06:00
Luca Weiss
dc14578426 arm64: dts: qcom: pmi632: Add PBS client and use in LPG node
With SDAM + PBS the LPG driver can configure the LED pattern in
hardware.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20240205-pmi632-ppg-v1-2-e236c95a2099@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-16 14:32:37 -06:00
Neil Armstrong
114990ce3e arm64: dts: qcom: sm8550: Use GIC-ITS for PCIe0 and PCIe1
Both PCIe0 and PCIe1 controllers are capable of signalling the MSIs
received from endpoint devices to the CPU using GIC-ITS MSI controller.
Add support for it.

The GIC-ITS MSI implementation provides an advantage over internal MSI
implementation using Locality-specific Peripheral Interrupts (LPI) that
would allow MSIs to be targeted for each CPU core.

Like SM8450, the IDs are swapped, but works fine on PCIe0 and PCIe1.

WiFi PCIe Device on SM8550-QRD using GIC-ITS:
218:          0          4          0          0          0          0          0          0   ITS-MSI 524288 Edge      bhi
219:          0          0          5          0          0          0          0          0   ITS-MSI 524289 Edge      mhi
220:          0          0          0         33          0          0          0          0   ITS-MSI 524290 Edge      mhi
221:          0          0          0          0          3          0          0          0   ITS-MSI 524291 Edge      ce0
222:          0          0          0          0          0          1          0          0   ITS-MSI 524292 Edge      ce1
223:          0          0          0          0          0          0         38          0   ITS-MSI 524293 Edge      ce2
224:          0          0          0          0          0          0          0         31   ITS-MSI 524294 Edge      ce3
225:          0          0          0          0          0          0          0          0   ITS-MSI 524295 Edge      ce5
226:          0          0          0          0          0          0          0          0   ITS-MSI 524296 Edge      DP_EXT_IRQ
227:          0          0          0          0          0          0          0          0   ITS-MSI 524297 Edge      DP_EXT_IRQ
228:          0          0          0          0          0          0          0          0   ITS-MSI 524298 Edge      DP_EXT_IRQ
229:          0          0          0          0          0          0          0          0   ITS-MSI 524299 Edge      DP_EXT_IRQ
230:          0          0          0          0          0          0          0          0   ITS-MSI 524300 Edge      DP_EXT_IRQ
231:          0          0          0          0          0          0          0          0   ITS-MSI 524301 Edge      DP_EXT_IRQ
232:          0          0          0          0          0          0          0          0   ITS-MSI 524302 Edge      DP_EXT_IRQ

NVMe in SM8550-HDK M.2 Slot using GIC-ITS:
212:          0          0         22          0          0          0          0          0   ITS-MSI 134742016 Edge      nvme0q0
213:     133098          0          0          0          0          0          0          0   ITS-MSI 134742017 Edge      nvme0q1
214:          0     139450          0          0          0          0          0          0   ITS-MSI 134742018 Edge      nvme0q2
215:          0          0     139476          0          0          0          0          0   ITS-MSI 134742019 Edge      nvme0q3
216:          0          0          0      69767          0          0          0          0   ITS-MSI 134742020 Edge      nvme0q4
217:          0          0          0          0      80368          0          0          0   ITS-MSI 134742021 Edge      nvme0q5
218:          0          0          0          0          0      77315          0          0   ITS-MSI 134742022 Edge      nvme0q6
219:          0          0          0          0          0          0      73022          0   ITS-MSI 134742023 Edge      nvme0q7
220:          0          0          0          0          0          0          0     329993   ITS-MSI 134742024 Edge      nvme0q8

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240122-topic-sm8550-upstream-pcie-its-v2-1-b3398d86d1f1@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-16 12:42:02 -06:00
Krzysztof Kozlowski
7c38989d0f arm64: dts: qcom: sm8150: correct PCIe wake-gpios
Bindings allow a "wake", not "enable", GPIO.  Schematics also use WAKE
name for the pin:

  sa8155p-adp.dtb: pcie@1c00000: Unevaluated properties are not allowed ('enable-gpio' was unexpected)

Fixes: a1c86c6805 ("arm64: dts: qcom: sm8150: Add PCIe nodes")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240108131216.53867-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-16 12:09:54 -06:00
Krzysztof Kozlowski
584a327c5c arm64: dts: qcom: sdm845-db845c: correct PCIe wake-gpios
Bindings allow a "wake", not "enable", GPIO.  Schematics also use WAKE
name for the pin:

  sdm845-db845c.dtb: pcie@1c00000: Unevaluated properties are not allowed ('enable-gpio' was unexpected)

Fixes: 4a657c264b ("arm64: dts: qcom: db845c: Enable PCIe controllers")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240108131216.53867-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-16 12:09:54 -06:00
Luca Weiss
891af1aa1e arm64: dts: qcom: sm7225-fairphone-fp4: Enable display and GPU
Add the description for the display panel found on this phone.
Unfortunately the LCDB module on PM6150L isn't yet supported upstream so
we need to use a dummy regulator-fixed in the meantime.

And with this done we can also enable the GPU and set the zap shader
firmware path.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20240216-fp4-panel-v3-4-a556e4b79640@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-16 11:18:49 -06:00
Luca Weiss
2abe4a310c arm64: dts: qcom: sm6350: Remove "disabled" state of GMU
The GMU won't probe without GPU being enabled, so we can remove the
disabled status so we don't have to explicitly enable the GMU in all the
devices that enable GPU.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20240216-fp4-panel-v3-3-a556e4b79640@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-16 11:18:32 -06:00
Joe Mason
b61fbc595e arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add fuel gauge
Like the Samsung Galaxy A3/A5, the Grand Prime/Core Prime uses a
Richtek RT5033 PMIC as battery fuel gauge, charger, flash LED and for some
regulators.
For now, only add the fuel gauge/battery device to the device tree, so we
can check the remaining battery percentage.

The other RT5033 drivers need some more work first before they can be used
properly.

Signed-off-by: Joe Mason <buddyjojo06@outlook.com>
[Raymond: Move to fortuna-common. Use interrupts-extended]
Signed-off-by: Raymond Hackley <raymondhackley@protonmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240216124639.24689-1-raymondhackley@protonmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-16 11:16:43 -06:00
Luca Weiss
fc48bb3135 arm64: dts: qcom: sm6350: Add interconnect for MDSS
Add the definition for the interconnect used in the display subsystem.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240216-sm6350-interconnect-v1-1-9d55667c06ca@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-16 11:16:37 -06:00
Walter Broemeling
e1839f78e4 arm64: dts: qcom: msm8916-samsung-fortuna/rossa: Add initial device trees
Samsung Galaxy Core Prime and Grand Prime are phones based on MSM8916.
They are similar to the other Samsung devices based on MSM8916 with only a
few minor differences.

This initial commit adds support for:
 - fortuna3g (SM-G530H)
 - gprimeltecan (SM-G530W)
 - grandprimelte (SM-G530FZ)
 - rossa (SM-G360G)

The device trees contain initial support with:
 - GPIO keys
 - Regulator haptic
 - SDHCI (internal and external storage)
 - USB Device Mode
 - UART (on USB connector via the SM5502/SM5504 MUIC)
 - WCNSS (WiFi/BT)
 - Regulators
 - QDSP6 audio
 - Speaker/earpiece/headphones/microphones via digital/analog codec in
   MSM8916/PM8916
 - WWAN Internet via BAM-DMUX

There are different variants of Core Prime and Grand Prime, with some
differences in accelerometer, NFC and panel.
Core Prime and Grand Prime are similar, with some differences in MUIC,
panel and touchscreen.

The common parts are shared in
msm8916-samsung-fortuna-common.dtsi and msm8916-samsung-rossa-common.dtsi
to reduce duplication.

Signed-off-by: Walter Broemeling <wallebroem@gmail.com>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
[Joe: Add audio, buttons and WiFi]
Signed-off-by: Joe Mason <buddyjojo06@outlook.com>
[Siddharth: Add fortuna3g]
Signed-off-by: Siddharth Manthan <siddharth.manthan@gmail.com>
[Raymond: Add modem, fortuna-common.dtsi, grandprimelte and rossa]
Signed-off-by: Raymond Hackley <raymondhackley@protonmail.com>
Link: https://lore.kernel.org/r/20240129143147.5058-1-raymondhackley@protonmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-14 09:41:27 -06:00
Konrad Dybcio
2f7be4caac arm64: dts: qcom: sm8550: Switch UFS from opp-table-hz to opp-v2
Now that the non-legacy form of OPP is supported within the UFS driver,
go ahead and switch to it, adding support for more intermediate freq/power
states.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Link: https://lore.kernel.org/r/20240203-topic-8550_ufs_oppv2-v2-1-b0bef2a73e6c@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-14 09:41:27 -06:00
Krzysztof Kozlowski
1587bb53c1 arm64: dts: qcom: sc8180x: describe all PCI MSI interrupts
Each group of MSI interrupts is mapped to the separate host interrupt.
Describe each of interrupts in the device tree for PCIe hosts.  This
also corrects PCIe1 and PCIe2 first MSI interrupt.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240205163123.81842-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-14 09:41:27 -06:00
Krzysztof Kozlowski
77e7257a60 arm64: dts: qcom: minor whitespace cleanup
The DTS code coding style expects exactly one space before '{' and
around '=' characters.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240208105208.128706-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-14 09:41:27 -06:00
Krzysztof Kozlowski
1fe82781df arm64: dts: qcom: ssm7125-xiaomi: drop incorrect UFS phy max current
Neither bindings nor UFS phy driver use properties like
'vdda-phy-max-microamp' and 'vdda-pll-max-microamp':

  sm7125-xiaomi-curtana.dtb: phy@1d87000: 'vdda-phy-max-microamp', 'vdda-pll-max-microamp' do not match any of the regexes: 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240212150558.81896-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-14 09:41:27 -06:00
Krzysztof Kozlowski
4442a67eed arm64: dts: qcom: x1e80100-crd: add sound card
Add sound card to X1E80100-CRD board and update DMIC supply.  Works so
far:
 - Audio playback via speakers or audio jack headset,
 - DMIC0-3 recording.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240212184403.246299-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-14 09:41:27 -06:00
Krzysztof Kozlowski
8794916799 arm64: dts: x1e80100: correct DMIC2 and DMIC3 pin config node names
Correct the TLMM pin configuration and muxing node names used for DMIC2
and DMIC3 (dmic01 -> dmic23).  This has no functional impact, but
improves code readability and avoids any confusion when reading the DTS.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240212172335.124845-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-14 09:41:20 -06:00
Krzysztof Kozlowski
94c3127671 arm64: dts: sm8650: correct DMIC2 and DMIC3 pin config node names
Correct the TLMM pin configuration and muxing node names used for DMIC2
and DMIC3 (dmic01 -> dmic23).  This has no functional impact, but
improves code readability and avoids any confusion when reading the DTS.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240212172335.124845-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-14 09:41:20 -06:00