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Ian Rogers
82e53e7ae0 perf jevents: Add cycles breakdown metric for arm64/AMD/Intel
Breakdown cycles to user, kernel and guest. Add a common_metrics.py
file for such metrics.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:46 -03:00
Ian Rogers
e74f72a7e2 perf jevents: Add mesh bandwidth saturation metric for Intel
Memory bandwidth saturation from CBOX/CHA events present in
broadwellde, broadwellx, cascadelakex, haswellx, icelakex, skylakex
and snowridgex.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:46 -03:00
Ian Rogers
5dc81578ad perf jevents: Add upi_bw metric for Intel
Break down UPI read and write bandwidth using uncore_upi counters.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:46 -03:00
Ian Rogers
6ec3058e70 perf jevents: Add local/remote miss latency metrics for Intel
Derive from CBOX/CHA occupancy and inserts the average latency as is
provided in Intel's uncore performance monitoring reference.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:46 -03:00
Ian Rogers
1fee2701a7 perf jevents: Add C-State metrics from the PCU PMU for Intel
Use occupancy events fixed in:

  https://lore.kernel.org/lkml/20240226201517.3540187-1-irogers@google.com/

Metrics are at the socket level referring to cores, not hyperthreads.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:46 -03:00
Ian Rogers
2166b44be9 perf jevents: Add dir breakdown metrics for Intel
Breakdown directory hit, misses and requests. The implementation uses
the M2M and CHA PMUs present in server models broadwellde, broadwellx
cascadelakex, emeraldrapids, icelakex, sapphirerapids and skylakex.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:46 -03:00
Ian Rogers
cde9c1a5d9 perf jevents: Add local/remote "mem" breakdown metrics for Intel
Breakdown local and remote memory bandwidth, read and writes.

The implementation uses the HA and CHA PMUs present in server models
broadwellde, broadwellx cascadelakex, emeraldrapids, haswellx, icelakex,
ivytown, sapphirerapids and skylakex.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:46 -03:00
Ian Rogers
130f4245af perf jevents: Add mem_bw metric for Intel
Break down memory bandwidth using uncore counters. For many models
this matches the memory_bandwidth_* metrics, but these metrics aren't
made available on all models.

Add support for free running counters.  Query the event JSON when
determining which what events/counters are available.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:46 -03:00
Ian Rogers
426b844289 perf jevents: Add Miss Level Parallelism (MLP) metric for Intel
Number of outstanding load misses per cycle.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:46 -03:00
Ian Rogers
d666f0172a perf jevents: Add FPU metrics for Intel
Metrics break down of floating point operations.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:46 -03:00
Ian Rogers
2f3d6ea05d perf jevents: Add context switch metrics for Intel
Metrics break down context switches for different kinds of
instruction.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
59341f4e17 perf jevents: Add ILP metrics for Intel
Use the counter mask (cmask) to see how many cycles an instruction
takes to retire. Present as a set of ILP metrics.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
d80edef231 perf jevents: Add load store breakdown metrics ldst for Intel
Give breakdown of number of instructions. Use the counter mask (cmask)
to show the number of cycles taken to retire the instructions.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
7413633e25 perf jevents: Add L2 metrics for Intel
Give a breakdown of various L2 counters as metrics, including totals,
reads, hardware prefetcher, RFO, code and evictions.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
cd1c6a4874 perf jevents: Add ports metric group giving utilization on Intel
The ports metric group contains a metric for each port giving its
utilization as a ratio of cycles.

The metrics are created by looking for UOPS_DISPATCHED.PORT events.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
397fdb3a24 perf jevents: Add software prefetch (swpf) metric group for Intel
Add metrics that breakdown software prefetch instruction use.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
37d0b00a1a perf jevents: Add br metric group for branch statistics on Intel
The br metric group for branches itself comprises metric groups for
total, taken, conditional, fused and far metric groups using JSON
events.

Conditional taken and not taken metrics are specific to Icelake and
later generations, so the presence of the event is used to determine
whether the metric should exist.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
8c345f3500 perf jevents: Add tsx metric group for Intel models
Allow duplicated metric to be dropped from JSON files. Detect when TSX
is supported by a model by using the JSON events, use sysfs events at
runtime as hypervisors, etc. may disable TSX.

Add CheckPmu to metric to determine if which PMUs have been associated
with the loaded events.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
7eb9fa417c perf jevents: Mark metrics with experimental events as experimental
When metrics are made with experimental events it is desirable the
metric description also carries this information in case of metric
inaccuracies.

Suggested-by: Perry Taylor <perry.taylor@intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
17d616b7d9 perf jevents: Add smi metric group for Intel models
Allow duplicated metric to be dropped from JSON files.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
61b7b2ef64 perf jevents: Add CheckPmu to see if a PMU is in loaded JSON events
CheckPmu can be used to determine if hybrid events are present,
allowing for hybrid conditional metrics/events/pmus to be premised on
the JSON files rather than hard coded tables.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
1d519e5aa8 perf jevents: Add idle metric for Intel models
Compute using the msr PMU the percentage of wallclock cycles where the
CPUs are in a low power state.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
bab90b3b46 perf jevents: Add RAPL metrics for all Intel models
Add a 'cpu_power' metric group that computes the power consumption
from RAPL events if they are present.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
3563030d4f perf jevents: Add context switch metrics for AMD
Metrics break down context switches for different kinds of
instruction.

Reviewed-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Falcon <thomas.falcon@intel.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
fb4c058174 perf jevents: Add load store breakdown metrics ldst for AMD
Give breakdown of number of instructions. Use the counter mask (cmask)
to show the number of cycles taken to retire the instructions.

Reviewed-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Falcon <thomas.falcon@intel.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
5ecb1622d0 perf jevents: Add uncore l3 metric group for AMD
Metrics use the amd_l3 PMU for access/miss/hit information.

Reviewed-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Falcon <thomas.falcon@intel.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
c4108b9509 perf jevents: Add dtlb metric group for AMD
Add metrics that give an overview and details of the dtlb (zen1, zen2,
zen3).

Reviewed-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Falcon <thomas.falcon@intel.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
e596f32966 perf jevents: Add itlb metric group for AMD
Add metrics that give an overview and details of the l1 itlb (zen1,
zen2, zen3) and l2 itlb (all zens).

Reviewed-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Falcon <thomas.falcon@intel.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
78067ae268 perf jevents: Add br metric group for branch statistics on AMD
The br metric group for branches itself comprises metric groups for
total, taken, conditional, fused and far metric groups using JSON
events.

The lack of conditional events on anything but zen2 means this category
is lacking on zen1, zen3 and zen4.

Reviewed-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Falcon <thomas.falcon@intel.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
9c9efc7462 perf jevents: Add upc metric for uops per cycle for AMD
The metric adjusts for whether or not SMT is on.

Reviewed-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Falcon <thomas.falcon@intel.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
6da95e1834 perf jevents: Add idle metric for AMD zen models
Compute using the MSR PMU the percentage of wallclock cycles where the
CPUs are in a low power state.

Reviewed-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Falcon <thomas.falcon@intel.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
d10ae3a935 perf jevents: Add RAPL event metric for AMD zen models
Add power per second metrics based on RAPL.

Reviewed-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Falcon <thomas.falcon@intel.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:45 -03:00
Ian Rogers
6bd6c5ef6c perf jevents: Add load event JSON to verify and allow fallbacks
Add a LoadEvents function that loads all event JSON files in a
directory.

In the Event constructor ensure all events are defined in the event JSON
except for legacy events like "cycles".

If the initial event isn't found then legacy_event1 is used, and if that
isn't found legacy_event2 is used.

This allows a single Event to have multiple event names as models will
often rename the same event over time. If the event doesn't exist an
exception is raised.

So that references to metrics can be added, add the MetricRef
class. This doesn't validate as an event name and so provides an
escape hatch for metrics to refer to each other.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:44 -03:00
Ian Rogers
19eab0efe7 perf jevents: Build support for generating metrics from python
Generate extra-metrics.json and extra-metricgroups.json from python
architecture specific scripts. The metrics themselves will be added in
later patches.

If a build takes place in tools/perf/ then extra-metrics.json and
extra-metricgroups.json are generated in that directory and so added
to .gitignore.

If there is an OUTPUT directory then the tools/perf/pmu-events/arch
files are copied to it so the generated extra-metrics.json and
extra-metricgroups.json can be added/generated there.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:44 -03:00
Leo Yan
7a0ba38911 perf: Remove redundant kernel.h include
Now that the bitfield dependency is resolved, the explicit inclusion of
kernel.h is no longer needed.

Remove the redundant include.

Signed-off-by: Leo Yan <leo.yan@arm.com>
Cc: Ian Rogers <irogers@google.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:44 -03:00
Leo Yan
a537c0da16 tools: Fix bitfield dependency failure
A perf build failure was reported by Thomas Voegtle on stable kernel
v6.6.120:

    CC      tests/sample-parsing.o
    CC      util/intel-pt-decoder/intel-pt-pkt-decoder.o
    CC      util/perf-regs-arch/perf_regs_csky.o
    CC      util/arm-spe-decoder/arm-spe-pkt-decoder.o
    CC      util/perf-regs-arch/perf_regs_loongarch.o
  In file included from util/arm-spe-decoder/arm-spe-pkt-decoder.h:10,
                   from util/arm-spe-decoder/arm-spe-pkt-decoder.c:14:
  /local/git/linux-stable-rc/tools/include/linux/bitfield.h: In function ‘le16_encode_bits’:
  /local/git/linux-stable-rc/tools/include/linux/bitfield.h:166:31: error: implicit declaration of
  function ‘cpu_to_le16’; did you mean ‘htole16’? [-Werror=implicit-function-declaration]
    ____MAKE_OP(le##size,u##size,cpu_to_le##size,le##size##_to_cpu) \
                                 ^~~~~~~~~
  /local/git/linux-stable-rc/tools/include/linux/bitfield.h:149:9: note: in definition of macro
  ‘____MAKE_OP’
    return to((v & field_mask(field)) * field_multiplier(field)); \
           ^~
  /local/git/linux-stable-rc/tools/include/linux/bitfield.h:170:1: note: in expansion of macro
  ‘__MAKE_OP’
   __MAKE_OP(16)

Fix this by including linux/kernel.h, which provides the required
definitions.

The issue was not found on the mainline due to the relevant C files have
included kernel.h.  It'd be good to merge this change on mainline
as well for robustness.

Closes: https://lore.kernel.org/stable/3a44500b-d7c8-179f-61f6-e51cb50d3512@lio96.de/
Fixes: 64d86c03e1 ("perf arm-spe: Extend branch operations")
Reported-by: Hamza Mahfooz <hamzamahfooz@linux.microsoft.com>
Reported-by: Thomas Voegtle <tv@lio96.de>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Ian Rogers <irogers@google.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
To: Sasha Levin <sashal@kernel.org>
Cc: stable@vger.kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:44 -03:00
Swapnil Sapkal
34b0a58eef perf sched stats: Fixes in man page
Fix the incorrect description of the schedstats report. Also fix the
spelling errors in man page.

Fixes: 800af362d6 ("perf sched stats: Add details in man page")
Reviewed-by: Shrikanth Hegde <sshegde@linux.ibm.com>
Reported-by: Shrikanth Hegde <sshegde@linux.ibm.com>
Signed-off-by: Swapnil Sapkal <swapnil.sapkal@amd.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Anubhav Shelat <ashelat@redhat.com>
Cc: Chen Yu <yu.c.chen@intel.com>
Cc: Gautham Shenoy <gautham.shenoy@amd.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Thomas Falcon <thomas.falcon@intel.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:41 -03:00
Swapnil Sapkal
f7dc496453 perf sched stats: Define macro for SEP_LEN
Define a macro for separator length of the line in perf sched stats
report.

Reviewed-by: Shrikanth Hegde <sshegde@linux.ibm.com>
Signed-off-by: Swapnil Sapkal <swapnil.sapkal@amd.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Anubhav Shelat <ashelat@redhat.com>
Cc: Chen Yu <yu.c.chen@intel.com>
Cc: Gautham Shenoy <gautham.shenoy@amd.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Thomas Falcon <thomas.falcon@intel.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:39 -03:00
Swapnil Sapkal
7284dc7e19 perf sched stats: correct spelling of function name
Replace store_schedtstat_cpu_diff() with store_schedstat_cpu_diff()

Reviewed-by: Shrikanth Hegde <sshegde@linux.ibm.com>
Signed-off-by: Swapnil Sapkal <swapnil.sapkal@amd.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Anubhav Shelat <ashelat@redhat.com>
Cc: Chen Yu <yu.c.chen@intel.com>
Cc: Gautham Shenoy <gautham.shenoy@amd.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Thomas Falcon <thomas.falcon@intel.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:35 -03:00
Swapnil Sapkal
b03b95b4d7 perf sched stats: Add NULL check for cd_map
In perf_sched__schedstat_live(), build_cpu_domain_map() returns the
pointer to cpu_domain_map which can also be NULL.

Add NULL check for the same to avoid NULL pointer dereference.

Fixes: 00093b3133 ("perf sched stats: Add support for live mode")
Reviewed-by: Shrikanth Hegde <sshegde@linux.ibm.com>
Signed-off-by: Swapnil Sapkal <swapnil.sapkal@amd.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Anubhav Shelat <ashelat@redhat.com>
Cc: Chen Yu <yu.c.chen@intel.com>
Cc: Gautham Shenoy <gautham.shenoy@amd.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Thomas Falcon <thomas.falcon@intel.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:31 -03:00
Swapnil Sapkal
05134d1537 perf util: Fix NULL check in cpumask_to_cpulist()
The function cpumask_to_cpulist() allocates memory with calloc() and
stores the result in 'bm', but then incorrectly checks 'cpumask' for
NULL instead of 'bm'.

This means that if the allocation fails, the function will dereference a
NULL pointer when trying to access 'bm'.

Fix the check to test the correct variable 'bm'.

Fixes: d40c68a49f ("perf header: Support CPU DOMAIN relation info")
Reviewed-by: Shrikanth Hegde <sshegde@linux.ibm.com>
Signed-off-by: Swapnil Sapkal <swapnil.sapkal@amd.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Anubhav Shelat <ashelat@redhat.com>
Cc: Chen Yu <yu.c.chen@intel.com>
Cc: Gautham Shenoy <gautham.shenoy@amd.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Thomas Falcon <thomas.falcon@intel.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:24 -03:00
Swapnil Sapkal
2a85bbaed0 perf header: Replace hardcoded max cpus by MAX_NR_CPUS
cpumask and cpulist from cpu-domain header have hardcoded max_cpus value
of 1024.

Current systems have more cpus than this value. Replace it with
MAX_NR_CPUS.

Also define a macro to represent domain name length.

Fixes: d40c68a49f ("perf header: Support CPU DOMAIN relation info")
Reported-by: Shrikanth Hegde <sshegde@linux.ibm.com>
Reviewed-by: Shrikanth Hegde <sshegde@linux.ibm.com>
Signed-off-by: Swapnil Sapkal <swapnil.sapkal@amd.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Anubhav Shelat <ashelat@redhat.com>
Cc: Chen Yu <yu.c.chen@intel.com>
Cc: Gautham Shenoy <gautham.shenoy@amd.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Thomas Falcon <thomas.falcon@intel.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2026-01-28 15:18:11 -03:00
Sumit Gupta
4a1cf5ed51 cpufreq: CPPC: Add generic helpers for sysfs show/store
Add generic helper functions for u64 sysfs attributes that follow the
common pattern of calling CPPC get/set APIs:
 - cppc_cpufreq_sysfs_show_u64(): reads value and handles -EOPNOTSUPP
 - cppc_cpufreq_sysfs_store_u64(): parses input and calls set function

Add CPPC_CPUFREQ_ATTR_RW_U64() macro to generate show/store functions
using these helpers, reducing boilerplate for simple attributes.

Convert auto_act_window and energy_performance_preference_val to use
the new macro.

No functional changes.

Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Reviewed-by: Lifeng Zheng <zhenglifeng1@huawei.com>
[ rjw: Retained empty code line after a conditional ]
Link: https://patch.msgid.link/20260120145623.2959636-2-sumitg@nvidia.com
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2026-01-28 19:10:50 +01:00
Arnd Bergmann
2120005213 More Qualcomm Arm32 DeviceTree updated for v6.20
MSM8226 is switched to generic RPMPD_ indices, to allow dropping the
 duplicate platform-specific constants.
 
 On MSM8960 two additional GSBIs and I2C controllers are introduced.
 Accelerometer, Magnetometer, NFC and Light/Proximity sensors are then
 enabled on the Samsung Galaxy Express.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAml6JRIACgkQCx85Pw2Z
 rcUe3Q/+IK1PvDC31p4QRztTvwiOR+SoCbeD07eojTi8ZqDteRzxL0z4xa76erH0
 zqdUhlPaGPu/eW2QJl+sMFFCBk+Q2L1jkIYwARC/PiVkBZ8VqUcnQoSs/dC85nfN
 mmEHR8cu87IIsRPcsxUsw0X52FTZLQ8ydgNv38/NuikcoN74+WH+xUDxAhQCcUhT
 pcYgjq78GC7wgw6MyyPrJ22ue9v4M+qJZ8ho8mhk16jcAS+u2CDA1M1uY6r+QWSY
 8CWQMbYb61xJAyKn0oaGHeCVH8VlmdXIKPTsCt2j1GJ7Yccp8MmzGRoWDYKxnJp2
 0Z82xDdbR2ajZ+l2S2aAsahQFTyPREVeM5Voju/0ietNKNIBYx9wJ3QuIhU5MSLj
 +uIp8QuJXOaDLRHvF05CheBhWM356WCTFJ1gGnZlpdZAE9AOi7tKRb/B1gyegdFG
 qajBbrrnkrogzcfBwswDwot59CS6JT6THvpyGtAvDwvW4izAGF+IIj2eeEyElbuE
 qwsD7N7dqnUCxl/va+QZFpiZTFjyqQQ6kMrO+pt2BsxGVhbJqrMrnM10fOyWpmh9
 ild64iYRSefo7GO33Eu4kAU0yo+ljKJPeLyIYnZpmyphaGIrfYbXvoKV1AXbAYx1
 9SpNW3c8jt656fVaD3PZDxO82YFg+8KxsT3ug3NYmfG8OOqsTCo=
 =DJx7
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml6UNEACgkQmmx57+YA
 GNnCjA//VvR7rIvIl2hp/jgjGt1g69e7W8xaeBBOldyn8TPJf2wT6bG1Rposz9Ab
 NL33moN30IePmLP/4qDi4xPwnEH4nm4XxZ5UskpkXfG1om0EnnUOKvWXg6YAX0Yc
 4kRS9nHABUECTACCOQ3JR71uRV+bDBYcJXSVtlT1D+mQVYzrlz5fkRZ2Z5bQPkhT
 enxiBb1gbIeaWJc2VsZ5wAZw+KsQmYMN7E0Ot79nqqWVHE3uR/cYovSdSw1BJkDe
 5gXSGDMMQ1VX4qIo9JNH2WB+UlczLXvI7rk68uKawPGAb69xpALXg2QV5OfNpHL9
 9PNP6kvbmxzw8HqSRo5X7bf+OKaEDzzgrNUmMBeSbSmeazBDE1TBcVBhJLNncCWL
 PCC5GBT77I7e0nXuZdoX1uhAIa5RUXqoMRN/fwqZ2tl4eyv+aiyW7V+TPn6XIenN
 vYu5pxj897wu8gwWozcD/YST0gJpyh4BENTGU+ftZW3X3wcrTaW+4GIE95vNFlDJ
 7/dHcJayeKK0BPDHxcbKQJL9uscUvz6z0JkVZGsHBpQxbuhXJVfZPDXbZQLR10SG
 wQzZp+rlzI54cBg8D27u8RGcEKhSVssYByqN2aV16QFI/E+hK7Vmu2ArlsjDlaTg
 a0+6PsuTZHHHnjgjU1aAMhCRW081tYOR8YYOhtD76Q27hSf+1Sw=
 =NSMm
 -----END PGP SIGNATURE-----

Merge tag 'qcom-arm32-for-6.20-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

More Qualcomm Arm32 DeviceTree updated for v6.20

MSM8226 is switched to generic RPMPD_ indices, to allow dropping the
duplicate platform-specific constants.

On MSM8960 two additional GSBIs and I2C controllers are introduced.
Accelerometer, Magnetometer, NFC and Light/Proximity sensors are then
enabled on the Samsung Galaxy Express.

* tag 'qcom-arm32-for-6.20-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  ARM: dts: qcom: switch to RPMPD_* indices
  ARM: dts: qcom: msm8960: expressatt: Add Accelerometer
  ARM: dts: qcom: msm8960: expressatt: Add Magnetometer
  ARM: dts: qcom: msm8960: expressatt: Add NFC
  ARM: dts: qcom: msm8960: expressatt: Add Light/Proximity Sensor
  ARM: dts: qcom: msm8960: Add GSBI2 & GSBI7

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-28 19:09:20 +01:00
Arnd Bergmann
a1f4991db6 More Qualcomm Arm64 DeviceTree updates for v6.20
Enable ADSP FastRPC and add missing GPU memory regions on Agatti.
 Also add the missing GPU regions on SM6115.
 
 Describe the application subsystem watchdog on Hamoa and enable this in
 the EL2 configurations.
 
 Add the camera control interface (CCI) I2C controller on MSM8953, and
 describe the camera regulators and the camera EEPROM on Fairphone FP3.
 
 Specify clock frequency for the i2c4 bus on OnePlus 6, to silence the
 warnings about missing frequency definition.
 
 Add FastRPC and associated heap memory, as well as Coresight, on SM8750
 
 Switch a variety of platforms to use the generic RPMPD_ constants,
 instead of target-specific duplicated, to allow us to drop these from
 the header files.
 
 Drop the invalid opp-shared on the QUP OPP table for Talos.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAml6K4sACgkQCx85Pw2Z
 rcWHGQ/+LoJ7kgEu8X4BG3XW3/C2Z3qV03YHqqfEjqUNOQHeVCPRhSdu4ZgbnQlN
 /sy8JrGIz6Hk6crv/aGTETZ/5WzBO/G3vqT7RnFaW94qi/TbEyA8ini6JTumP5p6
 VDpwpJ+uH5HzJLI9XrjfKDHUld8tFf6XzxyCbDLDHH6+WKUBtoxWZ29LkZfrNiCU
 x0X10K2ShCmKWZ1X/R8+xebSidv3Jr5ro4IOwhcE85miGVExbBXHaGtxxgCzIeK/
 VEr5Y0wKufjpNYaTgZqz4ahaewbTfLhk1VleycVFpk6txGXn4LGsAzeSA58gcBwd
 qyqMaCmfMfck0UqV970t/BqqxYWWL/hjbOZp3ZulNUDlXB7NKi6hE2HTbutTL89A
 DK512LZdM8xLiXWm9gzmvb4v/fLKL3Oxayrev9r7FqBc2/V+W3UELU+xBWUKJYA6
 UXDM5orEl7bOgVLQ1wClkP7gpzolwH3avYyMkvPPbZCQu6x3fq7wd9i9eJzCjwG+
 n1kz+8B/YE0yJHSn34OVTeCyge66TV2QW9qFgu5x3rXrZmJyxciKCGXZqS2ljIEp
 q5MhzmlyyhK7cgEo9t/5547ZBoRIZ1FrVQMs/s2M4OaulgvqyRX/LYdFI0xwF8Wb
 beJrnyHGWMRBRrRA0ghEgDkOfiJrHYEVozieuy53LHbk01Fyia4=
 =sKCi
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml6UIUACgkQmmx57+YA
 GNkYoRAAqjJkg0LDRgMtpJznR//HyjNJVKWYXid2lnaXV0kS3j9iXCVuAufTfgQd
 Thwsfk+81XSd+5CoheF+sFzh6Rv29Bqbz9pBzbkeEiaZXd9juftQp9D9s4ueWM3Z
 1wSi6sXDtrphLOxswqmgA/S+XZ7/WIZV6xgM3KsYI/Ku4dO7mQVAYGxN6H7/oFJP
 7wjbMCjhobDXG7QoRavZYM1p/8zErOzJrzrTqRAEhgr1UawoV2J/dZkTQ3qBYwbh
 MGitd32fWeRvJMTFQyMffF6KD0BFIMczuw/zcxMkskJ42ZF43bv65FbrPLDb7ppE
 zDUtemERvufjN5IhdHosuwO2LNeOi6xeg0IWxPmAS9qTy2jdE4S3+iIB9I0BQiwM
 o1Xo8gaypMojYYfCtqRmYTDYnHamCLWLtNqQ1VFe48+MQvtkaAEcs++fS1Q4MuCm
 oNQ9EOcCM84F58L8jCtVh/r8gcrD/N3KKb39xyXlhsQROjkLqDUSugEJbixMCNJx
 EWF/0DpWQr9Ao855lH8hVLorz+R4JdhUb1w5vAUwWyEsjzP9FHHNlTunv742RbsI
 42W1iIOYj5wv7rVZkDD6HpAeOICExzIo1XYZ37aFaxHJb2jTQsgjF0bDiF/KSpPv
 SF34leIt2VkGs/eG7QB5gl5ft//LoujhV4NztH+FGeOXNk9Xn3w=
 =0SGW
 -----END PGP SIGNATURE-----

Merge tag 'qcom-arm64-for-6.20-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

More Qualcomm Arm64 DeviceTree updates for v6.20

Enable ADSP FastRPC and add missing GPU memory regions on Agatti.
Also add the missing GPU regions on SM6115.

Describe the application subsystem watchdog on Hamoa and enable this in
the EL2 configurations.

Add the camera control interface (CCI) I2C controller on MSM8953, and
describe the camera regulators and the camera EEPROM on Fairphone FP3.

Specify clock frequency for the i2c4 bus on OnePlus 6, to silence the
warnings about missing frequency definition.

Add FastRPC and associated heap memory, as well as Coresight, on SM8750

Switch a variety of platforms to use the generic RPMPD_ constants,
instead of target-specific duplicated, to allow us to drop these from
the header files.

Drop the invalid opp-shared on the QUP OPP table for Talos.

* tag 'qcom-arm64-for-6.20-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  arm64: dts: qcom: sm6115: Add CX_MEM/DBGC GPU regions
  arm64: dts: qcom: agatti: Add CX_MEM/DBGC GPU regions
  arm64: dts: qcom: sm8750: add ADSP fastrpc-compute-cb nodes
  arm64: dts: qcom: sm8750: add memory node for adsp fastrpc
  arm64: dts: qcom: switch to RPMPD_* indices
  arm64: dts: qcom: oneplus-enchilada: Specify i2c4 clock frequency
  arm64: dts: qcom: sm6350: Add clocks for aggre1 & aggre2 NoC
  arm64: dts: qcom: agatti: enable FastRPC on the ADSP
  arm64: qcom: dts: sm8750: add coresight nodes
  arm64: dts: qcom: talos: Drop opp-shared from QUP OPP table
  arm64: dts: qcom: x1-el2: Enable the APSS watchdog
  arm64: dts: qcom: hamoa: Add the APSS watchdog
  dt-bindings: watchdog: Document X1E80100 compatible
  arm64: dts: qcom: sdm632-fairphone-fp3: Enable CCI and add EEPROM
  arm64: dts: qcom: sdm632-fairphone-fp3: Add camera fixed regulators
  arm64: dts: qcom: msm8953: Add CCI nodes
  arm64: dts: qcom: msm8953: Re-sort tlmm pinctrl states

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-28 19:08:03 +01:00
Arnd Bergmann
67fea39d2c New boards: Anberic RG-DS game console, Radxa CM3J module + baseboard
for the Rpi CM4 IO board, QNAP TS133 from the RK3568 NAS series.
 
 2 display outputs for the Lion board (old RK3368), TPS65185 pmic for the
 PineNote and fixes for the PCIe ranges on both RK356x and RK3588.
 These came quite late, so I wanted to give them the time till 6.20-rc1
 and have them migrate to stable-kernels afterwards.
 
 The rest is small stuff on a number of boards wrt gpios and compatibles.
 -----BEGIN PGP SIGNATURE-----
 
 iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmlyelAQHGhlaWtvQHNu
 dGVjaC5kZQAKCRDzpnnJnNEdgda6B/47KASiKcD4c6OfcD3U/qsu9w9iVejYADJe
 NxTAvS0cen5vU7L7G8Zjcrew26l1SFmhvsew1Pr4QIOKkFWJnOem7qVeLR0SIHGU
 ZFGtkLu62b3Iet8a99vpOnTea1IL0QhE5BncWaFTpC5fe9Q/nc3fN7hGd/DGyZx4
 6yjAFqp/hV2Yp5v1eqpurSc4JXbRDaiWIR0X60MdDQxkDGnZQxaK5JL0qPmAFxPt
 tIdtX2DKqOxGnQ0lNQqlMlQajq0kQO5gpA4enOVcVvKO5asYinLx6a/yMFXy0Roj
 Z30tp3sAbp4O7b7DdBciNhbEn4Vkhgnllt83YlplFgHA3x1D+mFQ
 =9a+a
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml6T/AACgkQmmx57+YA
 GNnqww//YjXQYp0mBHDpAGkwIp4wxQe9Ex25J8yv9hBRBpAtYAcP3vDTqEYaiDjH
 wr8opGLbcJJxLLRkbfCEdvFKCukXyG/e3qg69rxElVry3m3mTTL6Tq6tZocPOk8M
 F6hS+RCB0oI8Fazjq/a+TmQkL6WnNXY9/qZ4A05VZhYY+qaKOwUZTzCJsVfsZ66M
 SXo57b0lM7djbyb8l+MUFCjaLskJd5qOrcWlG8NEQDSz3Nt+FP1XMKeKEBmPx40Y
 mNPD7pqRfApEMPgPmsJKRBu4LTyuqPp6Y/0Wu7vHwadhIUVf5wj680/8FGFabs/U
 ZBKt6Gh6LeruySfks0UIYuNAbhd5DKAWQJGS3lPaLLnuSVKk+J0kGqXMgBKq8q9q
 bTsIJVWruJnUtDsqy4KBvaDDbzv9quxdSmkzjH/uZWuUHvy0q/4Zs7xU+Er2dnty
 EoZ+yLDF19qFX6TbBheNmnw2YORPtgaQ0hYR+W5dsSzzpSLwMbILXPi0hZWZZODZ
 aqoR0nocmvaDug1AZDMqxuwpv32RkYAqQg4ZPEqXU2SKbv13wwVLfkltElvEcAG2
 rd1OcMf97+t71i/SvFru/TBFehZv925gON053O507Gn+OJucfHCwixoPOK8xx4Bh
 3hK2GGzHapC7GUW8HY9hpLrUm4b56OG1No83I9K7Hy9deFIW3xM=
 =67JX
 -----END PGP SIGNATURE-----

Merge tag 'v6.20-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt

New boards: Anberic RG-DS game console, Radxa CM3J module + baseboard
for the Rpi CM4 IO board, QNAP TS133 from the RK3568 NAS series.

2 display outputs for the Lion board (old RK3368), TPS65185 pmic for the
PineNote and fixes for the PCIe ranges on both RK356x and RK3588.
These came quite late, so I wanted to give them the time till 6.20-rc1
and have them migrate to stable-kernels afterwards.

The rest is small stuff on a number of boards wrt gpios and compatibles.

* tag 'v6.20-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (25 commits)
  arm64: dts: rockchip: Fix rk3588 PCIe range mappings
  arm64: dts: rockchip: Fix rk356x PCIe range mappings
  arm64: dts: rockchip: Add Anbernic RG-DS
  dt-bindings: input: touchscreen: goodix: Add "panel" property
  dt-bindings: arm: rockchip: Add Anbernic RG-DS
  arm64: dts: rockchip: Explicitly request UFS reset pin on RK3576
  arm64: dts: rockchip: Add TPS65185 for PineNote
  arm64: dts: rockchip: Do not enable hdmi_sound node on Pinebook Pro
  arm64: dts: rockchip: Fix imx258 variant on pinephone pro
  arm64: dts: rockchip: Add the Video-Demo overlay for Lion Haikou
  arm64: dts: rockchip: Enable pwm1 on rk3368-lion-haikou
  arm64: dts: rockchip: Enable HDMI output on RK3368-Lion-Haikou
  arm64: dts: rockchip: Add HDMI node to RK3368
  arm64: dts: rockchip: Use phandle for i2c_lvds_blc on rk3368-lion haikou
  arm64: dts: rockchip: Fix SD card support for RK3576 Nanopi R76s
  arm64: dts: rockchip: Fix SD card support for RK3576 EVB1
  arm64: dts: rockchip: Add Radxa CM3J on RPi CM4 IO Board
  arm64: dts: rockchip: Add Radxa CM3J
  dt-bindings: arm: rockchip: Add Radxa CM3J on RPi CM4 IO Board
  arm64: dts: rockchip: Make eeprom read-only for Radxa ROCK 3C/5A/5C
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-28 19:05:34 +01:00
Arnd Bergmann
a46cb1c79f Removal of the obsolete mshc aliases from RK3036.
-----BEGIN PGP SIGNATURE-----
 
 iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmlycbsQHGhlaWtvQHNu
 dGVjaC5kZQAKCRDzpnnJnNEdgURRB/9KhwXfYdMjOCOR+sEQLt8iUQ8/b2FpqSeh
 T6BvQJjte/o0fmO0TjroHpaF5z96LQh7fAclKGbvMuaqh/cFc5AVygtaMPi7Zqmf
 RlVQTQhHdm4kbRTkT2Qe55lWcyvGzFiIqcVJ/kkek2Z2gYSDSogbqE9SuS/oMEEv
 jEpPysf3ZEiKAvFFkWDlHCwLSZsNFh8+VVEUSPruZkMFFPjp0c2g6WPG6cSyMDgo
 NLN4FsYsdLSaKJ19CZp9TWuyipA9FJ93NvxHS6X79LX7EUggPI4h2ZAoRTvtz9Ad
 oXy7IUqlOhdmlttY0EEi9NFzh0mRPmPnDnuXW0j0KgRi5+9o5c0P
 =RZ/Z
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml6T84ACgkQmmx57+YA
 GNlu4w/9E2CX/hylk/FB1yMT03cRWYYcvLsi+G83A82yZI0nuggZAYXFccCrQMIX
 yv64vF8Cd5XtOsq88RK4LCpclTfSGvmSts2vzp0GARkPCj9OOqFDvC6402rXDgC5
 4Il8A9caScS5fvmCu97SAhW7atCMgGiu+Zg2lyWK+LVYya3Qw6auX8XlHBqoge+k
 6qyQdi2Py0UZFjjKa9jOEB4PIuzAGbLQ0DeTeLDIDn6Rrb5G3SK2domSvM4rdu4o
 D9cTVSfEtDAlYjvZD8zVspyH8GNVocKrClMAVwwbq5wSRb4Mdmd4tIixZCGIOEnq
 IeVnFs2ru9thgRan4BfWh5l6rGV5SLTGNNWI3kjiG8LzuXV80Ow4GwX0bli3YiGw
 1tHLzK6DVFjIug6qd3p4A+NJ09Tamd/5Feq0zGU8ZvER2+lxrc+hrxQT7ETUY8UM
 wF2dMqclci3+J4ImeAF4X5rA15Nr6Yy7L/mzpyrMn0tsbWitgLFxRZnPOm+SW+Y8
 6a0GCVTeMvNdhLsGrbQBhyvhf3wI9Fa/cQdlE8MeoNzeCruntdvha/KxnUoLvSiP
 7sj7WDArVa8hKh9W0R8e1nxeadIGhsi+LJ5it0BxM4XNGJShCzPyDzK/BCicL6QJ
 Oiv6X3DBvcxoB6YusumoUWosBcFB6i4M8PaXoINA+zgzgye89RY=
 =X911
 -----END PGP SIGNATURE-----

Merge tag 'v6.20-rockchip-dts32-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt

Removal of the obsolete mshc aliases from RK3036.

* tag 'v6.20-rockchip-dts32-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: rk3036: remove mshc aliases

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-28 19:04:58 +01:00
Arnd Bergmann
72216ba360 - Add OrangePi 6 Plus board
-----BEGIN PGP SIGNATURE-----
 
 iQHLBAABCgA1FiEEE9MyVaemtW1m4wM6rfNrQFP6hVAFAml0DfQXHHBldGVyLmNo
 ZW5AY2l4dGVjaC5jb20ACgkQrfNrQFP6hVDtGQv/c90LC3S9nDoxB7vyf9XpK4uU
 ei83iKxRTxqNuB9PficrTcW0Jew4ES00EXIokEJxQuKYNJ/7VeiW9N3WBKH7WIZy
 8faFfZ4VNvpJ+ioeS8QFgEin8VpR4AWqm9JucmGo3qFUJREEvkIS8/w4Tg/dIliP
 8lJJxoEQot7iRDnEVVchF7lVf+RYl1hNTbe+bjO22R5KyEPHkpvZbVMmKleVNAyD
 U1JxMw9wEPOSTcOyGBU5ntmOm6yurk5hxnDk7r076pMtSO+hbRO4Si3mO1jsA4u8
 4BB1FYy1e8K2Hy1irlOqQtDSGhD00cVEiehADwE9oXxbNX1Hbj+E28KIF5QsxIYh
 /S/4O9Log1X73z2JUklwTrPdk2LUevpDw7LlYk9Qol/7OTIwA9si9kdHGPqnUbdo
 FcU5GjK20RpgNU0v9vjvzDw9LzKxj0M+KQN7uZqMa/dNPKrI0ukPtqjakPf1OOaM
 BH2kZEPR7gplcZ7CIW9zAr+q5yip4ARNid1NI/pO
 =BOd1
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml6TkwACgkQmmx57+YA
 GNll+hAAlZnsjjVAnxOkopSTFc154HD1RXlkl405aPBkUepnGZoHBosuTTWw3V2/
 0blLkSzsHPdKXTbsseg+DrvI2WsM9IZMJIU/lU/QAQgsVTZHAm8rbG8FgFgWRmBa
 NO0Z36QgNw/5ljMffrX+wuXSU/ZFewZvzWjq6ZONIjqdBBJzSK3Tn/4VnpYcUBN7
 ELuTPr5ALW6zvTUf0ljDNuh+//y9POlAcUBWCRMM4wLYNwsD8LcspnQKsgqawnrL
 xTgpb5kbPOuGoe6ZuL2k9PYvQtpdINN1vocXcxoPVzmWSonc4csu1wzTD136hQw0
 8grO4ihplsjJx4RJo2oMsh0mdVdLTbPsYn4AVXST2jdISlrT81l39h8v3sMxtGgn
 iq7z2WiXCAyGnVhx2zfqt5FEXkuv1WFYq507GsI1BPotpdfRVRDj0h801NlG8JUg
 3g5h5fEo9ZFNaPxch0vu591zpHjWWW9CzA4/6Q8VivajaBG6/PA5GlVA7dWN3PvC
 mitnOtZoUN7zvyli+QRs43eOJ2llBuF8zfOTwUlQQrm2r1OntKBeXr/CCUsB5YpY
 q4zijEPQHtlitnXyRhffGc16u8oY/QQeFLzxJiPV+4Y/hifREpK6XRdNZJSy/00j
 ckrhN4R/hpMBEVKVS1l4sIx940I4n5x2Ix0fiXZ4ZUA55e3ODec=
 =13nd
 -----END PGP SIGNATURE-----

Merge tag 'cix-dt-binding-v6.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix into soc/dt

- Add OrangePi 6 Plus board

* tag 'cix-dt-binding-v6.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix:
  dt-bindings: arm: cix: add OrangePi 6 Plus board

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-28 18:58:34 +01:00
Arnd Bergmann
2af1017ca6 Microchip AT91 device tree updates for v6.20
This update includes:
 - update the SAMA7D65 flexcom nodes to add the missing i2c, spi, and usart
   child nodes; the flexcom child nodes were also updated with DMA
   properties
 - add basic support for the PCB8385 board, based on LAN966X SoC
 - drop usb_a9g20-dab-mmx.dtsi as it is not used anywhere in the tree
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYKAB0WIQTsZ8eserC1pmhwqDmejrg/N2X7/QUCaXSQjgAKCRCejrg/N2X7
 /ZHxAQDwi48o/wR6r7CGhFiXd/Kp7M4UyLLFRSCnRVF5fM2u0gEApSSxCRrlKkPZ
 ZNa4bNbNHYnojFjRUQhZ8ByW/07BIgU=
 =tUBH
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml6TiEACgkQmmx57+YA
 GNnTzA/5Abj1y4boeRfY5OOj/j/rl1xfYKRkBv87fz9QU6XDob4oUx/1MM039md3
 vp9oEr9kYfTuzJbiYggZ1aLSU8E1zQ2+lzW2TEUKfQwxn+QimhIZjAibi4ydbkzI
 5r25WkBMz379qVp7jdoPEq7/yltAeHxB7Hyiva5RmWZy2QfjIPIV2HWpLK5TU2E1
 HC2Si9H7kxLivbAPQn/ZRW0zdRyZxqX8C3NgztfEm97DxicYnf1mTtGhnsVn1VBC
 Vmeb1LKdd/fiwX2WeJSoahE0x0sLOtkHKHIrmTiURqNNIKCCFg6QTESXR6DKTzOr
 C2yfnnb/U7633tXK4k1VXWakqDVAd1qNBD70pHkxdu9u1YDVL350geWdGKQWkW5i
 dGE/5zInuQjthE0TTIYERCDYgJne1ViQUrTVuIEb+h4b6YgIqHrLuw+vMwflxM6B
 ncbPsPJrJuWF7kwFZ7NA2GFVOyf7J2GAlQILBY3lGeu/uhSoVQ9FUMIdEXWmMMCP
 myAefEO3laMJEwphCF7UZ8yZPYTfyUtxZX+MbnBKTlrZCO8kai2bIGiCWLC46OIA
 VMvUQeXW8Ojem0SIq8Mid1AtBV1Y6ad7AULfz8+TBgQEr+ba1pOVGv7vlCK+s1om
 mZosRj5+2B5r39wgMW8Xhaa2g+xN/DNjTjrkeW3UHIGpKF1Lwyc=
 =Yszk
 -----END PGP SIGNATURE-----

Merge tag 'at91-dt-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt

Microchip AT91 device tree updates for v6.20

This update includes:
- update the SAMA7D65 flexcom nodes to add the missing i2c, spi, and usart
  child nodes; the flexcom child nodes were also updated with DMA
  properties
- add basic support for the PCB8385 board, based on LAN966X SoC
- drop usb_a9g20-dab-mmx.dtsi as it is not used anywhere in the tree

* tag 'at91-dt-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  ARM: dts: microchip: Drop usb_a9g20-dab-mmx.dtsi
  ARM: dts: Add support for pcb8385
  dt-bindings: arm: at91: add lan966 pcb8385 board
  ARM: dts: microchip: sama7d65: add missing flexcom nodes
  ARM: dts: microchip: sama7d65: add fifo-size to usart
  ARM: dts: microchip: sama7d65: add dma properties to usart6

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-28 18:57:51 +01:00
Arnd Bergmann
52c1a896a9 - add OrangePi 6 Plus board
- one small improvement
 -----BEGIN PGP SIGNATURE-----
 
 iQHLBAABCgA1FiEEE9MyVaemtW1m4wM6rfNrQFP6hVAFAml0DtYXHHBldGVyLmNo
 ZW5AY2l4dGVjaC5jb20ACgkQrfNrQFP6hVCODAv+MKZbcHSIc5nGMl6AqIBEeg8t
 /yM/U2rXXkU9V+XvS9qCxFuX2CAU4Z+IZIghiwsn83a9tB0n8xVPEsuDeB27FEkC
 d2G9Nsb9mPUzBXEbrUo6/a3d2sD13jlhwMUwjV+SsPLHpA0rX2QkkfUnbIaZbHPp
 ++0FtG9YGISwEFHjU9VHTJuSg5+ok6ozgT2GpqbapglmBjc+O4Mb/ZfanCiL2ep3
 QoUHPAXDCLrdViSlxlwu62LVosvYI5pB7MNclibo2L+VvUp7i4cPnhZjxZ8NwICP
 0wHEIWOB2FF6sqjXrNkueunqPMf8EyO19EOwr3MMr+ZzSpRk8tpDKImj6cUVVOHj
 XC8ue/sy292kDfclR9bLAG/Db8aE+PqqpFPnGdhpDOTrb1WovVA8rdDcaH7OHVj9
 6R6yET2Imb2ws4A8I9o4zLGH4/jtZkIDd7FX+D5hVWHo5N/OYZOaETOrfefwWVmJ
 mbGS2PFkJw6N70FgS0C0FWSyIP8PFXQGos9+W/1t
 =bCpG
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAml6TJUACgkQmmx57+YA
 GNmfJhAAre8gIj6FS6gr0Prw3R8qootQnuEX5o0jw4a+1CoGUIF8/Hie8qJLHpKk
 IdDN4eYtI/OeHcjf0JlSlx8SzAFdBAaS//IqURrRCWfB8uS9MNw9hJHnaaQJWtf7
 c/9nahikw/dC+1oAMulSx166w361UWdQdAOGtwq2kwmLvqI9tOUvl/uXfQA3tqTL
 vQh0eVNWCQlSoGNYsiTBDYIRipXOlvycEggIFlbTu6lwFfH/HlmEY9A+qJ63nBFJ
 jKV/BgYe91OSnmsALZwpwLFQJ980yS1O+VN47PkcjoNbjDYBqZKR60eMShC+EoRj
 GqVrtwdrDVtyBNta0wUCWqESGQ4sggu05fQVt0qcgXglh26LPn89dWRaaBkWRhdx
 bRK/kKhksQyDIoaxY6m/5ehFBQ0OzWZALDDjaFS6SlhJlsg81xaPBJjp5AWfrt7C
 JosKP5nNABWWxQPXm8BOHw3l+PQUM8FTQdvEh1Ij5mxT6BMcv/Rz5u9nY3Gcf3IQ
 4WweFC7VDzrC/yrsGdSz6fovIhue5AiNN1cRJEXMUYG5FXbbSCeKD1fKg6BlCK5Y
 XfTxFhrSmQ5GZ+Rx7Fv1yxeTY2HySUd3b0I1GP3UV/3d+2Z8/XG0ZK76eybsfT/X
 VnZ+ljUbWJJRgvMsOAoQb1kQZRPzfYrCG85jof8KNp1T58l0BHE=
 =BpW0
 -----END PGP SIGNATURE-----

Merge tag 'cix-dt-v6.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix into soc/dt

- add OrangePi 6 Plus board
- one small improvement

* tag 'cix-dt-v6.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix:
  arm64: dts: cix: Add OrangePi 6 Plus board support
  arm64: dts: cix: Use lowercase hex

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-28 18:51:14 +01:00