Add support for Armada 7020 Express Type 7 CPU module board by Marvell, including:
- COM Express CPU module and carrier board (Marvell DB-98CX85x0)
- DDR4 memory, 1Gbit OOB Ethernet, 10G KR Ethernet, NAND/SPI flash, PCIe, SATA, USB, and UART interfaces
Add SoC-specific compatibles for SafeXcel crypto engine on Armada 37xx and CP11x
Fix regulator type from "regulator-gpio" to "regulator-fixed" where no GPIO control is present
Add missing GPIO properties for "nxp,pca9536" on cn9131-cf-solidwan
Fix and clean up pinctrl-names properties and typos
Add missing "#phy-cells" to "usb-nop-xceiv" nodes
MAINTAINERS: Add Falcon DB to the list of maintained Marvell Armada dts files
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Merge tag 'mvebu-dt64-6.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
mvebu dt64 for 6.20 (part 1)
Add support for Armada 7020 Express Type 7 CPU module board by Marvell, including:
- COM Express CPU module and carrier board (Marvell DB-98CX85x0)
- DDR4 memory, 1Gbit OOB Ethernet, 10G KR Ethernet, NAND/SPI flash, PCIe, SATA, USB, and UART interfaces
Add SoC-specific compatibles for SafeXcel crypto engine on Armada 37xx and CP11x
Fix regulator type from "regulator-gpio" to "regulator-fixed" where no GPIO control is present
Add missing GPIO properties for "nxp,pca9536" on cn9131-cf-solidwan
Fix and clean up pinctrl-names properties and typos
Add missing "#phy-cells" to "usb-nop-xceiv" nodes
MAINTAINERS: Add Falcon DB to the list of maintained Marvell Armada dts files
* tag 'mvebu-dt64-6.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
MAINTAINERS: Add Falcon DB
arm64: dts: a7k: add COM Express boards
arm64: dts: marvell: Add SoC specific compatibles to SafeXcel crypto
arm64: dts: marvell: change regulator-gpio to regulator-fixed
arm64: dts: marvell: cn9131-cf-solidwan: Add missing GPIO properties on "nxp,pca9536"
arm64: dts: marvell: Fix stray and typo "pinctrl-names" properties
arm64: dts: marvell: Add missing "#phy-cells" to "usb-nop-xceiv"
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This adds support for new boards and variants based on different
already supported MediaTek SoCs, and improves support for current
boards.
In particular:
- New machines:
- Ezurio Tungsten 510 (MediaTek Genio 510 SoC)
- Ezurio Tungsten 700 (MediaTek Genio 700 SoC)
...improvements for already supported SoCs and machines:
- MT7981b gains support for PCI-Express, USB, Ethernet and for
the "GED" WiFi HW offload
- OpenWRT One board gains support for the same
- MT8188/8195/8390/8395 gains support for the DPI1 interface
and HDMI output from the SoC's HDMI Tx controller along with
its HDMI PHY and DDC IPs, usable on a selection of boards
that expose a HDMI connector, namely:
- All MT8390 Genio EVK based boards
- All MT8395 Genio EVK based boards
- Radxa NIO-12L (MT8395)
...and dtbs_check warning fixes for many of the MTK devicetrees,
including MT6795, MT7981, MT7986, MT7988, MT8173, MT8183, MT8186,
MT8188, MT8192, and a dts coding style fix for Airoha EN7581-EVB.
This also includes a fix for the new devicetree overlay warnings,
adding dtbs with applied overlays for all of the devices having
at least one overlay.
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Merge tag 'mtk-dts64-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
MediaTek ARM64 Device Tree updates
This adds support for new boards and variants based on different
already supported MediaTek SoCs, and improves support for current
boards.
In particular:
- New machines:
- Ezurio Tungsten 510 (MediaTek Genio 510 SoC)
- Ezurio Tungsten 700 (MediaTek Genio 700 SoC)
...improvements for already supported SoCs and machines:
- MT7981b gains support for PCI-Express, USB, Ethernet and for
the "GED" WiFi HW offload
- OpenWRT One board gains support for the same
- MT8188/8195/8390/8395 gains support for the DPI1 interface
and HDMI output from the SoC's HDMI Tx controller along with
its HDMI PHY and DDC IPs, usable on a selection of boards
that expose a HDMI connector, namely:
- All MT8390 Genio EVK based boards
- All MT8395 Genio EVK based boards
- Radxa NIO-12L (MT8395)
...and dtbs_check warning fixes for many of the MTK devicetrees,
including MT6795, MT7981, MT7986, MT7988, MT8173, MT8183, MT8186,
MT8188, MT8192, and a dts coding style fix for Airoha EN7581-EVB.
This also includes a fix for the new devicetree overlay warnings,
adding dtbs with applied overlays for all of the devices having
at least one overlay.
* tag 'mtk-dts64-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: (47 commits)
arm64: dts: mediatek: mt8192: Rename mt8192-afe-pcm to audio-controller
dt-bindings: arm: mediatek: audsys: Support mt8192-audsys variant
arm64: dts: mediatek: mt7988a: Fix PCI-Express T-PHY node address
arm64: dts: mediatek: mt8186-evb: Add vproc fixed regulator
arm64: dts: mediatek: mt7981b-openwrt-one: Add address/size cells to eth
arm64: dts: mediatek: mt8183-kukui: Clean up IT6505 regulator supply
arm64: dts: mediatek: mt7986a: Change compatible for SafeXcel crypto
arm64: dts: mediatek: mt8173-evb: Add interrupts to DA9211 regulator
arm64: dts: mediatek: mt6795-xperia-m5: Rename PMIC leds node
arm64: dts: mediatek: mt6795: Fix issues in SCPSYS node
arm64: dts: mediatek: mt6331: Fix VCAM IO regulator name
arm64: dts: mediatek: mt6795-xperia-m5: Add UHS pins for MMC1 and 2
arm64: dts: mediatek: mt8192-asurada: Remove unused clock-stretch-ns
arm64: dts: mediatek: mt8173-elm: Remove regulators from thermal node
arm64: dts: mediatek: mt8173-elm: Fix dsi0 ports warning
arm64: dts: mediatek: mt8173-elm: Fix bluetooth node name and reorder
arm64: dts: mediatek: mt8183-pumpkin: Fix pinmux node names
arm64: dts: mediatek: mt8183-jacuzzi-pico6: Fix typo in pinmux node
arm64: dts: mediatek: mt7981b-openwrt-one: Remove useless cells from flash@0
arm64: dts: mediatek: mt8183-evb: Fix dtbs_check warnings
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Not many changes this cycle.
- The A523 family of SoCs gained support for SPI controllers.
- Some cleanup of old ARM device tree files to fix DT binding validation
errors.
- D1 and A100 SoCs gained support for their LED controller. This was
from a couple years ago. The driver made it in, but the DT patches
were missed.
- D1 and T113 SoCs gained support for the internal thermal sensor.
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Merge tag 'sunxi-dt-for-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
Allwinner device tree changes for 6.20
Not many changes this cycle.
- The A523 family of SoCs gained support for SPI controllers.
- Some cleanup of old ARM device tree files to fix DT binding validation
errors.
- D1 and A100 SoCs gained support for their LED controller. This was
from a couple years ago. The driver made it in, but the DT patches
were missed.
- D1 and T113 SoCs gained support for the internal thermal sensor.
* tag 'sunxi-dt-for-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
riscv: dts: allwinner: d1: Add CPU thermal sensor and zone
ARM: dts: allwinner: Replace status "failed" with "fail"
riscv: dts: allwinner: d1: Add RGB LEDs to boards
riscv: dts: allwinner: d1: Add LED controller node
arm64: dts: allwinner: a100: Add LED controller node
ARM: dts: allwinner: sun5i-a13-utoo-p66: delete "power-gpios" property
arm64: dts: allwinner: t527: orangepi-4a: Enable SPI-NOR flash
arm64: dts: allwinner: sun55i: Add SPI controllers
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Cleanups:
- Use lowercase hex
- Use hyphen in node names
- move CPU OPP table and clock assignment to SoC.dtsi
- drop useless assigned-clock-parents
- MMC clock fixup across multiple families
- Add type-c controller on Radxa Zero 2 and enable NPU
- New board:
- Khadas VIM1s based on Amlogic S4
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Merge tag 'amlogic-arm64-dt-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
Amlogic ARM64 DT for v6.20:
- Cleanups:
- Use lowercase hex
- Use hyphen in node names
- move CPU OPP table and clock assignment to SoC.dtsi
- drop useless assigned-clock-parents
- MMC clock fixup across multiple families
- Add type-c controller on Radxa Zero 2 and enable NPU
- New board:
- Khadas VIM1s based on Amlogic S4
* tag 'amlogic-arm64-dt-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux:
arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: enable SDIO interface
arm64: dts: amlogic: add the type-c controller on Radxa Zero 2
arm64: dts: amlogic: meson-sm1-odroid: Eliminate Odroid HC4 power glitches during boot.
arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: enable eMMC storage
arm64: dts: meson-s4-s905y4-khadas-vim1s: add initial device tree
arm64: dts: meson-s4-aq222: update compatible string with s805x2
dt-bindings: arm: amlogic: introduce specific compatibles for S4 family
arm64: dts: amlogic: Enable the npu node on Radxa Zero 2
arm64: dts: amlogic: g12: assign the MMC A signal clock
arm64: dts: amlogic: g12: assign the MMC B and C signal clocks
arm64: dts: amlogic: gx: assign the MMC signal clocks
arm64: dts: amlogic: axg: assign the MMC signal clocks
arm64: dts: amlogic: a1: align the mmc clock setup
arm64: dts: amlogic: c3: assign the MMC signal clocks
arm64: dts: amlogic: s4: fix mmc clock assignment
arm64: dts: amlogic: s4: assign mmc b clock to 24MHz
arm64: dts: amlogic: drop useless assigned-clock-parents
arm64: dts: amlogic: move CPU OPP table and clock assignment to SoC.dtsi
arm64: dts: amlogic: Use lowercase hex
arm64: dts: amlogic: Use hyphen in node names
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
If a process wrote to POR_EL0 and then crashed before a context switch
happened, the coredump would contain an incorrect value for POR_EL0.
The value read in poe_get() would be a stale value left in thread.por_el0. Fix
this by reading the value from the system register, if the target thread is the
current thread.
This matches what gcs/fpsimd do.
Fixes: 1751981992 ("arm64/ptrace: add support for FEAT_POE")
Reported-by: David Spickett <david.spickett@arm.com>
Cc: stable@vger.kernel.org
Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Kevin Brodsky <kevin.brodsky@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Kevin Brodsky <kevin.brodsky@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Add support for handling PCIe M.2 connectors as Power Sequencing devices.
These connectors are exposed as Power Sequencing devices as they often
support multiple interfaces like PCIe/SATA, USB/UART to the host machine,
and the interfaces may be driven by different client drivers at the same
time.
This driver handles the PCIe interface of these connectors. It first checks
for the presence of the graph port in the Root Port node with the help of
of_graph_is_present() API. If present, it acquires/powers ON the
corresponding pwrseq device.
Once the pwrseq device is powered ON, the driver will skip parsing the Root
Port/Slot resources and register with the pwrctrl framework.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://patch.msgid.link/20260128-pci-m2-v7-1-9b3a5fe3d244@oss.qualcomm.com
Sophgo:
For CV18xx serials:
Update RX/TX FIFO size to fix the USB transfer issue.
For SG2042:
Optimize the DTS file format, including moving PLIC/CLINT
nodes into cpu dtsi and sorting peripheral nodes by address.
In addition, we also enable RTC for Pioneerbox.
For SG2044:
Add "b" ISA extension to fix dtbs_check warnings.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
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Merge tag 'riscv-sophgo-dt-for-v6.20' of https://github.com/sophgo/linux into soc/dt
RISC-V/Sophgo Devicetrees for v6.20
Sophgo:
For CV18xx serials:
Update RX/TX FIFO size to fix the USB transfer issue.
For SG2042:
Optimize the DTS file format, including moving PLIC/CLINT
nodes into cpu dtsi and sorting peripheral nodes by address.
In addition, we also enable RTC for Pioneerbox.
For SG2044:
Add "b" ISA extension to fix dtbs_check warnings.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* tag 'riscv-sophgo-dt-for-v6.20' of https://github.com/sophgo/linux:
riscv: dts: sophgo: sg2044: Add "b" ISA extension
riscv: dts: sophgo: fix the node order of SG2042 peripheral
riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi
riscv: dts: sophgo: enable hardware clock (RTC) on the Milk-V Pioneer
riscv: dts: sophgo: cv180x: fix USB dwc2 FIFO sizes
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Highlights:
----------
- MCU:
- Update/add Led support on ST boards.
- MPU:
- STM32MP13:
- Add boot led and red led on ST DK board.
- STMP32MP15:
- Add boot led and red led on ST DK boards.
- Add SPI1 sleep pinctrl group.
- STM32MP23:
- Add green ,orange and boot leds on ST boards.
- Add SPI, I2C, DCMIPP and CSI instances to CLUSTER_PD
power domain.
- Enable analog-filter to all I2C instances.
- STM32MP25:
- Add green ,orange and boot leds on ST boards.
- Add SPI, I2C, DCMIPP and CSI instances to CLUSTER_PD
power domain.
- Enable analog-filter to all I2C instances.
- Add LPDDR/DDR channels to ST boards.
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Merge tag 'stm32-dt-for-v6.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
STM32 DT for v6.20, round 1
Highlights:
----------
- MCU:
- Update/add Led support on ST boards.
- MPU:
- STM32MP13:
- Add boot led and red led on ST DK board.
- STMP32MP15:
- Add boot led and red led on ST DK boards.
- Add SPI1 sleep pinctrl group.
- STM32MP23:
- Add green ,orange and boot leds on ST boards.
- Add SPI, I2C, DCMIPP and CSI instances to CLUSTER_PD
power domain.
- Enable analog-filter to all I2C instances.
- STM32MP25:
- Add green ,orange and boot leds on ST boards.
- Add SPI, I2C, DCMIPP and CSI instances to CLUSTER_PD
power domain.
- Enable analog-filter to all I2C instances.
- Add LPDDR/DDR channels to ST boards.
* tag 'stm32-dt-for-v6.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (31 commits)
arm/arm64: dts: st: Drop unused .dtsi
arm64: STM32: drop an undefined Kconfig symbol
arm64: dts: st: Minor whitespace cleanup
arm64: dts: st: Use hyphen in node names
arm64: dts: st: add power-domain of dcmipp in stm32mp231.dtsi
arm64: dts: st: add power-domain of dcmipp in stm32mp251.dtsi
dt-bindings: media: st: dcmipp: add 'power-domains' property
arm64: dts: st: add power-domain of csi in stm32mp231.dtsi
arm64: dts: st: add power-domain of csi in stm32mp251.dtsi
dt-bindings: media: st: csi: add 'power-domains' property
ARM: dts: stm32: add spi1 sleep state pinctrl on stm32mp157c-ev1
arm64: dts: st: add DDR channel to stm32mp257f-ev1 board
arm64: dts: st: add LPDDR channel to stm32mp257f-dk board
arm64: dts: st: enable i2c analog-filter in stm32mp231.dtsi
arm64: dts: st: enable i2c analog-filter in stm32mp251.dtsi
arm64: dts: st: add power-domains in all i2c of stm32mp231.dtsi
arm64: dts: st: add power-domains in all i2c of stm32mp251.dtsi
dt-bindings: i2c: st,stm32-i2c: add 'power-domains' property
arm64: dts: st: add power-domains in all spi of stm32mp231.dtsi
arm64: dts: st: add power-domains in all spi of stm32mp251.dtsi
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Mark the Meson GPIO controller as sleeping to avoid a
context splat.
- Fix up the I2S2 and SWR TX group settings in the
Qualcomm SM8350 LPASS pin controller, and implement the
proper .get_direction() callback.
- Fix a pin typo in the TG1520 pin controller.
- Fix a group name in the Marvell armada 3710 XB pin
controller that got mangled in a DT schema rewrite.
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Merge tag 'pinctrl-v6.19-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij:
- Mark the Meson GPIO controller as sleeping to avoid a
context splat
- Fix up the I2S2 and SWR TX group settings in the
Qualcomm SM8350 LPASS pin controller, and implement the
proper .get_direction() callback
- Fix a pin typo in the TG1520 pin controller
- Fix a group name in the Marvell armada 3710 XB pin
controller that got mangled in a DT schema rewrite
* tag 'pinctrl-v6.19-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
dt-bindings: pinctrl: marvell,armada3710-xb-pinctrl: fix 'usb32_drvvbus0' group name
pinctrl: lpass-lpi: implement .get_direction() for the GPIO driver
pinctrl: th1520: Fix typo
pinctrl: qcom: sm8350-lpass-lpi: Merge with SC7280 to fix I2S2 and SWR TX pins
pinctrl: meson: mark the GPIO controller as sleeping
- New board support: i.MX8MP/i.MX91/i.MX93/i.MX95 FRDM, ifm VHIP4
EvalBoard, Apalis iMX8QP, TQ-Systems MBLS1028A/MBLS1028A-IND
- A number of series from Alexander Stein improving lpcg indices
description for tqma8xxs board, moving BMAN/QMAN buffers for
tqmls1046a, refreshing tqma8mpql-mba8mpxl support a bit, adding HDMI
audio support for tqma8mpql-mba8mp-ras314 etc.
- A series from Chancel Liu adding various audio features for
imx93-14x14-evk board
- A series from Francesco Dolcini enabling hdmi_pai device for
imx8mp-verdin and imx8mp-toradex-smarc
- A couple of changes from Francesco Valla enabling more devices
and correcting CAN transceiver gpio for imx93-11x11-frdm
- A few changes from Frank Li adding DDR perf support for imx8qm, adding
camera support for imx8mp-evk, enabling thermal support for i.MX91, etc.
- A series from Haibo Chen adding flexcan support for imx943-evk and
imx952-evk boards
- A series from Krzysztof Kozlowski fixing up coding style issues
- A couple of changes from Marek Vasut updating Data Modul i.MX8M Plus
eDM SBC DT to rev.903, using GPU_CGC as core clock for GPU on i.MX95
- A series from Markus Niebel to clean up imx8mm-tqma8mqml board
regulators
- A couple of series from Peng Fan replacing xceiver-supply with phys
for NXP EVK boards, improving imx952-evk board support
- A series from Sebastian Krzyszkowiak to refresh imx8mq-librem5 support
- A couple of series from Stefano Radaelli to improve
imx93-var-som-symphony and imx8mp-var-som support
- Other random changes for various boards
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Merge tag 'imx-dt64-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
i.MX arm64 device tree changes for 6.20:
- New board support: i.MX8MP/i.MX91/i.MX93/i.MX95 FRDM, ifm VHIP4
EvalBoard, Apalis iMX8QP, TQ-Systems MBLS1028A/MBLS1028A-IND
- A number of series from Alexander Stein improving lpcg indices
description for tqma8xxs board, moving BMAN/QMAN buffers for
tqmls1046a, refreshing tqma8mpql-mba8mpxl support a bit, adding HDMI
audio support for tqma8mpql-mba8mp-ras314 etc.
- A series from Chancel Liu adding various audio features for
imx93-14x14-evk board
- A series from Francesco Dolcini enabling hdmi_pai device for
imx8mp-verdin and imx8mp-toradex-smarc
- A couple of changes from Francesco Valla enabling more devices
and correcting CAN transceiver gpio for imx93-11x11-frdm
- A few changes from Frank Li adding DDR perf support for imx8qm, adding
camera support for imx8mp-evk, enabling thermal support for i.MX91, etc.
- A series from Haibo Chen adding flexcan support for imx943-evk and
imx952-evk boards
- A series from Krzysztof Kozlowski fixing up coding style issues
- A couple of changes from Marek Vasut updating Data Modul i.MX8M Plus
eDM SBC DT to rev.903, using GPU_CGC as core clock for GPU on i.MX95
- A series from Markus Niebel to clean up imx8mm-tqma8mqml board
regulators
- A couple of series from Peng Fan replacing xceiver-supply with phys
for NXP EVK boards, improving imx952-evk board support
- A series from Sebastian Krzyszkowiak to refresh imx8mq-librem5 support
- A couple of series from Stefano Radaelli to improve
imx93-var-som-symphony and imx8mp-var-som support
- Other random changes for various boards
* tag 'imx-dt64-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (104 commits)
arm64: dts: freescale: imx95: Add support for i.MX95 15x15 FRDM board
arm64: dts: imx91-11x11-frdm: fix CAN transceiver gpio
arm64: dts: imx93-11x11-frdm: enable additional devices
arm64: dts: imx93-11x11-frdm: Add MQS audio support
arm64: dts: imx952-evk: Add nxp,ctrl-ids for scmi misc
arm64: dts: imx952-evk: Add flexcan support
arm64: dts: imx952-evk: Enable TPM[3,6]
arm64: dts: imx952-evk: Enable wdog3
arm64: dts: imx952-evk: Enable USB[1,2]
arm64: dts: imx952-evk: Enable SPI7
arm64: dts: imx952-evk: Enable UART5
arm64: dts: imx952-evk: Enable I2C[2,3,4,6,7] bus
arm64: dts: imx952-evk: Change the usdhc1_200mhz drive strength to DSE4
arm64: dts: imx952: Add idle-states node
arm64: dts: imx8mn: Add ifm VHIP4 EvalBoard v1 and v2
arm64: dts: imx8mn: Add SNVS LPGPR
arm64: dts: imx8mq-librem5: Don't set mic-cfg for wm8962
arm64: dts: imx8mq-librem5: Set cap-power-off-card for usdhc2
arm64: dts: imx8mq-librem5: Limit uSDHC2 frequency to 50MHz
arm64: dts: imx8mq-librem5: Enable SNVS RTC
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This series updates various DT bindings for Tegra architecture,
primarily focusing on schema validation fixes and new feature
documentation for Tegra234 and Tegra264 SoCs. Key changes include
converting Tegra20 NAND bindings to YAML, and updating memory, DMA, and
IOMMU definitions for Tegra264 (introducing CMDQV and DBB clock
support). Additionally, it resolves legacy warnings for Tegra30/132
display and VI interfaces.
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Merge tag 'tegra-for-6.20-dt-bindings-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
dt-bindings: Changes for v6.20-rc1
This series updates various DT bindings for Tegra architecture,
primarily focusing on schema validation fixes and new feature
documentation for Tegra234 and Tegra264 SoCs. Key changes include
converting Tegra20 NAND bindings to YAML, and updating memory, DMA, and
IOMMU definitions for Tegra264 (introducing CMDQV and DBB clock
support). Additionally, it resolves legacy warnings for Tegra30/132
display and VI interfaces.
* tag 'tegra-for-6.20-dt-bindings-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: display: tegra: document Tegra30 VI and VIP
dt-bindings: display: tegra: document Tegra132 MIPI calibration device
dt-bindings: mtd: nvidia,tegra20-nand: convert to DT schema
dt-bindings: dma: Update ADMA bindings for tegra264
dt-bindings: iommu: Add NVIDIA Tegra CMDQV support
dt-bindings: memory: tegra: Document DBB clock for Tegra264
dt-bindings: tegra: pmc: Update aotag as an optional aperture
Make dma_set_max_seg_size() available to Rust so drivers can perform
standard DMA setup steps.
Signed-off-by: Beata Michalska <beata.michalska@arm.com>
Acked-by: Robin Murphy <robvin.murphy@arm.com>
Reviewed-by: Alice Ryhl <aliceryhl@google.com>
Link: https://patch.msgid.link/20260128135320.689046-1-beata.michalska@arm.com
Signed-off-by: Danilo Krummrich <dakr@kernel.org>
The LPSPI driver currently does not support setting SPI bus clock
polarity and phase, add support for it.
It is important to configure correct initial clock polarity and phase
before the GPIO chipselect toggles, otherwise a chip attached to the
bus might recognize the first change of clock signal as the first
clock cycle and get confused.
In order to set up the correct polarity and phase on the clock signal
before the GPIO chipselects get configured by the SPI core, the
controller has to be briefly brought up in fsl_lpspi_prepare_message().
The fsl_lpspi_prepare_message() behaves like a zero-length transfer
which always uses PIO and never DMA, and which leaves the clock signal
in the correct state at the end of such transfer, which happens before
the GPIO chipselect toggles.
Signed-off-by: Marek Vasut <marex@nabladev.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260127222353.1452003-1-marex@nabladev.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Async COPY operations hold copy stateids that represent NFSv4 state.
Thus, when the NFS server administrator revokes all NFSv4 state for
a filesystem via the unlock_fs interface, ongoing async COPY
operations referencing that filesystem must also be canceled.
Each cancelled copy triggers a CB_OFFLOAD callback carrying the
NFS4ERR_ADMIN_REVOKED status to notify the client that the server
terminated the operation.
The static drop_client() function is renamed to nfsd4_put_client()
and exported. The function must be exported because both the new
nfsd4_cancel_copy_by_sb() and the CB_OFFLOAD release callback in
nfs4proc.c need to release client references.
Reviewed-by: NeilBrown <neil@brown.name>
Reviewed-by: Jeff Layton <jlayton@kernel.org>
Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
Add a new "min_threads" variable to the nfsd_net, along with the
corresponding netlink interface, to set that value from userland.
Pass that value to svc_set_pool_threads() and svc_set_num_threads().
Signed-off-by: Jeff Layton <jlayton@kernel.org>
Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
nfsd() is changed to pass a timeout to svc_recv() when there is a min
number of threads set, and to handle error returns from it:
In the case of -ETIMEDOUT, if the service mutex can be taken (via
trylock), the thread becomes an RQ_VICTIM so that it will exit,
providing that the actual number of threads is above pool->sp_nrthrmin.
In the case of -EBUSY, if the actual number of threads is below
pool->sp_nrthrmax, it will attempt to start a new thread. This attempt
is gated on a new SP_TASK_STARTING pool flag that serializes thread
creation attempts within a pool, and further by mutex_trylock().
Neil says: "I think we want memory pressure to be able to push a thread
into returning -ETIMEDOUT. That can come later."
Signed-off-by: NeilBrown <neil@brown.name>
Signed-off-by: Jeff Layton <jlayton@kernel.org>
Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
To dynamically adjust the thread count, nfsd requires some information
about how busy things are.
Change svc_recv() to take a timeout value, and then allow the wait for
work to time out if it's set. If a timeout is not defined, then the
schedule will be set to MAX_SCHEDULE_TIMEOUT. If the task waits for the
full timeout, then have it return -ETIMEDOUT to the caller.
If it wakes up, finds that there is more work and that no threads are
available, then attempt to set SP_TASK_STARTING. If wasn't already set,
have the task return -EBUSY to cue to the caller that the service could
use more threads.
Signed-off-by: Jeff Layton <jlayton@kernel.org>
Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
Break out the part of svc_start_kthreads() that creates a thread into
svc_new_thread(), as a new exported helper function.
Signed-off-by: Jeff Layton <jlayton@kernel.org>
Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
Add a new pool->sp_nrthrmin field to track the minimum number of threads
in a pool. Add min_threads parameters to both svc_set_num_threads() and
svc_set_pool_threads(). If min_threads is non-zero and less than the
max, svc_set_num_threads() will ensure that the number of running
threads is between the min and the max.
If the min is 0 or greater than the max, then it is ignored, and the
maximum number of threads will be started, and never spun down.
For now, the min_threads is always 0, but a later patch will pass the
proper value through from nfsd.
Signed-off-by: Jeff Layton <jlayton@kernel.org>
Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
The kernel currently tracks the number of threads running in a pool in
the "sp_nrthreads" field. In the future, where threads are dynamically
spun up and down, it'll be necessary to keep track of the maximum number
of requested threads separately from the actual number running.
Add a pool->sp_nrthrmax parameter to track this. When userland changes
the number of threads in a pool, update that value accordingly.
Signed-off-by: Jeff Layton <jlayton@kernel.org>
Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
Now that svc_set_num_threads() handles distributing the threads among
the available pools, remove the special handling of a NULL pool pointer
from svc_start_kthreads() and svc_stop_kthreads().
Signed-off-by: Jeff Layton <jlayton@kernel.org>
Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
svc_set_num_threads() will set the number of running threads for a given
pool. If the pool argument is set to NULL however, it will distribute
the threads among all of the pools evenly.
These divergent codepaths complicate the move to dynamic threading.
Simplify the API by splitting these two cases into different helpers:
Add a new svc_set_pool_threads() function that sets the number of
threads in a single, given pool. Modify svc_set_num_threads() to
distribute the threads evenly between all of the pools and then call
svc_set_pool_threads() for each.
Signed-off-by: Jeff Layton <jlayton@kernel.org>
Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
Commit 7a94d5f31b ("soc: qcom: smem: better track SMEM uninitialized
state") changed the usage of __smem and init now as an error pointer
instead of NULL.
qcom_smem_is_available() wasn't updated to reflect this change and also
.qcom_smem_remove doesn't reset it on module exit.
Update both entry to reflect new handling of __smem.
Fixes: 7a94d5f31b ("soc: qcom: smem: better track SMEM uninitialized state")
Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
Closes: https://lore.kernel.org/all/aSAnR3ECa04CoPqp@stanley.mountain/
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251122185002.26524-1-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The call to nvme_free_sgls() in nvme_unmap_data() has the sg_list and sge
parameters swapped. This wasn't noticed by the compiler because both share
the same type. On a Xen PV hardware domain, and possibly any other
architectures that takes that path, this leads to corruption of the NVMe
contents.
Fixes: f0887e2a52 ("nvme-pci: create common sgl unmapping helper")
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Signed-off-by: Keith Busch <kbusch@kernel.org>
"pg_init_delay_msecs X" can be passed as a feature in the multipath
table and is used to set m->pg_init_delay_msecs in parse_features().
However, alloc_multipath_stage2(), which is called after
parse_features(), resets m->pg_init_delay_msecs to its default value.
Instead, set m->pg_init_delay_msecs in alloc_multipath(), which is
called before parse_features(), to avoid overwriting a value passed in
by the table.
Signed-off-by: Benjamin Marzinski <bmarzins@redhat.com>
Cc: stable@vger.kernel.org
This reverts commit f6007dce0c.
Commit f6007dce0c ("dm: fix a race condition in retrieve_deps") was
added to fix a race between retrieving the list of dm table devices and
multipath_message() modifying the list of table devices. But Commit
a48f6b82c5 ("dm mpath: don't call dm_get_device in multipath_message")
removed the call to dm_get_device() from multipath_message(). After that
commit, the only calls to dm_get_device() and dm_put_device() are in
target constructors and destructors, so the race with retrieve_deps() is
no longer possible.
Suggested-by: Martin Wilck <mwilck@suse.com>
Signed-off-by: Benjamin Marzinski <bmarzins@redhat.com>
Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
When commit fd81bc5cca ("scsi: device_handler: Return error pointer in
scsi_dh_attached_handler_name()") added code to fail parsing the path if
scsi_dh_attached_handler_name() failed with -ENOMEM, it didn't clean up
the reference to the path device that had just been taken. Fix this, and
steamline the error paths of parse_path() a little.
Fixes: fd81bc5cca ("scsi: device_handler: Return error pointer in scsi_dh_attached_handler_name()")
Cc: stable@vger.kernel.org
Signed-off-by: Benjamin Marzinski <bmarzins@redhat.com>
Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
GPIO Address Space handler gets a pointer to the in or out value.
This value is supposed to be at least 64-bit, but it's not limited
to be exactly 64-bit. When ACPI tables are being parsed, for
the bigger Connection():s ACPICA creates a Buffer instead of regular
Integer object. The Buffer exists as long as Namespace holds
the certain Connection(). Hence we can access the necessary bits
without worrying. On the other hand, the left shift, used in
the code, is limited by 31 (on 32-bit platforms) and otherwise
considered to be Undefined Behaviour. Also the code uses only
the first 64-bit word for the value, and anything bigger than 63
will be also subject to UB. Fix all this by modifying the code
to correctly set or clear the respective bit in the bitmap constructed
of 64-bit words.
Fixes: 59084c564c41 ("gpiolib: acpi: use BIT_ULL() for u64 mask in address space handler")
Fixes: 2c4d00cb8f ("gpiolib: acpi: Use BIT() macro to increase readability")
Cc: stable@vger.kernel.org
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://patch.msgid.link/20260128095918.4157491-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
The cache flush was happening on every level across the whole range of
iteration, even if no leafs or tables were cleared. Instead flush only the
sub range that was actually written.
Overflushing isn't a correctness problem but it does impact the
performance of unmap.
After this series the performance compared to the original VT-d
implementation with cache flushing turned on is:
map_pages
pgsz ,avg new,old ns, min new,old ns , min % (+ve is better)
2^12, 253,266 , 213,227 , 6.06
2^21, 246,244 , 221,219 , 0.00
2^30, 231,240 , 209,217 , 3.03
256*2^12, 2604,2668 , 2415,2540 , 4.04
256*2^21, 2495,2824 , 2390,2734 , 12.12
256*2^30, 2542,2845 , 2380,2718 , 12.12
unmap_pages
pgsz ,avg new,old ns, min new,old ns , min % (+ve is better)
2^12, 259,292 , 222,251 , 11.11
2^21, 255,259 , 227,236 , 3.03
2^30, 238,254 , 217,230 , 5.05
256*2^12, 2751,2620 , 2417,2437 , 0.00
256*2^21, 2461,2526 , 2377,2423 , 1.01
256*2^30, 2498,2543 , 2370,2404 , 1.01
Fixes: efa03dab7c ("iommupt: Flush the CPU cache after any writes to the page table")
Reported-by: Francois Dugast <francois.dugast@intel.com>
Closes: https://lore.kernel.org/all/20260121130233.257428-1-francois.dugast@intel.com/
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com>
Tested-by: Francois Dugast <francois.dugast@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
When building with -Wincompatible-function-pointer-types-strict, a
warning designed to catch kernel control flow integrity (kCFI) issues at
build time, there is an instance around amd_iommufd_hw_info():
drivers/iommu/amd/iommu.c:3141:13: error: incompatible function pointer types initializing 'void *(*)(struct device *, u32 *, enum iommu_hw_info_type *)' (aka 'void *(*)(struct device *, unsigned int *, enum iommu_hw_info_type *)') with an expression of type 'void *(struct device *, u32 *, u32 *)' (aka 'void *(struct device *, unsigned int *, unsigned int *)') [-Werror,-Wincompatible-function-pointer-types-strict]
3141 | .hw_info = amd_iommufd_hw_info,
| ^~~~~~~~~~~~~~~~~~~
While 'u32 *' and 'enum iommu_hw_info_type *' are ABI compatible, hence
no regular warning from -Wincompatible-function-pointer-types, the
mismatch will trigger a kCFI violation when amd_iommufd_hw_info() is
called indirectly.
Update the type parameter of amd_iommufd_hw_info() to be
'enum iommu_hw_info_type *' to match the prototype in
'struct iommu_ops', clearing up the warning and kCFI violation.
Fixes: 7d8b06ecc4 ("iommu/amd: Add support for hw_info for iommu capability query")
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Reviewed-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
The DesignWare EP core has supported updating the inbound iATU mapping
for an already configured BAR (i.e. allowing pci_epc_set_bar() to be
called again without a prior pci_epc_clear_bar()) since
commit 4284c88fff ("PCI: designware-ep: Allow pci_epc_set_bar() update
inbound map address").
Now that this capability is exposed via the dynamic_inbound_mapping EPC
feature bit, set it for DWC-based EP glue drivers using a common
initializer macro to avoid duplicating the same flag in each driver.
Note that pci-layerscape-ep.c is untouched. It currently constructs the
feature struct dynamically in ls_pcie_ep_init(). Once converted to a
static feature definition, it will use DWC_EPC_COMMON_FEATURES as well.
Signed-off-by: Koichiro Den <den@valinux.co.jp>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260124145012.2794108-4-den@valinux.co.jp
Some endpoint platforms have only a small number of usable BARs. At the
same time, EPF drivers (e.g. vNTB) may need multiple independent inbound
regions (control/scratchpad, one or more memory windows, and optionally
MSI or other feature-related regions). Subrange mapping allows these to
share a single BAR without consuming additional BARs that may not be
available, or forcing a fragile layout by aggressively packing into a
single contiguous memory range.
Extend the PCI endpoint core to support mapping subranges within a BAR.
Add an optional 'submap' field in struct pci_epf_bar so an endpoint
function driver can request inbound mappings that fully cover the BAR.
Introduce a new EPC feature bit, subrange_mapping, and reject submap
requests from pci_epc_set_bar() unless the controller advertises both
subrange_mapping and dynamic_inbound_mapping features.
The submap array describes the complete BAR layout (no overlaps and no
gaps are allowed to avoid exposing untranslated address ranges). This
provides the generic infrastructure needed to map multiple logical
regions into a single BAR at different offsets, without assuming a
controller-specific inbound address translation mechanism.
Signed-off-by: Koichiro Den <den@valinux.co.jp>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Link: https://patch.msgid.link/20260124145012.2794108-3-den@valinux.co.jp
Introduce a new EPC feature bit (dynamic_inbound_mapping) that indicates
whether an Endpoint Controller can update the inbound address
translation for a BAR without requiring the EPF driver to clear/reset
the BAR first.
Endpoint Function drivers (e.g. vNTB) can use this information to decide
whether it really is safe to call pci_epc_set_bar() multiple times to
update inbound mappings for the BAR.
Suggested-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Koichiro Den <den@valinux.co.jp>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260124145012.2794108-2-den@valinux.co.jp
There is no clear sign why we have tng_pinctrl_probe() in the first
place when it has already been using managed calls. Join the function
into its devm_tng_pinctrl_probe() wrapper.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
The pin control core is covered to report any error via message.
Since that it's not needed in the callers.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
The pin control core is covered to report any error via message.
Since that it's not needed in the callers.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
The pin control core is covered to report any error via message.
Since that it's not needed in the callers.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
The pin control core is covered to report any error via message.
Since that it's not needed in the callers.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
The pin control core is covered to report any error via message.
Since that it's not needed in the callers.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
When fp-pidbench was originally written SVE hardware was not widely
available so it was useful to run it in emulation and the default number
of loops was set very low, running for less than a second on actual
hardware. Now that SVE hardware is reasonably available it is very much
less interesting to use emulation, bump the default number of loops up to
even out a bit of the noise on real systems. On the machine I have to hand
this now takes about 15s which is still a toy microbenchmark but perhaps a
bit more useful.
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>
Some applications use SVE intermittently, one common case being where SVE
is used during statup (eg, by ld.so) but then rarely if ever during the
main application runtime. Add a repeat of the no SVE loop after we've done
the SVE loops to fp-pidbench to capture results for that.
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>
Passing IRQF_ONESHOT ensures that the interrupt source is masked until
the secondary (threaded) handler is done. If only a primary handler is
used then the flag makes no sense because the interrupt can not fire
(again) while its handler is running.
The flag also disallows force-threading of the primary handler and the
irq-core will warn about this.
The intention here was probably not allowing forced-threading.
Replace IRQF_ONESHOT with IRQF_NO_THREAD.
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Will Deacon <will@kernel.org>
