mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/
synced 2026-11-13 07:31:07 +00:00
600 commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Vivian Wang
|
64a0d47e0c |
riscv: boot: Always make Image from vmlinux, not vmlinux.unstripped
commit |
||
Sergey Matyukevich
|
9f393d8e75 |
riscv: dts: allwinner: d1: fix vlenb property
According to [1], the C906 vector registers are 128 bits wide.
The 'thead,vlenb' property specifies the vector register length
in bytes, so its value must be set to 16.
[1] https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
Fixes:
|
||
Linus Torvalds
|
07fdad3a93 |
Networking changes for 6.18.
Core & protocols
----------------
- Improve drop account scalability on NUMA hosts for RAW and UDP sockets
and the backlog, almost doubling the Pps capacity under DoS.
- Optimize the UDP RX performance under stress, reducing contention,
revisiting the binary layout of the involved data structs and
implementing NUMA-aware locking. This improves UDP RX performance by
an additional 50%, even more under extreme conditions.
- Add support for PSP encryption of TCP connections; this mechanism has
some similarities with IPsec and TLS, but offers superior HW offloads
capabilities.
- Ongoing work to support Accurate ECN for TCP. AccECN allows more than
one congestion notification signal per RTT and is a building block for
Low Latency, Low Loss, and Scalable Throughput (L4S).
- Reorganize the TCP socket binary layout for data locality, reducing
the number of touched cachelines in the fastpath.
- Refactor skb deferral free to better scale on large multi-NUMA hosts,
this improves TCP and UDP RX performances significantly on such HW.
- Increase the default socket memory buffer limits from 256K to 4M to
better fit modern link speeds.
- Improve handling of setups with a large number of nexthop, making dump
operating scaling linearly and avoiding unneeded synchronize_rcu() on
delete.
- Improve bridge handling of VLAN FDB, storing a single entry per bridge
instead of one entry per port; this makes the dump order of magnitude
faster on large switches.
- Restore IP ID correctly for encapsulated packets at GSO segmentation
time, allowing GRO to merge packets in more scenarios.
- Improve netfilter matching performance on large sets.
- Improve MPTCP receive path performance by leveraging recently
introduced core infrastructure (skb deferral free) and adopting recent
TCP autotuning changes.
- Allow bridges to redirect to a backup port when the bridge port is
administratively down.
- Introduce MPTCP 'laminar' endpoint that con be used only once per
connection and simplify common MPTCP setups.
- Add RCU safety to dst->dev, closing a lot of possible races.
- A significant crypto library API for SCTP, MPTCP and IPv6 SR, reducing
code duplication.
- Supports pulling data from an skb frag into the linear area of an XDP
buffer.
Things we sprinkled into general kernel code
--------------------------------------------
- Generate netlink documentation from YAML using an integrated
YAML parser.
Driver API
----------
- Support using IPv6 Flow Label in Rx hash computation and RSS queue
selection.
- Introduce API for fetching the DMA device for a given queue, allowing
TCP zerocopy RX on more H/W setups.
- Make XDP helpers compatible with unreadable memory, allowing more
easily building DevMem-enabled drivers with a unified XDP/skbs
datapath.
- Add a new dedicated ethtool callback enabling drivers to provide the
number of RX rings directly, improving efficiency and clarity in RX
ring queries and RSS configuration.
- Introduce a burst period for the health reporter, allowing better
handling of multiple errors due to the same root cause.
- Support for DPLL phase offset exponential moving average, controlling
the average smoothing factor.
Device drivers
--------------
- Add a new Huawei driver for 3rd gen NIC (hinic3).
- Add a new SpacemiT driver for K1 ethernet MAC.
- Add a generic abstraction for shared memory communication devices
(dibps)
- Ethernet high-speed NICs:
- nVidia/Mellanox:
- Use multiple per-queue doorbell, to avoid MMIO contention issues
- support adjacent functions, allowing them to delegate their
SR-IOV VFs to sibling PFs
- support RSS for IPSec offload
- support exposing raw cycle counters in PTP and mlx5
- support for disabling host PFs.
- Intel (100G, ice, idpf):
- ice: support for SRIOV VFs over an Active-Active link aggregate
- ice: support for firmware logging via debugfs
- ice: support for Earliest TxTime First (ETF) hardware offload
- idpf: support basic XDP functionalities and XSk
- Broadcom (bnxt):
- support Hyper-V VF ID
- dynamic SRIOV resource allocations for RoCE
- Meta (fbnic):
- support queue API, zero-copy Rx and Tx
- support basic XDP functionalities
- devlink health support for FW crashes and OTP mem corruptions
- expand hardware stats coverage to FEC, PHY, and Pause
- Wangxun:
- support ethtool coalesce options
- support for multiple RSS contexts
- Ethernet virtual:
- Macsec:
- replace custom netlink attribute checks with policy-level checks
- Bonding:
- support aggregator selection based on port priority
- Microsoft vNIC:
- use page pool fragments for RX buffers instead of full pages to
improve memory efficiency
- Ethernet NICs consumer, and embedded:
- Qualcomm: support Ethernet function for IPQ9574 SoC
- Airoha: implement wlan offloading via NPU
- Freescale
- enetc: add NETC timer PTP driver and add PTP support
- fec: enable the Jumbo frame support for i.MX8QM
- Renesas (R-Car S4): support HW offloading for layer 2 switching
- support for RZ/{T2H, N2H} SoCs
- Cadence (macb): support TAPRIO traffic scheduling
- TI:
- support for Gigabit ICSS ethernet SoC (icssm-prueth)
- Synopsys (stmmac): a lot of cleanups
- Ethernet PHYs:
- Support 10g-qxgmi phy-mode for AQR412C, Felix DSA and Lynx PCS
driver
- Support bcm63268 GPHY power control
- Support for Micrel lan8842 PHY and PTP
- Support for Aquantia AQR412 and AQR115
- CAN:
- a large CAN-XL preparation work
- reorganize raw_sock and uniqframe struct to minimize memory usage
- rcar_canfd: update the CAN-FD handling
- WiFi:
- extended Neighbor Awareness Networking (NAN) support
- S1G channel representation cleanup
- improve S1G support
- WiFi drivers:
- Intel (iwlwifi):
- major refactor and cleanup
- Broadcom (brcm80211):
- support for AP isolation
- RealTek (rtw88/89) rtw88/89:
- preparation work for RTL8922DE support
- MediaTek (mt76):
- HW restart improvements
- MLO support
- Qualcomm/Atheros (ath10k_
- GTK rekey fixes
- Bluetooth drivers:
- btusb: support for several new IDs for MT7925
- btintel: support for BlazarIW core
- btintel_pcie: support for _suspend() / _resume()
- btintel_pcie: support for Scorpious, Panther Lake-H484 IDs
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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Merge tag 'net-next-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next
Pull networking updates from Paolo Abeni:
"Core & protocols:
- Improve drop account scalability on NUMA hosts for RAW and UDP
sockets and the backlog, almost doubling the Pps capacity under DoS
- Optimize the UDP RX performance under stress, reducing contention,
revisiting the binary layout of the involved data structs and
implementing NUMA-aware locking. This improves UDP RX performance
by an additional 50%, even more under extreme conditions
- Add support for PSP encryption of TCP connections; this mechanism
has some similarities with IPsec and TLS, but offers superior HW
offloads capabilities
- Ongoing work to support Accurate ECN for TCP. AccECN allows more
than one congestion notification signal per RTT and is a building
block for Low Latency, Low Loss, and Scalable Throughput (L4S)
- Reorganize the TCP socket binary layout for data locality, reducing
the number of touched cachelines in the fastpath
- Refactor skb deferral free to better scale on large multi-NUMA
hosts, this improves TCP and UDP RX performances significantly on
such HW
- Increase the default socket memory buffer limits from 256K to 4M to
better fit modern link speeds
- Improve handling of setups with a large number of nexthop, making
dump operating scaling linearly and avoiding unneeded
synchronize_rcu() on delete
- Improve bridge handling of VLAN FDB, storing a single entry per
bridge instead of one entry per port; this makes the dump order of
magnitude faster on large switches
- Restore IP ID correctly for encapsulated packets at GSO
segmentation time, allowing GRO to merge packets in more scenarios
- Improve netfilter matching performance on large sets
- Improve MPTCP receive path performance by leveraging recently
introduced core infrastructure (skb deferral free) and adopting
recent TCP autotuning changes
- Allow bridges to redirect to a backup port when the bridge port is
administratively down
- Introduce MPTCP 'laminar' endpoint that con be used only once per
connection and simplify common MPTCP setups
- Add RCU safety to dst->dev, closing a lot of possible races
- A significant crypto library API for SCTP, MPTCP and IPv6 SR,
reducing code duplication
- Supports pulling data from an skb frag into the linear area of an
XDP buffer
Things we sprinkled into general kernel code:
- Generate netlink documentation from YAML using an integrated YAML
parser
Driver API:
- Support using IPv6 Flow Label in Rx hash computation and RSS queue
selection
- Introduce API for fetching the DMA device for a given queue,
allowing TCP zerocopy RX on more H/W setups
- Make XDP helpers compatible with unreadable memory, allowing more
easily building DevMem-enabled drivers with a unified XDP/skbs
datapath
- Add a new dedicated ethtool callback enabling drivers to provide
the number of RX rings directly, improving efficiency and clarity
in RX ring queries and RSS configuration
- Introduce a burst period for the health reporter, allowing better
handling of multiple errors due to the same root cause
- Support for DPLL phase offset exponential moving average,
controlling the average smoothing factor
Device drivers:
- Add a new Huawei driver for 3rd gen NIC (hinic3)
- Add a new SpacemiT driver for K1 ethernet MAC
- Add a generic abstraction for shared memory communication
devices (dibps)
- Ethernet high-speed NICs:
- nVidia/Mellanox:
- Use multiple per-queue doorbell, to avoid MMIO contention
issues
- support adjacent functions, allowing them to delegate their
SR-IOV VFs to sibling PFs
- support RSS for IPSec offload
- support exposing raw cycle counters in PTP and mlx5
- support for disabling host PFs.
- Intel (100G, ice, idpf):
- ice: support for SRIOV VFs over an Active-Active link
aggregate
- ice: support for firmware logging via debugfs
- ice: support for Earliest TxTime First (ETF) hardware offload
- idpf: support basic XDP functionalities and XSk
- Broadcom (bnxt):
- support Hyper-V VF ID
- dynamic SRIOV resource allocations for RoCE
- Meta (fbnic):
- support queue API, zero-copy Rx and Tx
- support basic XDP functionalities
- devlink health support for FW crashes and OTP mem corruptions
- expand hardware stats coverage to FEC, PHY, and Pause
- Wangxun:
- support ethtool coalesce options
- support for multiple RSS contexts
- Ethernet virtual:
- Macsec:
- replace custom netlink attribute checks with policy-level
checks
- Bonding:
- support aggregator selection based on port priority
- Microsoft vNIC:
- use page pool fragments for RX buffers instead of full pages
to improve memory efficiency
- Ethernet NICs consumer, and embedded:
- Qualcomm: support Ethernet function for IPQ9574 SoC
- Airoha: implement wlan offloading via NPU
- Freescale
- enetc: add NETC timer PTP driver and add PTP support
- fec: enable the Jumbo frame support for i.MX8QM
- Renesas (R-Car S4):
- support HW offloading for layer 2 switching
- support for RZ/{T2H, N2H} SoCs
- Cadence (macb): support TAPRIO traffic scheduling
- TI:
- support for Gigabit ICSS ethernet SoC (icssm-prueth)
- Synopsys (stmmac): a lot of cleanups
- Ethernet PHYs:
- Support 10g-qxgmi phy-mode for AQR412C, Felix DSA and Lynx PCS
driver
- Support bcm63268 GPHY power control
- Support for Micrel lan8842 PHY and PTP
- Support for Aquantia AQR412 and AQR115
- CAN:
- a large CAN-XL preparation work
- reorganize raw_sock and uniqframe struct to minimize memory
usage
- rcar_canfd: update the CAN-FD handling
- WiFi:
- extended Neighbor Awareness Networking (NAN) support
- S1G channel representation cleanup
- improve S1G support
- WiFi drivers:
- Intel (iwlwifi):
- major refactor and cleanup
- Broadcom (brcm80211):
- support for AP isolation
- RealTek (rtw88/89) rtw88/89:
- preparation work for RTL8922DE support
- MediaTek (mt76):
- HW restart improvements
- MLO support
- Qualcomm/Atheros (ath10k):
- GTK rekey fixes
- Bluetooth drivers:
- btusb: support for several new IDs for MT7925
- btintel: support for BlazarIW core
- btintel_pcie: support for _suspend() / _resume()
- btintel_pcie: support for Scorpious, Panther Lake-H484 IDs"
* tag 'net-next-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1536 commits)
net: stmmac: Add support for Allwinner A523 GMAC200
dt-bindings: net: sun8i-emac: Add A523 GMAC200 compatible
Revert "Documentation: net: add flow control guide and document ethtool API"
octeontx2-pf: fix bitmap leak
octeontx2-vf: fix bitmap leak
net/mlx5e: Use extack in set rxfh callback
net/mlx5e: Introduce mlx5e_rss_params for RSS configuration
net/mlx5e: Introduce mlx5e_rss_init_params
net/mlx5e: Remove unused mdev param from RSS indir init
net/mlx5: Improve QoS error messages with actual depth values
net/mlx5e: Prevent entering switchdev mode with inconsistent netns
net/mlx5: HWS, Generalize complex matchers
net/mlx5: Improve write-combining test reliability for ARM64 Grace CPUs
selftests/net: add tcp_port_share to .gitignore
Revert "net/mlx5e: Update and set Xon/Xoff upon MTU set"
net: add NUMA awareness to skb_attempt_defer_free()
net: use llist for sd->defer_list
net: make softnet_data.defer_count an atomic
selftests: drv-net: psp: add tests for destroying devices
selftests: drv-net: psp: add test for auto-adjusting TCP MSS
...
|
||
|
Linus Torvalds
|
0f048c878e |
soc: dt changes for 6.18
There are five sets of new SoCs that get added in existing families,
all of them being either upgrades or cut-down versions of the older chips:
- Apple M2 Pro, M2 Max and M2 Ultra, used in the 2022/2023 generation of
high-end workstations and laptops from Apple. Linux has been working
on these for a while but stil requires patches.
- Axis Artpec8 is an Armv8 chip based on Samsung Exynos design,
unlike the earlier Armv7 Artpec6 from the same company that
was part of a separate family of chips.
- NXP i.MX91 is a cut-down version of i.MX93, using only a single
Cortex-A55 core.
- Qualcomm Lemans Auto is a variant of the Lemans SoC that was
originally merged under the sa8775p name, the differences
being mostly the firmware configuration of the platform.
- Four new Renesas SoCs RZ/T2H (r9a09g077m44), RZ/N2H (r9a09g087m44),
RZ/T2H (r9a09g077), and RZ/N2H (r9a09g087) are all industrial bedded
SoCs based on Cortex-A55 cores
In total, there are 65 new machines, including:
- Industrial embedded system and single-board computers based on NXP,
Allwinner, TI, Rockchips, Marvell, Xilinx Spacemit, Starfive chips.
- Reference boards for the newly added Renesas, Qualcomm, NXP and Axis
ARMv8 chips as well as Microchip's MPFS RISC-V SoC
- Laptops and Workstations using Apple M2 and Qualcomm Snapdragon
X1 chips.
- Several Samsung phones using Qualcomm Snapdragon chips
- Set-top boxes based on Allwinner H313
- Five BMC boards using 32-bit ASpeed SoCs
- Three network routers using IXP4xx (ARMv5!) and Broadcom bcm4708
(ARMv7) SoCs
Two machines get phased out because they were available only in small
quantities but never made it into products: one STi407 based reference
board, and a Snapdragon 845 based Chromebook.
Aside from the newly added machines, a lot of work went into
improving hardware support on the existing machines and cleaning
up contents for validation.
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Merge tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC dt updates from Arnd Bergmann:
"There are five sets of new SoCs that get added in existing families,
all of them being either upgrades or cut-down versions of the older
chips:
- Apple M2 Pro, M2 Max and M2 Ultra, used in the 2022/2023 generation
of high-end workstations and laptops from Apple. Linux has been
working on these for a while but stil requires patches.
- Axis Artpec8 is an Armv8 chip based on Samsung Exynos design,
unlike the earlier Armv7 Artpec6 from the same company that was
part of a separate family of chips.
- NXP i.MX91 is a cut-down version of i.MX93, using only a single
Cortex-A55 core.
- Qualcomm Lemans Auto is a variant of the Lemans SoC that was
originally merged under the sa8775p name, the differences being
mostly the firmware configuration of the platform.
- Four new Renesas SoCs RZ/T2H (r9a09g077m44), RZ/N2H (r9a09g087m44),
RZ/T2H (r9a09g077), and RZ/N2H (r9a09g087) are all industrial
bedded SoCs based on Cortex-A55 cores
In total, there are 65 new machines, including:
- Industrial embedded system and single-board computers based on NXP,
Allwinner, TI, Rockchips, Marvell, Xilinx Spacemit, Starfive chips.
- Reference boards for the newly added Renesas, Qualcomm, NXP and
Axis ARMv8 chips as well as Microchip's MPFS RISC-V SoC
- Laptops and Workstations using Apple M2 and Qualcomm Snapdragon X1
chips.
- Several Samsung phones using Qualcomm Snapdragon chips
- Set-top boxes based on Allwinner H313
- Five BMC boards using 32-bit ASpeed SoCs
- Three network routers using IXP4xx (ARMv5!) and Broadcom bcm4708
(ARMv7) SoCs
Two machines get phased out because they were available only in small
quantities but never made it into products: one STi407 based reference
board, and a Snapdragon 845 based Chromebook.
Aside from the newly added machines, a lot of work went into improving
hardware support on the existing machines and cleaning up contents for
validation"
* tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (931 commits)
arm64: dts: apm-shadowcat: Drop "apm,xgene2-pcie" compatible
arm64: dts: apm-shadowcat: Move slimpro nodes out of "simple-bus" node
ARM: dts: microchip: sam9x7: Add qspi controller
arm64: dts: qcom: Add MST pixel streams for displayport
arm64: dts: qcom: sm6350: correct DP compatibility strings
arm64: dts: qcom: monaco-evk: Enable Adreno 623 GPU
arm64: dts: qcom: qcs8300-ride: Enable Adreno 623 GPU
arm64: dts: qcom: qcs8300: Add gpu and gmu nodes
arm64: dts: allwinner: h313: Add Amediatech X96Q
dt-bindings: arm: sunxi: Add Amediatech X96Q
arm64: dts: apple: t8015: Add SPMI node
arm64: dts: apple: t8012: Add SPMI node
arm64: dts: apple: Add J180d (Mac Pro, M2 Ultra, 2023) device tree
arm64: dts: rockchip: Add devicetree for the ROC-RK3588-RT
dt-bindings: arm: rockchip: Add Firefly ROC-RK3588-RT
arm64: dts: rockchip: update pinctrl names for Radxa E52C
arm64: dts: rockchip: remove vcc_3v3_pmu regulator for Radxa E52C
arm64: dts: apple: Add J474s, J475c and J475d device trees
arm64: dts: apple: Add J414 and J416 Macbook Pro device trees
arm64: dts: apple: Add initial t6020/t6021/t6022 DTs
...
|
||
|
Linus Torvalds
|
a8253f8077 |
soc: new SoC support for 6.18
Pinkesh Vaghela adds support for the ESWIN EIC7700 SoC, as described in [1]: "Add support for ESWIN EIC7700 SoC consisting of SiFive Quad-Core P550 CPU cluster and the first development board that uses it, the SiFive HiFive Premier P550. This patch series adds initial device tree and also adds ESWIN architecture support. Boot-tested using intiramfs with Linux v6.17-rc3 on HiFive Premier P550 board using U-Boot 2024.01 and OpenSBI 1.4." [1] https://lore.kernel.org/linux-riscv/20250825132427.1618089-1-pinkesh.vaghela@einfochips.com/ -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjdpqUACgkQmmx57+YA GNlh3g//QmkkOnHUZvbUNNhf3WMulaVFA7K8pX6DB+ZI8WJSY3asJsKKUfgx5EhO Dml85lMYI4RUtia6TkSQ9RgG7ECmrcn07RWEqUR5MNeAYh2+lcVHn6dEO6vSmllG yxXH1AcqRm1CP9nKnz8g5yRcrndfPVKGl8oIENlyfnGoBmrdPanKElXvx6krzexw J8h/BJo29TntCqUCDsw9/N+5xA9lUVHS7v7alF01M10w48nDaEg8l/X7QxUhxhKl Knd9o8abNzxt2au8AunS91rJhZCxm17Gnwsg3R3ij+Ws+Dgao3aWpYRVRIE2ND7m 6YhWIK+IeuMI48dnZ+QzKbNhwvF/RLUOt3P8zNGyRxDGh8azLUCp3BXtt8FSrJ2n /mSCrQyB2BnQHJs4cD6I2+shHWVpMJ9mf0lmQZBINamTkXFqIoIisGih/YDdX9x3 5BDG4D9mNFAP+qzLcrHq0WNGfHZHbhk06sw0YEv6AhgRgeKqRIjbWUn+8l7EnQts 8E8vZc+Ztd61hxLP3XD5Ads01kDz5nAU/7IJ6l+0r7qp+S6GxjKkaPXsvrdSscTn bACIgw5hsFr5t9rleyTcyS5XeqGwt778jA4mjC8PFLmXKqf0vpuCAOCSFjk7euea pMJjeyH6khA0VXCDvgolCF+O3STVY3RtqefEwJaOmBtQaycmNZ8= =DONh -----END PGP SIGNATURE----- Merge tag 'soc-newsoc-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull new SoC support from Arnd Bergmann: "Pinkesh Vaghela adds support for the ESWIN EIC7700 SoC consisting of SiFive Quad-Core P550 CPU cluster and the first development board that uses it, the SiFive HiFive Premier P550 [1]. This adds initial device tree and also adds ESWIN architecture support. Boot-tested using intiramfs with Linux v6.17-rc3 on HiFive Premier P550 board using U-Boot 2024.01 and OpenSBI 1.4" Link: https://lore.kernel.org/linux-riscv/20250825132427.1618089-1-pinkesh.vaghela@einfochips.com/ [1] * tag 'soc-newsoc-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: riscv: dts: eswin: add HiFive Premier P550 board device tree riscv: dts: add initial support for EIC7700 SoC dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC dt-bindings: riscv: Add SiFive HiFive Premier P550 board riscv: Add Kconfig option for ESWIN platforms dt-bindings: riscv: Add SiFive P550 CPU compatible |
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|
Linus Torvalds
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03a53e09cd |
Updates for interrupt chip drivers:
- Use the startup/shutdown callbacks for the PCI/MSI per device interrupt
domains.
This allows to initialize the RISCV PLIC interrupt hierarchy correctly
and provides a mechanism to decouple the masking and unmasking during
run-time from the expensive PCI mask and unmask when the underlying MSI
provider implementation allows the interrupt to be masked.
- Initialize the RISCV PLIC MSI interrupt hierarchy correctly so that the
affinity assignment works correctly by switching it over to the
startup/shutdown scheme
- Allow MSI providers to opt out from masking a PCI/MSI interrupt at the
PCI device during operation when the provider can mask the interrupt at
the underlying interrupt chip. This reduces the overhead in scenarios
where disable_irq()/enable_irq() is utilized frequently by a driver.
The PCI/MSI device level [un]masking is only required on startup and
shutdown in this case.
- Remove the conditional mask/unmask logic in the PCI/MSI layer as this
is now handled unconditionally.
- Replace the hardcoded interrupt routing in the Loongson EIOINTC
interrupt driver to respect the firmware settings and spread them out
to different CPU interrupt inputs so that the demultiplexing handler
only needs to read only a single 64-bit status register instead of
four, which significantly reduces the overhead in VMs as the status
register access causes a VM exit.
- Add support for the new AST2700 SCU interrupt controllers
- Use the legacy interrupt domain setup for the Loongson PCH-LPC
interrupt controller, which resembles the x86 legacy PIC setup and has
the same hardcoded legacy requirements.
- The usual set of cleanups, fixes and improvements all over the place
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Merge tag 'irq-drivers-2025-09-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq chip driver updates from Thomas Gleixner:
- Use the startup/shutdown callbacks for the PCI/MSI per device
interrupt domains.
This allows us to initialize the RISCV PLIC interrupt hierarchy
correctly and provides a mechanism to decouple the masking and
unmasking during run-time from the expensive PCI mask and unmask when
the underlying MSI provider implementation allows the interrupt to be
masked.
- Initialize the RISCV PLIC MSI interrupt hierarchy correctly so that
the affinity assignment works correctly by switching it over to the
startup/shutdown scheme
- Allow MSI providers to opt out from masking a PCI/MSI interrupt at
the PCI device during operation when the provider can mask the
interrupt at the underlying interrupt chip. This reduces the overhead
in scenarios where disable_irq()/enable_irq() is utilized frequently
by a driver.
The PCI/MSI device level [un]masking is only required on startup and
shutdown in this case.
- Remove the conditional mask/unmask logic in the PCI/MSI layer as this
is now handled unconditionally.
- Replace the hardcoded interrupt routing in the Loongson EIOINTC
interrupt driver to respect the firmware settings and spread them out
to different CPU interrupt inputs so that the demultiplexing handler
only needs to read only a single 64-bit status register instead of
four, which significantly reduces the overhead in VMs as the status
register access causes a VM exit.
- Add support for the new AST2700 SCU interrupt controllers
- Use the legacy interrupt domain setup for the Loongson PCH-LPC
interrupt controller, which resembles the x86 legacy PIC setup and
has the same hardcoded legacy requirements.
- The usual set of cleanups, fixes and improvements all over the place
* tag 'irq-drivers-2025-09-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits)
irqchip/loongson-pch-lpc: Use legacy domain for PCH-LPC IRQ controller
PCI/MSI: Remove the conditional parent [un]mask logic
irqchip/msi-lib: Honor the MSI_FLAG_PCI_MSI_MASK_PARENT flag
irqchip/aspeed-scu-ic: Add support for AST2700 SCU interrupt controllers
dt-bindings: interrupt-controller: aspeed: Add AST2700 SCU IC compatibles
dt-bindings: mfd: aspeed: Add AST2700 SCU compatibles
irqchip/aspeed-scu-ic: Refactor driver to support variant-based initialization
irqchip/gic-v5: Fix error handling in gicv5_its_irq_domain_alloc()
irqchip/gic-v5: Fix loop in gicv5_its_create_itt_two_level() cleanup path
irqchip/gic-v5: Delete a stray tab
irqchip/sg2042-msi: Set irq type according to DT configuration
riscv: sophgo: dts: sg2044: Change msi irq type to IRQ_TYPE_EDGE_RISING
riscv: sophgo: dts: sg2042: Change msi irq type to IRQ_TYPE_EDGE_RISING
irqchip/gic-v2m: Handle Multiple MSI base IRQ Alignment
irqchip/renesas-rzg2l: Remove dev_err_probe() if error is -ENOMEM
irqchip: Use int type to store negative error codes
irqchip/gic-v5: Remove the redundant ITS cache invalidation
PCI/MSI: Check MSI_FLAG_PCI_MSI_MASK_PARENT in cond_[startup|shutdown]_parent()
irqchip/loongson-eiointc: Add multiple interrupt pin routing support
irqchip/loongson-eiointc: Route interrupt parsed from bios table
...
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Jakub Kicinski
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203e3beb73 |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
Cross-merge networking fixes after downstream PR (net-6.17-rc8). Conflicts: drivers/net/can/spi/hi311x.c |
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Min Lin
|
fee2f45def |
riscv: dts: eswin: add HiFive Premier P550 board device tree
Add minimal device tree for HiFive Premier P550 Development board Currently the data populated in this DT file is for UART. Signed-off-by: Min Lin <linmin@eswincomputing.com> Co-developed-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com> Tested-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20250825132427.1618089-7-pinkesh.vaghela@einfochips.com Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Min Lin
|
3329e2f3b5 |
riscv: dts: add initial support for EIC7700 SoC
Add initial support for EIC7700 SoC that uses a SiFive Quad-Core P550 CPU cluster. This file is expected to grow as more device drivers are added to the kernel. Signed-off-by: Min Lin <linmin@eswincomputing.com> Co-developed-by: Pritesh Patel <pritesh.patel@einfochips.com> Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com> Co-developed-by: Darshan Prajapati <darshan.prajapati@einfochips.com> Signed-off-by: Darshan Prajapati <darshan.prajapati@einfochips.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com> Link: https://lore.kernel.org/r/20250825132427.1618089-6-pinkesh.vaghela@einfochips.com Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
|
8c0650e0ce |
RISC-V Misc Devicetrees for v6.18
Starfive: The main new addition is support for the JH7110 Milk-V Mars CM lite SoM. Other than that, there's several cleanups done to the common JH7110 dtsi file, some relating to properties used by U-Boot or encountered during U-Boot development. Additionally, there's a binding and devicetree node for the memory controller on the JH7110. The memory controller only sees use in U-Boot, so the binding is here rather than in Krzysztof's branch. SiFive: Support for SiFive vendor-specific extensions in the binding file for extensions. These currently only see use in the SBI implementation. Microchip: Addition of support for the PolarFire SoC Discovery kit and non-engineering sample Icicle kit. The latter differs very slightly from the final ES devices due to bug fixes affecting functionality, and needs its own dts. To reduce duplication, the common portion of the two Icicle kits are moved into a dtsi. There's a few minor fixes here too, mostly low-hanging fruit detected during the addition of the Discovery kit that were then applied to the Icicle. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCaNQsNwAKCRB4tDGHoIJi 0tRJAQCOiusij3bReKGIWj0IwCJqPWzopPM7SksV68FXFaM/dAD+OJIKn/WmLHjN luAnAUeUslgubmKuDNIQimrQm1OsSQ8= =V7Gc -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjUYZ4ACgkQmmx57+YA GNk2ABAAiA1kE871avv5q6kCo5ubiNl1yJFds/P++fu2pDDL+tEW5yUciYjTvWLi N8GXov77FkxDtvcfp+8XRtzZpcfutaIIcaC24dNFoGxoUONuqR8ZDZ1BH3Nd7M8M jro3iKWscj91hhtLWQK4HeW/7cDtVvW732Z+d+vfYsAecdIL7PPL/4aJ3LOm9+Lw icQjfhCoH9qiyih6GO6/aMJW9aFi7gB46j7ggInUUlIo8CEM+3V3of5jS7/wRMPM PZoES3N+w1tSqXYrVz+jr3ErEYmeYC0AvPgcV9/TcAgpgCjYbvTUlC+IL5EEupMW kOTkEjG1UsgmUwBskI/zH9xxlv5vjk6mRIWlHkQ24T/LwdVz4YDYfmRWcS8sVokf 3ZeOoPjnGZ+ANGz1rgbitcffydnDX/xJSMkGkCZFP/BjEXQtCXhNnXm9ECZ0lFuU NLn8leOnCB5VWrRm/ExSJIB6FTjm5OWwHIC2zs/9O+RvRVO54DTRwlaiqKybSE/E dV0GGgbvqtS3cMEzpiFh3zDCEZ1ivpTsIyuGj4wBW41/GdeXLTjNNEqPBtmtr8VX 4kAuLEK/DKEe6/JL/E0TQai0SPky2TtXfCCX9eALShu0uDAx21WFyjacnbRuIhXY V2UDs64/fkg3evp5rvSNDkFTsXj6NnvXFIrYLoAzOqzGVYHqf8g= =mB9N -----END PGP SIGNATURE----- Merge tag 'riscv-dt-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Misc Devicetrees for v6.18 Starfive: The main new addition is support for the JH7110 Milk-V Mars CM lite SoM. Other than that, there's several cleanups done to the common JH7110 dtsi file, some relating to properties used by U-Boot or encountered during U-Boot development. Additionally, there's a binding and devicetree node for the memory controller on the JH7110. The memory controller only sees use in U-Boot, so the binding is here rather than in Krzysztof's branch. SiFive: Support for SiFive vendor-specific extensions in the binding file for extensions. These currently only see use in the SBI implementation. Microchip: Addition of support for the PolarFire SoC Discovery kit and non-engineering sample Icicle kit. The latter differs very slightly from the final ES devices due to bug fixes affecting functionality, and needs its own dts. To reduce duplication, the common portion of the two Icicle kits are moved into a dtsi. There's a few minor fixes here too, mostly low-hanging fruit detected during the addition of the Discovery kit that were then applied to the Icicle. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: add Milk-V Mars CM Lite system-on-module dt-bindings: riscv: starfive: add milkv,marscm-lite riscv: dts: starfive: add Milk-V Mars CM system-on-module dt-bindings: riscv: starfive: add milkv,marscm-emmc riscv: dts: starfive: add common board dtsi for Milk-V Mars CM variants riscv: dts: microchip: add a device tree for Discovery Kit dt-bindings: riscv: microchip: document Discovery Kit riscv: dts: microchip: rename icicle kit ccc clock and other minor fixes riscv: dts: microchip: add icicle kit with production device dt-bindings: riscv: microchip: document icicle kit with production device riscv: dts: microchip: add common board dtsi for icicle kit variants riscv: dts: starfive: jh7110-common: drop mmc post-power-on-delay-ms riscv: dts: starfive: jh7110-common: drop no-mmc property from mmc1 riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader riscv: dts: starfive: jh7110: add DMC memory controller dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC riscv: dts: starfive: jh7110-common: drop no-sdio property from mmc1 riscv: dts: microchip: Minor whitespace cleanup dt-bindings: riscv: Add SiFive vendor extensions description Link: https://lore.kernel.org/r/20250924-frighten-magazine-ee2f16e64638@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
|
5eba504bb2 |
Allwinner fixes for 6.17
Two device tree style cleanups from the device tree maintainers. -----BEGIN PGP SIGNATURE----- iQJCBAABCgAsFiEE2nN1m/hhnkhOWjtHOJpUIZwPJDAFAmjK4l0OHHdlbnNAY3Np ZS5vcmcACgkQOJpUIZwPJDAdNxAAyr4rjXOMg5hNdhoAJYHoB8OtfzXBfPNk7gSH n5EIZqJsH4yUBHY/ULrCeePRXb9RczsrV6vSucRT2RnejUhMf8XXDHSY9GO5KJZV muhGpHGeijVDi1MgGdUKA3TOE7HFGMDHwHOhn0kxZFpUIl5uLzQGhhzH4yVg9RDU s6xqyeTAg3LQmSwS7wJIcT2W26+Ggj0KeqDb5II5UfWKgxcib9oo/WjzEGNpVOYr FqoDbboF/K9pHTaJGdUMJnKL6Fu647owc+uwL4UJFlS8jdKtQ10/bysdIZ41hvjr bZvfxTFz7UvnGeWbzulMs8nVl4ifPGsJEPpe17gZ9E111TpZqClJAHeJNt4ajKZ/ Wx8QOZr2qsfnEl34U9IixUUdfsdTvWWSRduJOet+kj9FCPBOPw9sX4eshOZVT3uV OcZeLlVgUTUI9QH2yWUDb0s9m4evSv+QZF2jAl6zADw7OCO2mkLOc1/2dhJFMc0X 88Q/wGiB1bD94Su5VNwAp6afcopMNYeXuZfRTTJ3mexOQ5S2akpiLDE41y+SQb9p uUcc4DDHlZZzKLe6wFMbbqSROUq/LqSPOBa8OGBOblgGZeVtIsyO6Kg7NFdJ30Ij +qvst6ny1wbohQf5D1F23DWCCDnIPFf0X+GAJ1JzR4eW2HPASYrE7refV9uds+hC s32yPxQ= =VlZ3 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjTA4EACgkQmmx57+YA GNng4g//Ug+NDzj217MjXMNogJkc/MZoJh7QJuW6YiH7++XykJ9RH4drbXvYDm/K dYP9u39j4ZUtrL8CJe1YxOOQxHXKG6IK69FMqRDiGQcWFBWsVZprAlEFRnMluM5J b/Pq78fFZhJjL9absM2oFkz0Se0a9MzIxvDJYKO+WeLqxKIwRBdaGzhEuiejmemC lupZbE/kh05gY1i8oGy5njbSjoFSVkftkNbRpYbUXErpclppFV53DEv393Zg7SSI EQuzeDY8NFC7KBGBvaJvSdOOeW9VRugVhWUvU+SEqeSQbdZc/LuQmYmfHS50W8np 7KQ/5znXQXr8JBUmh/GkxTTFYCiZdOA21r3/8hBiku0144ZBsw+x5sBOhUOW2eQg l+l+xZzDnP586mPJz/MbluiV5l4ibup060HN8Ws8zJfi4jUkOeKCMUDIUAC1UrJb xaQilNilTN/2UgeRFCztq3IOP/lLPRlA+gPy7Kozn3I3Zk5nhKd+MpBd1kIpv/WD Nteskf00YC1R656j+3Of7OywoTXeotmUm/R6Byihxf8qcU4Euo4bgTcLNfdknDvN gEi3yW1gj/rqO7ZxVhr9KIY/wMexwlXGZsanjFfgRZpepc+k+PJ4xkP1jVqYIIcN 0F953PgnJD8vfP66CI8HsArYTek7zEzkeu5meBE/WDg1ZFIlcuM= =pWOK -----END PGP SIGNATURE----- Merge tag 'sunxi-fixes-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/fixes Allwinner fixes for 6.17 Two device tree style cleanups from the device tree maintainers. * tag 'sunxi-fixes-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: riscv: dts: allwinner: rename devterm i2c-gpio node to comply with binding ARM: dts: allwinner: Minor whitespace cleanup Link: https://lore.kernel.org/r/aMrsUfkTWx8g3bJ7@wens.tw Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
|
ec1ede181e |
RISC-V SpacemiT DT changes for 6.18
- Add OrangePi RV2 board support - Add reset support to UART driver - Add PDMA driver support - Remove sec_uart1 node -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQKTBAABCgB9FiEEtbq4ycMbcRVnAiPcMarqR1lNu+0FAmjKrHBfFIAAAAAALgAo aXNzdWVyLWZwckBub3RhdGlvbnMub3BlbnBncC5maWZ0aGhvcnNlbWFuLm5ldEI1 QkFCOEM5QzMxQjcxMTU2NzAyMjNEQzMxQUFFQTQ3NTk0REJCRUQACgkQMarqR1lN u+0HzQ/+KGE0SIqzxIFwK77tfBePv/ViLND5DQtFMO+Cfno4aoWVBKID7M5zy7uu BQ7dPB6PzJkeBINClGw91yY2BnsnI6vZI65CIPxbr1IYDe/BNhHF4DujMYqwywtj N2tZJ9TbtW1gKW/9XmJW+pA5ODZoLz3hbH0Qi8IKDhiokmkDZBvTA0nogsZTf2TE pqeBB478WKv7dp7P5isDJl6e8NeeEIIgaPHeLKpYvgs2r+ptWERJq6yBmNnGWYot DnZQkUbMZAyW1aZMk8ZFih39rVfiUnnafAfBsRTj5fb4/2gYa5hXJHvZ05sSlFDQ 8f/Uh+94EIC+rQ/EMuyZLUhwczHuFN5JejwSNi1b9EnhWY0YLX1EI9gR4HQHTNDD nFSon+XjEZtRzLPWtxNlX2lFC2rAjAkTDFSQbCaSuSzUpRbzj05xwopOldKvwAx7 Xt0D4QPgLe2NU/eWBznklI4D6AJ5yXPwT9LWoeRoFZ0spzwHBH6Jt13xP9WojUEw YGHKBFkp4gLTeMWBuNSVknsHsQIqQUqZCDNsgDPTnlMZKXxN8pnS0nlasg3OM7DI C6bnyJYdYoHX3gwBomDydgITS2bxYmZGaNESpIYZWIBKntrqSSV3zkKXxuRdBngh 0n0uYodFLNGS6aVJjG2R6h89bWrXLR+2qzjksY25us7ezqLvStg= =kXs0 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjTAYAACgkQmmx57+YA GNk7Pg//UaWjxgecvuKXynpmho/KDR+QtMOOmVAEhhnxWBcPZDA1WOMzw5ikbKat aGGW/+d81XYr64G9jGJRNl1LmsvMfNv8V0+UVzGG+IXPi+oJutOaRr+67oZvapSL QqmlnZcr+UN8KRdFecuHtlOIq3VXEmUyKxc4spwxg0E8TfOJM6ND/Zps86GxSyVO u4qvlDd5BmgL4gJzoZJHFl15Bgg7qIm3pCQJIECgn1n1BMJJSMqOBcKwftCAhglT NrGGtHwL+8Xjh8frv+cjch/N7SC2DX00NIdHYojzfVKzOvwSitXBWYeuXO4FUrnc YOPz7/yky2/9QzrlPV2d/LqdgL89CzdxLKhM5z6g9q/NCg1Ftz7O3efStKsabcHB AF6UfDqoE9Y/zf24gzBGnKDFHvuvF084yfP8NB8b14KYaOGZlSFtiTkBDuQnCuGP ckFAeLVHsQ/PCzp0LdOXWEP0BUXZ/8p+leFZvXqJnhcfDRiS17J0cE9IiZOEXB1r N759GC9Wy0yCOOzne5psXEl/FisFOIjWBxtLTE9hK4uXAYumef6yqnh5zaLZAZ7T 5RLBX3GKKec11lb/TzEfj6Lz3YyctBbytCnxIu8WFo4OiqVNNLSCoW2IMBfW1Pgd f/O1tyUCH1X1h5tTUfsxZVtSVqG+zw7zdUz9st4GxSLolDBMxF4= =XxMz -----END PGP SIGNATURE----- Merge tag 'spacemit-dt-for-6.18-1' of https://github.com/spacemit-com/linux into soc/dt RISC-V SpacemiT DT changes for 6.18 - Add OrangePi RV2 board support - Add reset support to UART driver - Add PDMA driver support - Remove sec_uart1 node * tag 'spacemit-dt-for-6.18-1' of https://github.com/spacemit-com/linux: riscv: dts: spacemit: uart: remove sec_uart1 device node riscv: dts: spacemit: Enable PDMA on Banana Pi F3 and Milkv Jupiter riscv: dts: spacemit: Add PDMA node for K1 SoC riscv: dts: spacemit: add UART resets for Soc K1 riscv: dts: spacemit: Add OrangePi RV2 board device tree dt-bindings: riscv: spacemit: Add OrangePi RV2 board Link: https://lore.kernel.org/r/20250919055525-GYC5766558@gentoo.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
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17752efeca |
Allwinner Device Tree changes for 6.18
This tag contains two DT binding header changes that are shared with the clk tree. In this cycle we gained support for the MCU PRCM clock and reset controller on the A523/A527/T527 family of SoCs, the NPU which is a Vivante GC9000 IP block, and the NPU clock that was missing. The other PRCM clock controller gained default bus clock rate settings. These were not configured in the upstream U-boot bootloader, leading to them running at slower rates. The assigned rates are from the user manual. There is also a new board, the NetCube Systems Nagami SoM and two of its carrier boards. The A523 family development boards now have their internal RTC clocks configured correctly, so that the RTC does not drift wildly. The missing functions for the AXP717 on these boards are added. Missing reset GPIOs and delays for Ethernet PHYs are added. Last, the Cubie A5E now has its LEDs described and usable. An overlay for the Orange Pi Zero interface (addon) board was added. This can be used with the Orange Pi Zero and Zero Plus 2. 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In this cycle we gained support for the MCU PRCM clock and reset controller on the A523/A527/T527 family of SoCs, the NPU which is a Vivante GC9000 IP block, and the NPU clock that was missing. The other PRCM clock controller gained default bus clock rate settings. These were not configured in the upstream U-boot bootloader, leading to them running at slower rates. The assigned rates are from the user manual. There is also a new board, the NetCube Systems Nagami SoM and two of its carrier boards. The A523 family development boards now have their internal RTC clocks configured correctly, so that the RTC does not drift wildly. The missing functions for the AXP717 on these boards are added. Missing reset GPIOs and delays for Ethernet PHYs are added. Last, the Cubie A5E now has its LEDs described and usable. An overlay for the Orange Pi Zero interface (addon) board was added. This can be used with the Orange Pi Zero and Zero Plus 2. Default audio routing for these two boards (to be used with the addon) were added to complement the overlay. * tag 'sunxi-dt-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm64: dts: allwinner: sun55i: Complete AXP717A sub-functions arm64: dts: allwinner: t527: orangepi-4a: hook up external 32k crystal arm64: dts: allwinner: t527: avaota-a1: hook up external 32k crystal arm64: dts: allwinner: a527: cubie-a5e: Drop external 32.768 KHz crystal arm64: dts: sun55i: a523: Assign standard clock rates to PRCM bus clocks ARM: dts: sunxi: add support for NetCube Systems Nagami Keypad Carrier ARM: dts: sunxi: add support for NetCube Systems Nagami Basic Carrier ARM: dts: sunxi: add support for NetCube Systems Nagami SoM riscv: dts: allwinner: d1s-t113: Add pinctrl's required by NetCube Systems Nagami SoM dt-bindings: arm: sunxi: Add NetCube Systems Nagami SoM and carrier board bindings ARM: dts: allwinner: Add Orange Pi Zero Interface Board overlay ARM: dts: allwinner: orangepi-zero-plus2: Add default audio routing ARM: dts: allwinner: orangepi-zero: Add default audio routing arm64: dts: allwinner: a523: Add NPU device node arm64: dts: allwinner: a523: Add MCU PRCM CCU node dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clock arm64: dts: allwinner: t527: avaota-a1: Add ethernet PHY reset setting arm64: dts: allwinner: a527: cubie-a5e: Add ethernet PHY reset setting arm64: dts: allwinner: a527: cubie-a5e: Add LEDs Link: https://lore.kernel.org/r/aMrtuZg8HlR--TAt@wens.tw Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Arnd Bergmann
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0651061855 |
RISC-V Devicetrees for v6.18
Sophgo: Minor changes here only for SG2042. Enable numa and we can see significant performance improvements, for example in the STREAM test. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> -----BEGIN PGP SIGNATURE----- iQGzBAABCgAdFiEEdoBX2jyDC9ZCTwZjDCzASqG0i0IFAmjKa6YACgkQDCzASqG0 i0JqeQwAgknIaAet2WndrfaHmjfF3l6utvI/bJS+irq2rrzBpIsVcDmmejhqmawd 7Kd2zvsCpYzmyCUKWgx0fyj4mVBvgJcUeYb+Cd92qPeuXw0TVKzBPausFZALHIz6 HIQMe8W18oWBps+wbucIpEDbM5/cNB49gC8fNXB0OrwVAAfJuuORPqkbZMUGwPbg 1XAjEUQW/PMPol/kiYOCcv3AaUjlFJxSy5wX3endc+2T/f5eNIU46JI/GH51DpLy UsJJlDq1mneuqL3Nsb//KTh5LpECmQAcxJnbqXz2myk0EKI84LYIJHet3V+zoeme eHxqszSSl69W/Bu8GSdW/ZR4ABNpibocv71PMg4PesUclWQgru06GG2up+wE3RPv xbSrTm/7f7W7ZG6p1jZ4sRWLX0gwOOXGEasW5xYkXbijY2TjC5Ai22RINidDYnvb XXPQcVEidIzh7zkVfJ39N+5WfuN9oLnLC7mz6RMqVcYa+Rim+SPEd/vAwuIe0f4M BVRpZ8qj =4hzm -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjS/9QACgkQmmx57+YA GNmGbhAAmezDnPUHibicM55+7lZss+lftZ7gfE5dwp4ty+9q+zHmm7NfUwfsEeSV OJUCky26UTPQV0xqyxGguxaio9IJDa4vTu+doB09LQxIu44QvmpPAA8Cc86MRTbh js84bSfg2ljGTIY7I9JeB3ko0Ftr4sUvd79O0Cqux076UX56c0t2BBkkbLvLor99 KkCVZgpv2nDaIVfVPhugZFNaqacoLPlX8Gze2GO5hCKKwM3nkfEtv9aXjgHLjqCY HXwvQCqKwNytKNPZugCesAZXIwb/g+9xDDK5rrprMB3f/nT+7wTk+IEbENIEVx5N TnIZtR+X1Trrl7GMjMng9uYjlYrNgjQxrVxqz1PwimKZtKHXhX4rLe/tz/IxDQaT IBCwebacLxqYOx9fmeUQ1hVMZsI9CSY9CTbYJySwhLvzWsOF/oLc9Gi8VHUyagwf qQFNyj4YBaJB5Fmlup13dTBpqeiZEOAFFDIYfyXB/TS8SjcszSTMk4Tk03I8PMXc hEqP85RMqETGQmeAJw8teaxPTxUQh9ebkmlQfLxutdNYgn83a8Ikz6PmkFFNMwOA KfDCvwChE7iTwgysQYNIeYQyRh1SAfwrfc5QYGXdCsFkCEU88rCP06dX50xdIBKx ZnMxbRZqnKzTY5z58qcl7ZPSP+IR8rv83eiK0P75BiV0lJqKkjE= =RXxa -----END PGP SIGNATURE----- Merge tag 'riscv-sophgo-dt-for-v6.18' of https://github.com/sophgo/linux into soc/dt RISC-V Devicetrees for v6.18 Sophgo: Minor changes here only for SG2042. Enable numa and we can see significant performance improvements, for example in the STREAM test. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * tag 'riscv-sophgo-dt-for-v6.18' of https://github.com/sophgo/linux: dts: sophgo: sg2042: added numa id description Link: https://lore.kernel.org/r/MAUPR01MB11072ABA02A18CC7AA9B88874FE17A@MAUPR01MB11072.INDPRD01.PROD.OUTLOOK.COM Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Han Gao
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4d94abded4 |
dts: sophgo: sg2042: added numa id description
According to the description of [1], sg2042 is divided into 4 numa. STREAM test performance will improve. Before: Function Best Rate MB/s Avg time Min time Max time Copy: 10739.7 0.015687 0.014898 0.016385 Scale: 10865.9 0.015628 0.014725 0.016757 Add: 10622.3 0.023276 0.022594 0.023899 Triad: 10583.4 0.023653 0.022677 0.024761 After: Function Best Rate MB/s Avg time Min time Max time Copy: 34254.9 0.005142 0.004671 0.005995 Scale: 37735.5 0.004752 0.004240 0.005407 Add: 44206.8 0.005983 0.005429 0.006461 Triad: 43040.6 0.006320 0.005576 0.006996 [1] https://github.com/sophgo/sophgo-doc/blob/main/SG2042/TRM/source/pic/mesh.png Signed-off-by: Han Gao <rabenda.cn@gmail.com> Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/20250910105531.519897-1-rabenda.cn@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn> |
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E Shattow
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4cce8b2503 |
riscv: dts: starfive: add Milk-V Mars CM Lite system-on-module
Milk-V Mars CM Lite is a System-on-Module based on the Milk-V Mars CM without the onboard eMMC storage component populated and configured instead for SD3.0 Card Slot on that interface via 100-pin connector. Link to Milk-V Mars CM Lite schematics: https://github.com/milkv-mars/mars-files/tree/main/Mars-CM_Hardware_Schematices Link to StarFive JH7110 Technical Reference Manual: https://doc-en.rvspace.org/JH7110/TRM/index.html Link to Raspberry Pi CM4IO datasheet: https://datasheets.raspberrypi.com/cm4io/cm4io-datasheet.pdf Add the devicetree file to make use of StarFive JH7110 common supported features PMIC, EEPROM, UART, I2C, GPIO, PCIe, QSPI Flash, PWM, and Ethernet. Also configure the eMMC interface mmc0 for SD Card use and configure the common SD Card interface mmc1 for onboard SDIO BT+WiFi. Signed-off-by: E Shattow <e@freeshell.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
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E Shattow
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8d193bc0aa |
riscv: dts: starfive: add Milk-V Mars CM system-on-module
Milk-V Mars CM is a System-on-Module based on the StarFive VisionFive 2 board and Radxa CM3 System-on-Module compatible with the Raspberry Pi CM4IO Classic IO Board. Mars CM SoM features: - StarFive JH7110 System on Chip with RV64GC up to 1.5GHz - AXP15060 Power Management Unit - LPDDR4 2GB / 4GB / 8GB DRAM memory - BL24C04F 4K bits (512 x 8) EEPROM - GigaDevice 25LQ128EWIG QSPI NOR Flash 16M or SoC ROM UART loader for boot (selectable by GPIO) - eMMC5.0 8GB / 16GB / 32GB flash storage onboard - AP6256 via SDIO 2.0 onboard wireless connectivity WiFi 5 + Bluetooth 5.2 (optional, present in models with WiFi feature) - 1x Motorcomm YT8531C Gigabit Ethernet PHY - IMG BXE-4-32 Integrated GPU with 3D Acceleration: - H.264 & H.265 4K@60fps Decoding - H.265 1080p@30fps Encoding - JPEG encoder / decoder Additional features available via 2x 100-pin connectors for CM4IO Board: - 1x HDMI 2.0 - 1x MIPI DSI (4-lanes) - 1x 2CH Audio out (via GPIO) - 1x MIPI CSI (2x2-lanes or 1x4-lanes) - 1x USB 2.0 - 1x PCIe 1-lane Host, Gen 2 (5Gbps) - Up to 28x GPIO, supporting 3.3V - UART x6 - PWM x8 - I2C x7 - SPI - I2S Link to Milk-V Mars CM schematics: https://github.com/milkv-mars/mars-files/tree/main/Mars-CM_Hardware_Schematices Link to StarFive JH7110 Technical Reference Manual: https://doc-en.rvspace.org/JH7110/TRM/index.html Link to Raspberry Pi CM4IO datasheet: https://datasheets.raspberrypi.com/cm4io/cm4io-datasheet.pdf Add the devicetree file to make use of StarFive JH7110 common supported features PMIC, EEPROM, UART, I2C, GPIO, eMMC, PCIe, QSPI Flash, PWM, and Ethernet. Also configure the common SD Card interface mmc1 for onboard SDIO BT+WiFi. Signed-off-by: E Shattow <e@freeshell.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
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E Shattow
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651b30c587 |
riscv: dts: starfive: add common board dtsi for Milk-V Mars CM variants
Add a common board dtsi for use by Milk-V Mars CM and Milk-V Mars CM Lite. Signed-off-by: E Shattow <e@freeshell.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
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Vivian Wang
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e32dc7a936 |
riscv: dts: spacemit: Add Ethernet support for Jupiter
Milk-V Jupiter uses an RGMII PHY for each port and uses GPIO for PHY reset. Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn> Reviewed-by: Yixun Lan <dlan@gentoo.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20250914-net-k1-emac-v12-5-65b31b398f44@iscas.ac.cn Signed-off-by: Paolo Abeni <pabeni@redhat.com> |
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Vivian Wang
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3c247a6366 |
riscv: dts: spacemit: Add Ethernet support for BPI-F3
Banana Pi BPI-F3 uses an RGMII PHY for each port and uses GPIO for PHY reset. Tested-by: Hendrik Hamerlinck <hendrik.hamerlinck@hammernet.be> Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn> Reviewed-by: Yixun Lan <dlan@gentoo.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20250914-net-k1-emac-v12-4-65b31b398f44@iscas.ac.cn Signed-off-by: Paolo Abeni <pabeni@redhat.com> |
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Vivian Wang
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60775f28cf |
riscv: dts: spacemit: Add Ethernet support for K1
Add nodes for each of the two Ethernet MACs on K1 with generic properties. Also add "gmac" pins to pinctrl config. Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://patch.msgid.link/20250914-net-k1-emac-v12-3-65b31b398f44@iscas.ac.cn Signed-off-by: Paolo Abeni <pabeni@redhat.com> |
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Arnd Bergmann
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48c7bf3ebd |
T-HEAD Devicetrees for v6.18
Add a device tree node for the IMG BXM-4-64 GPU present in the T-HEAD TH1520 SoC used by the Lichee Pi 4A board. This node enables support for the GPU using the drm/imagination driver. By adding this node, the kernel can recognize and initialize the GPU, providing graphics acceleration capabilities on the Lichee Pi 4A and other boards based on the TH1520 SoC. The display controller and HDMI output are still a work in progress. Also included is a MAINTAINERS patch that adds an entry for the T-Head SoC patchwork. Signed-off-by: Drew Fustini <fustini@kernel.org> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQSy8G7QpEpV9aCf6Lbb7CzD2SixDAUCaLx9VAAKCRDb7CzD2Six DHXtAQCxK0kmJWID+40PSrvAnK6TO0nDPmS5IP1ZCP4cNp3RQAD/ePNIwaBDGiP1 8uyujrLGrp1t4B4jKPDUgpdDr9ZYxQE= =FKml -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjIDA4ACgkQmmx57+YA GNk2rxAAngIWvzhGLd3AW/ejkLLO2yurZJnbwNfCaLpJpGWFRRIorlL0L/yfoC0m Q2zUxFZ0+m/ZorVY+P/QntzUSfFOCYoo8sEkZiQGFq1un5dOVVXbpRecXbWKVUmf Qq24Uic7kVtLLTyBaH0pZe/WySRiJL8LYi0V57dVbeKhDKkm0eVjK6UnJwUOK57f q/H3/xS+COudss0Yt10Uc3hFlL/A77vV6fBqlXZZqlG6gXbhuNaeOx2yd3sNQh0z zP5laN8kbIopPYA+HzCzpcPLbUoa/cQGPe74FHBHe+keUknvoq9G+9UCDndGeNSp JDb1nE83vg1vBHBBERTDHjOCwXKFUvGbv4cx9otQV3xMQ9ypkkL/Bimf5DtFjydJ FNzzhxSukD6MyohjiBWeVMCR2gpxR/+K/DZFVRba789pEf0ypCzsP9gI1tk0aPuc RuqsqcENCCu4ClWqXyDjfekWdVGQgo3YV3VZChSM4izIH5iSxGFGi6/ylotueHMA 7E3Wza046jd8FrrMpdP6SjNBVQToLl0BZ1FaYq9PeD1US+wMesQYXk9+m0ZSa2gs dN/S7uJJk8j2AycoRVT1QddR3boaWABOJCO7+L/RBrBaPqlNcO0qHhwWDl5AxRv/ 5XXSf59Rhzsw6X/K4huDpo73mkWMfEtrmWvKjryU86tfmwahUhc= =NobZ -----END PGP SIGNATURE----- Merge tag 'thead-dt-for-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into soc/dt T-HEAD Devicetrees for v6.18 Add a device tree node for the IMG BXM-4-64 GPU present in the T-HEAD TH1520 SoC used by the Lichee Pi 4A board. This node enables support for the GPU using the drm/imagination driver. By adding this node, the kernel can recognize and initialize the GPU, providing graphics acceleration capabilities on the Lichee Pi 4A and other boards based on the TH1520 SoC. The display controller and HDMI output are still a work in progress. Also included is a MAINTAINERS patch that adds an entry for the T-Head SoC patchwork. Signed-off-by: Drew Fustini <fustini@kernel.org> * tag 'thead-dt-for-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux: MAINTAINERS: Add RISC-V T-HEAD SoC patchwork riscv: dts: thead: th1520: Add IMG BXM-4-64 GPU node Link: https://lore.kernel.org/r/aLyIXR1G9DUzwGWc@x1 Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
Lukas Schmid
|
cbce6d5326 |
riscv: dts: allwinner: d1s-t113: Add pinctrl's required by NetCube Systems Nagami SoM
Added the following pinctrl's used by the NetCube Systems Nagami SoM * i2c2_pins * i2c3_pins * i2s1_pins, i2s1_din_pins, i2s1_dout_pins * spi1_pins, spi1_hold_pin, spi1_wp_pin Signed-off-by: Lukas Schmid <lukas.schmid@netcube.li> Link: https://patch.msgid.link/20250831162536.2380589-3-lukas.schmid@netcube.li [wens@csie.org: Fix up node names and labels for i2c* and i2s1_d* pins] Signed-off-by: Chen-Yu Tsai <wens@csie.org> |
||
Conor Dooley
|
a5d7a8ab4b |
riscv: dts: allwinner: rename devterm i2c-gpio node to comply with binding
The i2c controller binding does not permit permit the node name to
contain "gpio", resulting in two warnings:
i2c-gpio-0 (i2c-gpio): $nodename:0: 'i2c-gpio-0' does not match '^i2c(@.+|-[a-z0-9]+)?$'
i2c-gpio-0 (i2c-gpio): Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'adc@54' were unexpected)
Drop it to satisfy dtbs_check.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20250909-frown-wrinkle-f16df243a970@spud
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
|
||
Valentina Fernandez
|
acc211539c |
riscv: dts: microchip: add a device tree for Discovery Kit
Add a minimal device tree for the Microchip PolarFire SoC Discovery Kit. The Discovery Kit is a cost-optimized board based on PolarFire SoC MPFS095T and features: - 1 GB DDR4x16 - 1x Gigabit Ethernet - 3x UARTs - Raspberry Pi connector - mikroBus connector - microSD card connector Link: https://www.microchip.com/en-us/development-tool/mpfs-disco-kit Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
|
Valentina Fernandez
|
02428682b2 |
riscv: dts: microchip: rename icicle kit ccc clock and other minor fixes
Rename the Clock Conditioning Circuit (CCC) reference clock to match the fixed clock bindings naming recommendation. Update the reserved memory regions in the Icicle Kit common dtsi to use lowercase hex and drop the redundant status properties from the memory regions, as they are not required. Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
|
Valentina Fernandez
|
2775e87c34 |
riscv: dts: microchip: add icicle kit with production device
With the introduction of the Icicle Kit using the production MPFS250T device, it's necessary to distinguish it from the engineering sample (-es) variant. Engineering samples cannot write to flash from the MSS, as noted in the PolarFire SoC FPGA ES errata. Add a new device tree (mpfs-icicle-kit-prod.dts) for the production board which includes the icicle kit common dtsi and enable the system controller SPI flash, which is only accessible on production silicon. Remove redundant board compatible from fabric dtsi and update board compatibles for v2025.07 release, which includes Mi-V IHC v2 for AMP cluster communication. Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
|
Valentina Fernandez
|
f401a8ba75 |
riscv: dts: microchip: add common board dtsi for icicle kit variants
In preparation for supporting the Icicle Kit with production silicon, add a common board dtsi for the icicle kit with hardware shared by both the engineering sample and production versions. Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
|
E Shattow
|
b5a861a438 |
riscv: dts: starfive: jh7110-common: drop mmc post-power-on-delay-ms
Drop post-power-on-delay-ms from mmc0 mmc1 interfaces. There is no known reason for these properties to continue, testing appears to be fine without them [1]. 1: https://lore.kernel.org/lkml/NT0PR01MB1312E0D9EE9F158A57B77700E63D2@NT0PR01MB1312.CHNPR01.prod.partner.outlook.cn/ Signed-off-by: E Shattow <e@freeshell.de> Tested-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
|
E Shattow
|
08128670a9 |
riscv: dts: starfive: jh7110-common: drop no-mmc property from mmc1
Relax no-mmc restriction on mmc1 for jh7110 boards. The restriction is only needed to block use of commands that would cause a device to malfunction, which by testing and observation [1] is not any problem. 1: https://lore.kernel.org/lkml/NT0PR01MB1312E0D9EE9F158A57B77700E63D2@NT0PR01MB1312.CHNPR01.prod.partner.outlook.cn/ Signed-off-by: E Shattow <e@freeshell.de> Tested-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
|
E Shattow
|
8181cc2f3f |
riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader
Add bootph-pre-ram hinting to jh7110.dtsi: - CPU interrupt controller(s) - gmac1_rgmii_rxin fixed-clock (dependency of syscrg) - gmac1_rmii_refin fixed-clock (dependency of syscrg) - oscillator - core local interrupt timer - syscrg clock-controller - pllclk clock-controller (dependency of syscrg) - DDR memory controller Signed-off-by: E Shattow <e@freeshell.de> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
|
E Shattow
|
7114969021 |
riscv: dts: starfive: jh7110: add DMC memory controller
Add JH7110 SoC DDR external memory controller. Signed-off-by: E Shattow <e@freeshell.de> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
Chen Wang
|
8aefd27244 |
riscv: sophgo: dts: sg2044: Change msi irq type to IRQ_TYPE_EDGE_RISING
Fix msi irq type to be the correct type, although this field is not used yet. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Inochi Amaoto <inochiama@gmail.com> # Sophgo SRD3-10 Link: https://lore.kernel.org/all/c38b9b1682af978473705b7e70b6faaa36fe5024.1756953919.git.unicorn_wang@outlook.com |
||
|
Chen Wang
|
a4bd4c330d |
riscv: sophgo: dts: sg2042: Change msi irq type to IRQ_TYPE_EDGE_RISING
Fix msi irq type to be the correct type, although this field is not used yet. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/831c1b650c575380d56ef3e2faed9bee278c9006.1756953919.git.unicorn_wang@outlook.com |
||
Yixun Lan
|
0f084b221e |
riscv: dts: spacemit: uart: remove sec_uart1 device node
sec_uart1 is not available from Linux, and no clock is implemented in CCF framework, thus 'make dtbs_check' will pop up this warning message: serial@f0612000: 'clock-names' is a required property Removing the node from device tree to silence the DT check warning. Link: https://lore.kernel.org/r/20250902-02-k1-uart-clock-v2-1-f146918d44f6@gentoo.org Signed-off-by: Yixun Lan <dlan@gentoo.org> |
||
Guodong Xu
|
0e28eab0ca |
riscv: dts: spacemit: Enable PDMA on Banana Pi F3 and Milkv Jupiter
Enable the PDMA on the SpacemiT K1-based Banana Pi F3 and Milkv Jupiter boards by setting its status to "okay". Signed-off-by: Guodong Xu <guodong@riscstar.com> Link: https://lore.kernel.org/r/20250822-working_dma_0701_v2-v5-7-f5c0eda734cc@riscstar.com Signed-off-by: Yixun Lan <dlan@gentoo.org> |
||
|
Guodong Xu
|
81d79ad0dd |
riscv: dts: spacemit: Add PDMA node for K1 SoC
Add PDMA dma-controller node under dma_bus for SpacemiT K1 SoC. The PDMA node is marked as disabled by default, allowing board-specific device trees to enable it as needed. Signed-off-by: Guodong Xu <guodong@riscstar.com> Reviewed-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Link: https://lore.kernel.org/r/20250822-working_dma_0701_v2-v5-6-f5c0eda734cc@riscstar.com Signed-off-by: Yixun Lan <dlan@gentoo.org> |
||
Michal Wilczynski
|
5052d5cf13 |
riscv: dts: thead: th1520: Add IMG BXM-4-64 GPU node
Add a device tree node for the IMG BXM-4-64 GPU present in the T-HEAD TH1520 SoC used by the Lichee Pi 4A board. This node enables support for the GPU using the drm/imagination driver. By adding this node, the kernel can recognize and initialize the GPU, providing graphics acceleration capabilities on the Lichee Pi 4A and other boards based on the TH1520 SoC. Add fixed clock gpu_mem_clk, as the MEM clock on the T-HEAD SoC can't be controlled programatically. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Drew Fustini <fustini@kernel.org> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Matt Coster <matt.coster@imgtec.com> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com> Signed-off-by: Drew Fustini <fustini@kernel.org> |
||
Hendrik Hamerlinck
|
eba84c94f9 |
riscv: dts: spacemit: add UART resets for Soc K1
The UARTs in the SpacemiT K1 device tree are probed by the 8250_of driver, but without reset lines they remain non-functional. Add reset control entries so that the UARTs can operate when mapped to devices. UART0 is already de-asserted by the bootloader, but include its reset as well to avoid relying on bootloader state. Tested on Orange Pi RV2 and Banana Pi BPI-F3 boards, with UART9 enabled and verified functional. Signed-off-by: Hendrik Hamerlinck <hendrik.hamerlinck@hammernet.be> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20250821152619.597051-1-hendrik.hamerlinck@hammernet.be Signed-off-by: Yixun Lan <dlan@gentoo.org> |
||
|
E Shattow
|
481ee0fcbb |
riscv: dts: starfive: jh7110-common: drop no-sdio property from mmc1
Relax no-sdio restriction on mmc1 for jh7110 boards. Property was introduced for StarFive VisionFive2 dts to configure mmc1 for SD Card but this is not necessary, the restriction is only needed to block use of commands that would cause a device to malfunction. Signed-off-by: E Shattow <e@freeshell.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
Krzysztof Kozlowski
|
cec6e40a02 |
riscv: dts: microchip: Minor whitespace cleanup
The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> |
||
|
Hendrik Hamerlinck
|
bab8dea259 |
riscv: dts: spacemit: Add OrangePi RV2 board device tree
Add initial device tree support for the OrangePi RV2 board [1]. The board is described as using the Ky X1 SoC, which, based on available downstream sources and testing, appears to be identical or very closely related to the SpacemiT K1 SoC [2]. The device tree is adapted from the OrangePi vendor tree [3], and similar integration can be found in the Banana Pi kernel tree [4], confirming SoC compatibility. The main difference with the current Banana Pi BPI-F3 tree is that status led is using GPIO_ACTIVE_LOW. This minimal device tree enables booting into a serial console with UART output and a blinking LED. Link: http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-RV2.html [1] Link: https://www.spacemit.com/en/key-stone-k1 [2] Link: https://github.com/BPI-SINOVOIP/pi-linux/blob/linux-6.6.63-k1/arch/riscv/boot/dts/spacemit/k1-x_orangepi-rv2.dts [3] Link: https://github.com/orangepi-xunlong/linux-orangepi/tree/orange-pi-6.6-ky [4] Signed-off-by: Hendrik Hamerlinck <hendrik.hamerlinck@hammernet.be> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20250813092240.180333-3-hendrik.hamerlinck@hammernet.be Signed-off-by: Yixun Lan <dlan@gentoo.org> |
||
Yao Zi
|
a7f75e2883 |
riscv: dts: thead: Add APB clocks for TH1520 GMACs
Describe perisys-apb4-hclk as the APB clock for TH1520 SoC, which is
essential for accessing GMAC glue registers.
Fixes:
|
||
|
Linus Torvalds
|
4df9c0a246 |
soc: new SoC support for 6.17
These five newly supported chips come with both devicetree descriptions
and the changes to wire them up to the build system for easier bisection.
The chips in question are:
- Marvell PXA1908 was the first 64-bit mobile phone chip from Marvell
in the product line that started with the Digital StrongARM SA1100
based PDAs and continued with the Intel PXA2xx that dominated early
smartphones. This one only made it only into a few products before the
entire product line was cut in 2015.
- The QiLai SoC is made by RISC-V core designer Andes Technologies
and is in the 'Voyager' reference board in MicroATX form factor.
It uses four in-order AX45MP cores, which is the midrange product
from Andes.
- CIX P1 is one of the few Arm chips designed for small workstations,
and this one uses 12 Cortex-A720/A520 cores, making it also one
of the only ARMv9.2 machines that one can but at the moment.
- Axiado AX3000 is an embedded chip with relative small Cortex-A53
CPU cores described as a "Trusted Control/Compute Unit" that can
be used as a BMC in servers. In addition to the usual I/O, this one
comes with 10GBit ethernet and and a 4TOPS NPU.
- Sophgo SG2000 is an embedded chip that comes with both RISC-V
and Arm cores that can run Linux. This was already supported for
RISC-V but now it also works on Arm
One more chip, the Black Sesame C1200 did not make it in tirm for the
merge window.
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Merge tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull new SoC support from Arnd Bergmann:
"These five newly supported chips come with both devicetree
descriptions and the changes to wire them up to the build system for
easier bisection.
The chips in question are:
- Marvell PXA1908 was the first 64-bit mobile phone chip from Marvell
in the product line that started with the Digital StrongARM SA1100
based PDAs and continued with the Intel PXA2xx that dominated early
smartphones. This one only made it only into a few products before
the entire product line was cut in 2015.
- The QiLai SoC is made by RISC-V core designer Andes Technologies
and is in the 'Voyager' reference board in MicroATX form factor. It
uses four in-order AX45MP cores, which is the midrange product from
Andes.
- CIX P1 is one of the few Arm chips designed for small workstations,
and this one uses 12 Cortex-A720/A520 cores, making it also one of
the only ARMv9.2 machines that one can but at the moment.
- Axiado AX3000 is an embedded chip with relative small Cortex-A53
CPU cores described as a "Trusted Control/Compute Unit" that can be
used as a BMC in servers. In addition to the usual I/O, this one
comes with 10GBit ethernet and and a 4TOPS NPU.
- Sophgo SG2000 is an embedded chip that comes with both RISC-V and
Arm cores that can run Linux. This was already supported for RISC-V
but now it also works on Arm
One more chip, the Black Sesame C1200 did not make it in tirm for the
merge window"
* tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits)
arm64: defconfig: Enable rudimentary Sophgo SG2000 support
arm64: Add SOPHGO SOC family Kconfig support
arm64: dts: sophgo: Add Duo Module 01 Evaluation Board
arm64: dts: sophgo: Add Duo Module 01
arm64: dts: sophgo: Add initial SG2000 SoC device tree
MAINTAINERS: Add entry for Axiado
arm64: defconfig: enable the Axiado family
arm64: dts: axiado: Add initial support for AX3000 SoC and eval board
arm64: add Axiado SoC family
dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller
dt-bindings: serial: cdns: add Axiado AX3000 UART controller
dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant
dt-bindings: gpio: cdns: convert to YAML
dt-bindings: arm: axiado: add AX3000 EVK compatible strings
dt-bindings: vendor-prefixes: Add Axiado Corporation
MAINTAINERS: Add CIX SoC maintainer entry
arm64: dts: cix: Add sky1 base dts initial support
dt-bindings: clock: cix: Add CIX sky1 scmi clock id
arm64: defconfig: Enable CIX SoC
mailbox: add CIX mailbox driver
...
|
||
|
Linus Torvalds
|
115e74a29b |
soc: dt changes for 6.17
There are a few new variants of existing chips:
- mt6572 is an older mobile phone chip from mediatek that was
extremely popular a decade ago but never got upstreamed until now.
- exynos2200 is a recent high-end mobile phone chip used in a
few Samsung phones like the Galaxy S22
- Renesas R-Car V4M-7 (R8A779H2) is an updated version of R-Car V4M
(R8A779H0) and used in automotive applications
- Tegra264 is a new chip from NVIDIA, but support is fairly minimal
for now, and not much information is public about it.
There are five more chips in a separate branch, as those are new
chip families that I merged along with the necessary infrastructure.
New board support is not that exciting, with a total of 33 newly
added machines here:
- Evaluation platforms for the chips above, plus TI am62d2 and
Sophgo sg2042.
- Six 32-bit industrial boards based on stm32, imx6 and am33 chips,
plus eight 64-bit rockchips rk33xx/rk35xx, am62d2, t527, imx8 and
imx95.
- Two newly added ASPEED BMC based motherboards, and one that got
removed
- Phones and Tablets based on 32-bit mt6572, tegra30 and 64-bit
msm8976 SoCs
- Three Laptops based on Mediatek mt8186 and Qualcomm Snapdragon X1
- A set-top box based on Amlogic meson-gxm.
Updates for existing machines are spread over all the above families.
One notable change here is support for the RP1 I/O chip used in
Raspberry Pi 5.
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-----END PGP SIGNATURE-----
Merge tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC devicetree updates from Arnd Bergmann:
"There are a few new variants of existing chips:
- mt6572 is an older mobile phone chip from mediatek that was
extremely popular a decade ago but never got upstreamed until now
- exynos2200 is a recent high-end mobile phone chip used in a few
Samsung phones like the Galaxy S22
- Renesas R-Car V4M-7 (R8A779H2) is an updated version of R-Car V4M
(R8A779H0) and used in automotive applications
- Tegra264 is a new chip from NVIDIA, but support is fairly minimal
for now, and not much information is public about it
There are five more chips in a separate branch, as those are new chip
families that I merged along with the necessary infrastructure.
New board support is not that exciting, with a total of 33 newly added
machines here:
- Evaluation platforms for the chips above, plus TI am62d2 and Sophgo
sg2042
- Six 32-bit industrial boards based on stm32, imx6 and am33 chips,
plus eight 64-bit rockchips rk33xx/rk35xx, am62d2, t527, imx8 and
imx95
- Two newly added ASPEED BMC based motherboards, and one that got
removed
- Phones and Tablets based on 32-bit mt6572, tegra30 and 64-bit
msm8976 SoCs
- Three Laptops based on Mediatek mt8186 and Qualcomm Snapdragon X1
- A set-top box based on Amlogic meson-gxm
Updates for existing machines are spread over all the above families.
One notable change here is support for the RP1 I/O chip used in
Raspberry Pi 5"
* tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (606 commits)
riscv: dts: sophgo: fix mdio node name for CV180X
riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device
riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree
riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree
dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings
riscv: dts: sophgo: add ethernet GMAC device for sg2042
riscv: dts: sophgo: Enable ethernet device for Huashan Pi
riscv: dts: sophgo: Add mdio multiplexer device for cv18xx
riscv: dts: sophgo: Add ethernet device for cv18xx
riscv: dts: sophgo: sg2044: add pmu configuration
riscv: dts: sophgo: sg2044: add ziccrse extension
riscv: dts: sophgo: add zfh for sg2042
riscv: dts: sophgo: add ziccrse for sg2042
riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
riscv: dts: sophgo: sg2044: add PCIe device support for SG2044
riscv: dts: sophgo: sg2044: add MSI device support for SG2044
riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000
riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property
...
|
||
|
Arnd Bergmann
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8113e1dfbc |
RISC-V Misc Devicetrees for v6.17
StarFive: Sort properties on the MilkV Mars and add the power status LED to all jh7110 boards. AMD: Add 64-bit Microblaze V cpu compatible. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCaIDzhAAKCRB4tDGHoIJi 0oNSAQCPRdAfpwl0dAvQHgn0XRQ7H8pY0OmtaC40wHmqerM8uQD9F1aO3xF1H1IH svhfV5mJrHXgn2s9q/yZYBSgm39P6w4= =OCr5 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmiBRL8ACgkQmmx57+YA GNmn7w//S7QJyThD8b9FWXr06EgPDxBoCzXsvRy7XItRTrq2XstrJ3qum7OngGUS 9HWO+6j0PFdgMwXJjupVRI/TcdsmHlNCW8lFp//nKpWkJL7J6aVQry+pGihgBzyt 0QExxfEaywM57bxvl6DMnBYtmUjuQ5Mlj0l0fp5iJuAMIgqWTsseLRyWC0BCw74v Ms0Oy9kDqP9Cf9FThq6hSP3BPALwymKF/Mq1BhMp5DKbPd2Nb3DFbk3oNt2rWkI7 Kol1vlWMytI0doqt30UIaK9XLQ9qbAjdsypQVTkzVj+7eOo8Wu6g4ONbf7UaRwlC SsQtEwBzBWmtTlBjKvcHZIDvbtMWFf9FZ8b/kVrWuD0C/Iow/fIrwwXta2ZCG6d9 6OjZpM9+R/CKElJ1M0FZ9IiAamIl8sCnkS92KE6eTO6os9HAL161l+Oh7PKqEEnw VKN+E4fcrxcRt/kB/yDI2qrlzYLNiVZ7NaaAVsM9pIcNvooHkxM6kLmHfdpceyb5 9FzkaLAeDqL56PUz/6Q/xC7qYtjChd7ODBoZ0r6pGKQzGuEjOQtgDxIkhF/MIbTj Kl8yd0ta2+IcHK3YCiKpGs02dQuv7P+LySmrmW0UPZbE04uTB4n+FUH1DPprPbms H1bSrxmxcaWYSpkbIfCLVRa2ibnveapk2hTl3YO3ksiBWHW38bs= =AHIz -----END PGP SIGNATURE----- Merge tag 'riscv-dt-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Misc Devicetrees for v6.17 StarFive: Sort properties on the MilkV Mars and add the power status LED to all jh7110 boards. AMD: Add 64-bit Microblaze V cpu compatible. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: dt-bindings: riscv: cpus: Add AMD MicroBlaze V 64bit compatible riscv: dts: starfive: jh7110-common: add status power led node riscv: dts: starfive: jh7110-milkv-mars sort properties Link: https://lore.kernel.org/r/20250723-postage-skylight-597377b5f8e4@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
||
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Arnd Bergmann
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11949d263a |
RISC-V Devicetrees for v6.17
Sophgo: For CV18xx serials: There are three major changes. The first is to add the RTCSYS MFD node, which provides rich control registers for soc power management and other rich control functions; the second is to add the reset controller node and add related reset properties for other peripherals; the third is to add ethernet controller related nodes to the soc and enable ethernet device control for HuashanPi. For SG2042: There are three major changes. The first is to add ISA extensions such as xtheadvector/ziccrse/zfh for cpu cores; the second is add ethernet controller support; the third is add two new boards EVB_V1 & EVB_V2 which use SG2042 SoC. For SG2044: There are many changes. The first is to add pmu configuration; the second is to add ISA extensions ziccrse and add missing riscv,cbop-block-size property for cpu cores; the third is to add more peripherals nodes for SoC after clock controller is ready, such as MSI/PCIe/pwm/SPI-NOR etc. This PR also add HWMON MCU device for the sophgo-srd3-10 board and reserve uart0 node for sophgo-srd3-10 board because uart0 is already occupied by the firmware. This PR also moves sophgo.yaml from the riscv directory to soc/sophgo for sharing between riscv and arm. CV18xx SoC contains a RISC-V big core and an ARM64 big core. Moving sophgo.yaml to a shared location will help us add support for ARM cores to the CV18xx chip in the future. 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The first is to add the RTCSYS MFD node, which provides rich control registers for soc power management and other rich control functions; the second is to add the reset controller node and add related reset properties for other peripherals; the third is to add ethernet controller related nodes to the soc and enable ethernet device control for HuashanPi. For SG2042: There are three major changes. The first is to add ISA extensions such as xtheadvector/ziccrse/zfh for cpu cores; the second is add ethernet controller support; the third is add two new boards EVB_V1 & EVB_V2 which use SG2042 SoC. For SG2044: There are many changes. The first is to add pmu configuration; the second is to add ISA extensions ziccrse and add missing riscv,cbop-block-size property for cpu cores; the third is to add more peripherals nodes for SoC after clock controller is ready, such as MSI/PCIe/pwm/SPI-NOR etc. This PR also add HWMON MCU device for the sophgo-srd3-10 board and reserve uart0 node for sophgo-srd3-10 board because uart0 is already occupied by the firmware. This PR also moves sophgo.yaml from the riscv directory to soc/sophgo for sharing between riscv and arm. CV18xx SoC contains a RISC-V big core and an ARM64 big core. Moving sophgo.yaml to a shared location will help us add support for ARM cores to the CV18xx chip in the future. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * tag 'riscv-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux: (32 commits) riscv: dts: sophgo: fix mdio node name for CV180X riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings riscv: dts: sophgo: add ethernet GMAC device for sg2042 riscv: dts: sophgo: Enable ethernet device for Huashan Pi riscv: dts: sophgo: Add mdio multiplexer device for cv18xx riscv: dts: sophgo: Add ethernet device for cv18xx riscv: dts: sophgo: sg2044: add pmu configuration riscv: dts: sophgo: sg2044: add ziccrse extension riscv: dts: sophgo: add zfh for sg2042 riscv: dts: sophgo: add ziccrse for sg2042 riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree riscv: dts: sophgo: sg2044: add PCIe device support for SG2044 riscv: dts: sophgo: sg2044: add MSI device support for SG2044 riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000 riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property ... Link: https://lore.kernel.org/r/MAUPR01MB1107297124C9DA0CD77DA3DC1FE5FA@MAUPR01MB11072.INDPRD01.PROD.OUTLOOK.COM Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Inochi Amaoto
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7f90573099 |
riscv: dts: sophgo: fix mdio node name for CV180X
As the mdio multipledxer is marked as mdio device, the check complains
the mdio bus number exceed the maximum.
Change the node name to mdio-mux to remove the following warnings:
mdio@3009800 (mdio-mux-mmioreg): mdio@80:reg:0:0: 128 is greater than
the maximum of 31
Fixes: b7945143bc33 ("riscv: dts: sophgo: Add mdio multiplexer device for cv18xx")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202507140738.XRjv3G8i-lkp@intel.com/
Closes: https://lore.kernel.org/oe-kbuild-all/202507121830.POx2KDVi-lkp@intel.com/
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250715221349.11034-1-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
|
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Inochi Amaoto
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46683af1fb |
riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device
As the uart0 is already occupied by the firmware, reserve it to avoid this port is used by mistake. Tested-by: Han Gao <rabenda.cn@gmail.com> Reviewed-by: Chen Wang <wangchen20@iscas.ac.cn> Link: https://lore.kernel.org/r/20250703004024.85221-1-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn> |
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Han Gao
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6ea2a06165 |
riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree
Sophgo SG2042_EVB_V2.0 [1] is a prototype development board based on SG2042 Currently supports serial port, sdcard/emmc, pwm, fan speed control. Link: https://github.com/sophgo/sophgo-hardware/tree/master/SG2042/SG2042-x4-EVB [1] Signed-off-by: Han Gao <rabenda.cn@gmail.com> Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com> Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/c1b6ccdc69af0c1457fc1486a6bc8a1e83671537.1751700954.git.rabenda.cn@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn> |
