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linux/arch/riscv/include
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Frederik Haxel 0fbd510985 riscv: Fixed wrong register in XIP_FIXUP_FLASH_OFFSET macro 
[ Upstream commit 5daa372641 ]

During the refactoring, a bug was introduced in the rarly used
XIP_FIXUP_FLASH_OFFSET macro.

Fixes: bee7fbc385 ("RISC-V CPU Idle Support")
Fixes: e7681beba9 ("RISC-V: Split out the XIP fixups into their own file")

Signed-off-by: Frederik Haxel <haxel@fzi.de>
Link: https://lore.kernel.org/r/20231212130116.848530-3-haxel@fzi.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
History 2024-01-25 15:45:19 -08:00
..
asm riscv: Fixed wrong register in XIP_FIXUP_FLASH_OFFSET macro 2024-01-25 15:45:19 -08:00
uapi/asm RISC-V Patches for the 6.7 Merge Window, Part 2 2023-11-10 09:23:17 -08:00