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d8f5840992
The DRAM refresh-interval is getting erroneously set to "1" on exiting from memory self-refreshing mode. The clobbered interval causes the "refresh request overflow timeout" error raised by the External Memory Controller on exiting from LP1 on Tegra30. The same may happen on Tegra20, but EMC registers are not latched after exiting from self-refreshing mode on Tegra20 and hence refresh-interval is not altered until an event that causes registers latching happens. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> |
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Linux kernel
============
There are several guides for kernel developers and users. These guides can
be rendered in a number of formats, like HTML and PDF. Please read
Documentation/admin-guide/README.rst first.
In order to build the documentation, use ``make htmldocs`` or
``make pdfdocs``. The formatted documentation can also be read online at:
https://www.kernel.org/doc/html/latest/
There are various text files in the Documentation/ subdirectory,
several of them using the Restructured Text markup notation.
Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.