ARM: tegra: Fix DRAM refresh-interval clobbering on resume from LP1 on Tegra30

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The DRAM refresh-interval is getting erroneously set to "1" on exiting
from memory self-refreshing mode. The clobbered interval causes the
"refresh request overflow timeout" error raised by the External Memory
Controller on exiting from LP1 on Tegra30. The same may happen on Tegra20,
but EMC registers are not latched after exiting from self-refreshing mode
on Tegra20 and hence refresh-interval is not altered until an event that
causes registers latching happens.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Dmitry Osipenko 2018-11-25 00:13:47 +03:00 • committed by Thierry Reding

parent 82cdfc382b

commit d8f5840992

2 changed files with 0 additions and 4 deletions

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arch/arm/mach-tegra/sleep-tegra20.S

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arch/arm/mach-tegra/sleep-tegra30.S

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