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Nicolin Chen db22b33c7e iommu/tegra241-cmdqv: Read SMMU IDR1.CMDQS instead of hardcoding ... commit e94dc6ddda upstream. The hardware limitation "max=19" actually comes from SMMU Command Queue. So, it'd be more natural for tegra241-cmdqv driver to read it out rather than hardcoding it itself. This is not an issue yet for a kernel on a baremetal system, but a guest kernel setting the queue base/size in form of IPA/gPA might result in a noncontiguous queue in the physical address space, if underlying physical pages backing up the guest RAM aren't contiguous entirely: e.g. 2MB-page backed guest RAM cannot guarantee a contiguous queue if it is 8MB (capped to VCMDQ_LOG2SIZE_MAX=19). This might lead to command errors when HW does linear-read from a noncontiguous queue memory. Adding this extra IDR1.CMDQS cap (in the guest kernel) allows VMM to set SMMU's IDR1.CMDQS=17 for the case mentioned above, so a guest-level queue will be capped to maximum 2MB, ensuring a contiguous queue memory. Fixes: a3799717b8 ("iommu/tegra241-cmdqv: Fix alignment failure at max_n_shift") Reported-by: Ian Kalinowski <ikalinowski@nvidia.com> Cc: stable@vger.kernel.org Signed-off-by: Nicolin Chen <nicolinc@nvidia.com> Link: https://lore.kernel.org/r/20241219051421.1850267-1-nicolinc@nvidia.com Signed-off-by: Will Deacon <will@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		History 2025-02-17 10:05:31 +01:00
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arm-smmu	iommu/arm-smmu-qcom: add sdm670 adreno iommu compatible	2025-02-17 10:04:54 +01:00
arm-smmu-v3	iommu/tegra241-cmdqv: Read SMMU IDR1.CMDQS instead of hardcoding	2025-02-17 10:05:31 +01:00
Makefile	iommu/arm-smmu: Move Arm SMMU drivers into their own subdirectory	2020-07-27 12:53:10 +01:00