| .. |
|
clk-div6.c
|
clk: renesas: div6: Implement range checking
|
2021-05-11 09:58:13 +02:00 |
|
clk-div6.h
|
We have two changes to the core framework this time around. The first being a
|
2017-11-17 20:04:24 -08:00 |
|
clk-emev2.c
|
clk: renesas: emev2: Remove obsolete clkdev registration
|
2023-07-27 14:32:41 +02:00 |
|
clk-mstp.c
|
clk: Use of_property_present()
|
2024-08-02 16:53:38 -07:00 |
|
clk-r8a73a4.c
|
clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT
|
2024-04-25 10:38:19 +02:00 |
|
clk-r8a7740.c
|
clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT
|
2024-04-25 10:38:19 +02:00 |
|
clk-r8a7778.c
|
clk: renesas: r8a7778: Remove struct r8a7778_cpg
|
2022-06-13 11:53:18 +02:00 |
|
clk-r8a7779.c
|
clk: renesas: r8a7779: Remove struct r8a7779_cpg
|
2022-06-13 11:53:18 +02:00 |
|
clk-rz.c
|
clk: renesas: rza1: Remove struct rz_cpg
|
2022-06-13 11:53:18 +02:00 |
|
clk-sh73a0.c
|
clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT
|
2024-04-25 10:38:19 +02:00 |
|
Kconfig
|
clk: renesas: Add RZ/V2H(P) CPG driver
|
2024-08-20 09:48:24 +02:00 |
|
Makefile
|
clk: renesas: Add RZ/V2H(P) CPG driver
|
2024-08-20 09:48:24 +02:00 |
|
r7s9210-cpg-mssr.c
|
clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register
|
2025-12-18 13:54:41 +01:00 |
|
r8a774a1-cpg-mssr.c
|
clk: renesas: rcar-gen3: Add ADG clocks
|
2023-08-15 11:34:43 +02:00 |
|
r8a774b1-cpg-mssr.c
|
clk: renesas: rcar-gen3: Add ADG clocks
|
2023-08-15 11:34:43 +02:00 |
|
r8a774c0-cpg-mssr.c
|
clk: renesas: rcar-gen3: Add ADG clocks
|
2023-08-15 11:34:43 +02:00 |
|
r8a774e1-cpg-mssr.c
|
clk: renesas: rcar-gen3: Add ADG clocks
|
2023-08-15 11:34:43 +02:00 |
|
r8a779a0-cpg-mssr.c
|
clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs
|
2024-07-30 10:44:19 +02:00 |
|
r8a779f0-cpg-mssr.c
|
clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs
|
2024-07-30 10:44:19 +02:00 |
|
r8a779g0-cpg-mssr.c
|
clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs
|
2024-07-30 10:44:19 +02:00 |
|
r8a779h0-cpg-mssr.c
|
clk: renesas: r8a779h0: Add CANFD clock
|
2024-08-20 09:48:24 +02:00 |
|
r8a7742-cpg-mssr.c
|
clk: renesas: r8a7742: Add clk entry for VSPR
|
2020-09-04 09:42:01 +02:00 |
|
r8a7743-cpg-mssr.c
|
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
|
2020-09-04 09:42:01 +02:00 |
|
r8a7745-cpg-mssr.c
|
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
|
2020-09-04 09:42:01 +02:00 |
|
r8a7790-cpg-mssr.c
|
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
|
2020-09-04 09:42:01 +02:00 |
|
r8a7791-cpg-mssr.c
|
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
|
2020-09-04 09:42:01 +02:00 |
|
r8a7792-cpg-mssr.c
|
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
|
2020-09-04 09:42:01 +02:00 |
|
r8a7794-cpg-mssr.c
|
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
|
2020-09-04 09:42:01 +02:00 |
|
r8a7795-cpg-mssr.c
|
clk: renesas: r8a7795: Constify r8a7795_*_clks
|
2023-09-26 09:38:00 +02:00 |
|
r8a7796-cpg-mssr.c
|
clk: renesas: rcar-gen3: Add ADG clocks
|
2023-08-15 11:34:43 +02:00 |
|
r8a77470-cpg-mssr.c
|
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
|
2020-09-04 09:42:01 +02:00 |
|
r8a77965-cpg-mssr.c
|
clk: renesas: rcar-gen3: Add ADG clocks
|
2023-08-15 11:34:43 +02:00 |
|
r8a77970-cpg-mssr.c
|
clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register
|
2025-12-18 13:54:41 +01:00 |
|
r8a77980-cpg-mssr.c
|
clk: renesas: r8a77980: Add I2C5 clock
|
2023-03-30 16:44:04 +02:00 |
|
r8a77990-cpg-mssr.c
|
clk: renesas: rcar-gen3: Add ADG clocks
|
2023-08-15 11:34:43 +02:00 |
|
r8a77995-cpg-mssr.c
|
clk: renesas: rcar-gen3: Add ADG clocks
|
2023-08-15 11:34:43 +02:00 |
|
r9a06g032-clocks.c
|
clk: renesas: r9a06g032: Fix memory leak in error path
|
2025-12-18 13:54:57 +01:00 |
|
r9a07g043-cpg.c
|
clk: renesas: r9a07g043: Fix HP clock source for RZ/Five
|
2025-04-20 10:15:51 +02:00 |
|
r9a07g044-cpg.c
|
clk: renesas: r9a07g044: Mark resets array as const
|
2024-03-26 09:30:44 +01:00 |
|
r9a08g045-cpg.c
|
clk: renesas: r8a08g045: Check the source of the CPU PLL settings
|
2025-04-10 14:39:18 +02:00 |
|
r9a09g011-cpg.c
|
clk: renesas: r9a09g011: Add CSI related clocks
|
2023-07-10 09:31:53 +02:00 |
|
r9a09g057-cpg.c
|
clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT
|
2024-09-02 10:15:38 +02:00 |
|
rcar-cpg-lib.c
|
clk: renesas: cpg-lib: Use DEFINE_SPINLOCK() for global spinlock
|
2024-06-07 14:09:59 +02:00 |
|
rcar-cpg-lib.h
|
clk: renesas: rcar-gen3: Switch to new SD clock handling
|
2021-11-19 11:32:39 +01:00 |
|
rcar-gen2-cpg.c
|
clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register
|
2025-12-18 13:54:41 +01:00 |
|
rcar-gen2-cpg.h
|
clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register
|
2025-12-18 13:54:41 +01:00 |
|
rcar-gen3-cpg.c
|
clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register
|
2025-12-18 13:54:41 +01:00 |
|
rcar-gen3-cpg.h
|
clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register
|
2025-12-18 13:54:41 +01:00 |
|
rcar-gen4-cpg.c
|
clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register
|
2025-12-18 13:54:41 +01:00 |
|
rcar-gen4-cpg.h
|
clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register
|
2025-12-18 13:54:41 +01:00 |
|
rcar-usb2-clock-sel.c
|
clk: Switch back to struct platform_driver::remove()
|
2024-09-21 14:12:05 -07:00 |
|
renesas-cpg-mssr.c
|
clk: renesas: cpg-mssr: Read back reset registers to assure values latched
|
2025-12-18 13:54:41 +01:00 |
|
renesas-cpg-mssr.h
|
clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register
|
2025-12-18 13:54:41 +01:00 |
|
rzg2l-cpg.c
|
clk: renesas: rzg2l: Select correct div round macro
|
2026-03-04 07:21:36 -05:00 |
|
rzg2l-cpg.h
|
clk: renesas: r8a08g045: Check the source of the CPU PLL settings
|
2025-04-10 14:39:18 +02:00 |
|
rzv2h-cpg.c
|
clk: renesas: rzv2h: Fix missing CLK_SET_RATE_PARENT flag for ddiv clocks
|
2025-08-15 12:13:49 +02:00 |
|
rzv2h-cpg.h
|
clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT
|
2024-09-02 10:15:38 +02:00 |
47671671a3