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clk-div6.c
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clk: renesas: div6: Implement range checking
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2021-05-11 09:58:13 +02:00 |
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clk-div6.h
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We have two changes to the core framework this time around. The first being a
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2017-11-17 20:04:24 -08:00 |
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clk-emev2.c
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clk: renesas: emev2: Remove obsolete clkdev registration
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2023-07-27 14:32:41 +02:00 |
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clk-mstp.c
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clk: renesas: mstp: Add genpd OF provider at postcore_initcall()
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2025-08-18 09:36:55 +02:00 |
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clk-r8a73a4.c
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clk: renesas: Remove duplicate and trailing empty lines
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2024-10-01 09:13:38 +02:00 |
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clk-r8a7740.c
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clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT
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2024-04-25 10:38:19 +02:00 |
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clk-r8a7778.c
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clk: renesas: Remove duplicate and trailing empty lines
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2024-10-01 09:13:38 +02:00 |
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clk-r8a7779.c
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clk: renesas: r8a7779: Remove struct r8a7779_cpg
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2022-06-13 11:53:18 +02:00 |
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clk-rz.c
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clk: renesas: rza1: Remove struct rz_cpg
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2022-06-13 11:53:18 +02:00 |
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clk-sh73a0.c
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clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT
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2024-04-25 10:38:19 +02:00 |
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clk-vbattb.c
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clk: renesas: vbattb: Add VBATTB clock driver
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2024-11-06 08:52:45 +01:00 |
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Kconfig
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clk: renesas: Add CPG/MSSR support to RZ/N2H SoC
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2025-06-19 20:19:19 +02:00 |
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Makefile
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clk: renesas: Add CPG/MSSR support to RZ/N2H SoC
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2025-06-19 20:19:19 +02:00 |
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r7s9210-cpg-mssr.c
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clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register
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2025-06-10 10:20:45 +02:00 |
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r8a774a1-cpg-mssr.c
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clk: renesas: rcar-gen3: Add ADG clocks
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2023-08-15 11:34:43 +02:00 |
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r8a774b1-cpg-mssr.c
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clk: renesas: rcar-gen3: Add ADG clocks
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2023-08-15 11:34:43 +02:00 |
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r8a774c0-cpg-mssr.c
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clk: renesas: rcar-gen3: Add ADG clocks
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2023-08-15 11:34:43 +02:00 |
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r8a774e1-cpg-mssr.c
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clk: renesas: rcar-gen3: Add ADG clocks
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2023-08-15 11:34:43 +02:00 |
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r8a779a0-cpg-mssr.c
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clk: renesas: r8a779a0: Add ISP core clocks
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2025-02-03 11:07:05 +01:00 |
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r8a779f0-cpg-mssr.c
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clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs
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2024-07-30 10:44:19 +02:00 |
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r8a779g0-cpg-mssr.c
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clk: renesas: r8a779g0: Add ISP core clocks
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2025-02-03 11:07:05 +01:00 |
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r8a779h0-cpg-mssr.c
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clk: renesas: r8a779h0: Add VSPX clock
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2025-02-03 11:07:06 +01:00 |
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r8a7742-cpg-mssr.c
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clk: renesas: r8a7742: Add clk entry for VSPR
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2020-09-04 09:42:01 +02:00 |
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r8a7743-cpg-mssr.c
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clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
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2020-09-04 09:42:01 +02:00 |
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r8a7745-cpg-mssr.c
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clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
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2020-09-04 09:42:01 +02:00 |
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r8a7790-cpg-mssr.c
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clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
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2020-09-04 09:42:01 +02:00 |
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r8a7791-cpg-mssr.c
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clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
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2020-09-04 09:42:01 +02:00 |
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r8a7792-cpg-mssr.c
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clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
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2020-09-04 09:42:01 +02:00 |
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r8a7794-cpg-mssr.c
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clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
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2020-09-04 09:42:01 +02:00 |
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r8a7795-cpg-mssr.c
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clk: renesas: r8a7795: Constify r8a7795_*_clks
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2023-09-26 09:38:00 +02:00 |
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r8a7796-cpg-mssr.c
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clk: renesas: rcar-gen3: Add ADG clocks
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2023-08-15 11:34:43 +02:00 |
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r8a77470-cpg-mssr.c
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clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
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2020-09-04 09:42:01 +02:00 |
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r8a77965-cpg-mssr.c
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clk: renesas: rcar-gen3: Add ADG clocks
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2023-08-15 11:34:43 +02:00 |
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r8a77970-cpg-mssr.c
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clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register
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2025-06-10 10:20:45 +02:00 |
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r8a77980-cpg-mssr.c
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clk: renesas: r8a77980: Add I2C5 clock
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2023-03-30 16:44:04 +02:00 |
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r8a77990-cpg-mssr.c
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clk: renesas: rcar-gen3: Add ADG clocks
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2023-08-15 11:34:43 +02:00 |
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r8a77995-cpg-mssr.c
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clk: renesas: rcar-gen3: Add ADG clocks
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2023-08-15 11:34:43 +02:00 |
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r9a06g032-clocks.c
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clk: renesas: r9a06g032: Use BIT macro consistently
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2024-12-10 12:00:30 +01:00 |
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r9a07g043-cpg.c
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clk: renesas: r9a07g04[34]: Use tabs instead of spaces
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2025-08-20 09:16:32 +02:00 |
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r9a07g044-cpg.c
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clk: renesas: r9a07g04[34]: Use tabs instead of spaces
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2025-08-20 09:16:32 +02:00 |
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r9a08g045-cpg.c
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clk: renesas: r9a08g045: Add MSTOP for GPIO
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2025-08-20 09:16:31 +02:00 |
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r9a09g011-cpg.c
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clk: renesas: rzg2l: Add support for MSTOP in clock enable/disable API
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2025-06-10 10:24:17 +02:00 |
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r9a09g047-cpg.c
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clk: renesas: r9a09g047: Add USB3.0 clocks/resets
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2025-09-12 09:53:37 +02:00 |
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r9a09g056-cpg.c
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clk: renesas: r9a09g05[67]: Reduce differences
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2025-09-12 09:53:37 +02:00 |
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r9a09g057-cpg.c
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clk: renesas: r9a09g05[67]: Reduce differences
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2025-09-12 09:53:37 +02:00 |
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r9a09g077-cpg.c
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clk: renesas: r9a09g077: Add Ethernet Subsystem core and module clocks
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2025-09-04 11:33:10 +02:00 |
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rcar-cpg-lib.c
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clk: renesas: Remove duplicate and trailing empty lines
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2024-10-01 09:13:38 +02:00 |
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rcar-cpg-lib.h
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clk: renesas: rcar-gen3: Switch to new SD clock handling
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2021-11-19 11:32:39 +01:00 |
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rcar-gen2-cpg.c
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clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register
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2025-06-10 10:20:45 +02:00 |
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rcar-gen2-cpg.h
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clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register
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2025-06-10 10:20:45 +02:00 |
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rcar-gen3-cpg.c
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clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register
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2025-06-10 10:20:45 +02:00 |
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rcar-gen3-cpg.h
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clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register
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2025-06-10 10:20:45 +02:00 |
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rcar-gen4-cpg.c
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clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register
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2025-06-10 10:20:45 +02:00 |
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rcar-gen4-cpg.h
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clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register
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2025-06-10 10:20:45 +02:00 |
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rcar-usb2-clock-sel.c
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clk: Switch back to struct platform_driver::remove()
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2024-09-21 14:12:05 -07:00 |
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renesas-cpg-mssr.c
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clk: renesas: cpg-mssr: Fix memory leak in cpg_mssr_reserved_init()
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2025-09-12 09:52:47 +02:00 |
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renesas-cpg-mssr.h
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clk: renesas: Add support for R9A09G077 SoC
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2025-06-10 10:24:17 +02:00 |
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rzg2l-cpg.c
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clk: renesas: rzg2l: Re-assert reset on deassert timeout
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2025-09-04 11:29:31 +02:00 |
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rzg2l-cpg.h
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clk: renesas: r9a07g044: Add MSTOP for RZ/G2L
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2025-08-20 09:16:32 +02:00 |
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rzv2h-cpg.c
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clk: renesas: rzv2h: Simplify polling condition in __rzv2h_cpg_assert()
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2025-09-04 11:30:01 +02:00 |
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rzv2h-cpg.h
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clk: renesas: r9a09g056: Add XSPI clock/reset
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2025-07-02 20:53:35 +02:00 |
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