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linux/arch/riscv/include
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Nam Cao 3f0605239f riscv: correct riscv_insn_is_c_jr() and riscv_insn_is_c_jalr() 
[ Upstream commit 79bc3f85c5 ]

The instructions c.jr and c.jalr must have rs1 != 0, but
riscv_insn_is_c_jr() and riscv_insn_is_c_jalr() do not check for this. So,
riscv_insn_is_c_jr() can match a reserved encoding, while
riscv_insn_is_c_jalr() can match the c.ebreak instruction.

Rewrite them with check for rs1 != 0.

Signed-off-by: Nam Cao <namcaov@gmail.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Fixes: ec5f908775 ("RISC-V: Move riscv_insn_is_* macros into a common header")
Link: https://lore.kernel.org/r/20230731183925.152145-1-namcaov@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
History 2023-08-23 17:32:51 +02:00
..
asm riscv: correct riscv_insn_is_c_jr() and riscv_insn_is_c_jalr() 2023-08-23 17:32:51 +02:00
uapi/asm KVM/riscv changes for 6.4 2023-05-05 06:11:48 -04:00