linux/arch/riscv/errata
Yong-Xuan Wang 148ab873d8 RISC-V: errata: Add SiFive MAL-9092 workaround
SiFive cores with MAL-9092 require fence.rw instructions around
HLV/HLVX/HSV hypervisor instructions to ensure proper memory ordering
when accessing guest memory.

Note that HSTATUS.HU is cleared during KVM initialization, restricting
hypervisor instructions to HS-mode only. If future changes enable
HSTATUS.HU for U-mode access, additional errata considerations will be
needed.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Link: https://patch.msgid.link/20260817-sifive-errata-v1-1-6a80f1a2743d@sifive.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
History 2026-10-05 19:02:38 -06:00
..
andes asm-generic: introduce text-patching.h 2024-11-07 14:25:15 -08:00
mips riscv: errata: Fix bitwise vs logical AND in MIPS errata patching 2026-04-30 20:00:14 -06:00
sifive RISC-V: errata: Add SiFive MAL-9092 workaround 2026-10-05 19:02:38 -06:00
thead riscv: fix various typos in comments and code 2026-04-04 18:42:39 -06:00
Makefile riscv: errata: Fix the PAUSE Opcode for MIPS P8700 2025-09-19 10:33:56 -06:00